DE69831460D1 - Schaltungsentwurfprüfung - Google Patents

Schaltungsentwurfprüfung

Info

Publication number
DE69831460D1
DE69831460D1 DE69831460T DE69831460T DE69831460D1 DE 69831460 D1 DE69831460 D1 DE 69831460D1 DE 69831460 T DE69831460 T DE 69831460T DE 69831460 T DE69831460 T DE 69831460T DE 69831460 D1 DE69831460 D1 DE 69831460D1
Authority
DE
Germany
Prior art keywords
circuit design
design review
review
circuit
design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69831460T
Other languages
English (en)
Other versions
DE69831460T2 (de
Inventor
Brian Michael Dowling
James David Rodeo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69831460D1 publication Critical patent/DE69831460D1/de
Application granted granted Critical
Publication of DE69831460T2 publication Critical patent/DE69831460T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
DE69831460T 1997-10-02 1998-10-02 Schaltungsentwurfprüfung Expired - Fee Related DE69831460T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/943,085 US6099579A (en) 1997-10-02 1997-10-02 Method and apparatus for checking asynchronous HDL circuit designs
US943085 1997-10-02

Publications (2)

Publication Number Publication Date
DE69831460D1 true DE69831460D1 (de) 2005-10-13
DE69831460T2 DE69831460T2 (de) 2006-08-24

Family

ID=25479078

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69831460T Expired - Fee Related DE69831460T2 (de) 1997-10-02 1998-10-02 Schaltungsentwurfprüfung

Country Status (3)

Country Link
US (1) US6099579A (de)
EP (1) EP0907133B1 (de)
DE (1) DE69831460T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6879948B1 (en) * 1999-12-14 2005-04-12 Silicon Graphics, Inc. Synchronization of hardware simulation processes
KR100375828B1 (ko) * 2000-11-10 2003-03-15 한국전자통신연구원 아이피 인터페이스 파형의 흐름도 변환에 의한브이에이치디엘 코드 생성 방법
US6567961B2 (en) * 2000-12-13 2003-05-20 International Business Machines Corporation Method for detecting lack of synchronism in VLSI designs during high level simulation
US7269811B1 (en) * 2003-01-10 2007-09-11 Xilinx, Inc. Method of and apparatus for specifying clock domains in electronic circuit designs
US7412678B2 (en) * 2004-06-02 2008-08-12 Lsi Corporation Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design
US20060190754A1 (en) * 2005-02-24 2006-08-24 Atrenta, Inc. A Method for Automatic Recognition of Handshake Data Exchange at Clock-Domain Crossing in Integrated Circuit Design
US8065647B2 (en) * 2007-10-19 2011-11-22 The University Of Utah Research Foundation Method and system for asynchronous chip design
JP5445358B2 (ja) * 2010-07-02 2014-03-19 富士通株式会社 検証支援プログラム、検証支援装置および検証支援方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530841A (en) * 1990-12-21 1996-06-25 Synopsys, Inc. Method for converting a hardware independent user description of a logic circuit into hardware components
US5664181A (en) * 1992-03-17 1997-09-02 International Business Machines Corporation Computer program product and program storage device for a data transmission dictionary for encoding, storing, and retrieving hierarchical data processing information for a computer system
US5392227A (en) * 1992-07-24 1995-02-21 Logic Modeling Corporation System and method for generating electronic circuit simulation models having improved accuracy
US5426591A (en) * 1994-01-28 1995-06-20 Vlsi Technology, Inc. Apparatus and method for improving the timing performance of a circuit
US5854926A (en) * 1995-01-23 1998-12-29 Vlsi Technology, Inc. Method and apparatus for identifying flip-flops in HDL descriptions of circuits without specific templates
US5650938A (en) * 1995-12-13 1997-07-22 Synopsys, Inc. Method and apparatus for verifying asynchronous circuits using static timing analysis and dynamic functional simulation
US5864487A (en) * 1996-11-19 1999-01-26 Unisys Corporation Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool

Also Published As

Publication number Publication date
EP0907133A2 (de) 1999-04-07
EP0907133A3 (de) 2000-05-10
DE69831460T2 (de) 2006-08-24
EP0907133B1 (de) 2005-09-07
US6099579A (en) 2000-08-08

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., HOUSTON

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee