DE69836117D1 - Stabilisierung von Titanpolyzid mittels einer porösen Sperrschicht - Google Patents

Stabilisierung von Titanpolyzid mittels einer porösen Sperrschicht

Info

Publication number
DE69836117D1
DE69836117D1 DE69836117T DE69836117T DE69836117D1 DE 69836117 D1 DE69836117 D1 DE 69836117D1 DE 69836117 T DE69836117 T DE 69836117T DE 69836117 T DE69836117 T DE 69836117T DE 69836117 D1 DE69836117 D1 DE 69836117D1
Authority
DE
Germany
Prior art keywords
stabilization
barrier layer
porous barrier
titanium polycide
polycide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69836117T
Other languages
English (en)
Other versions
DE69836117T2 (de
Inventor
Atul C Ajmera
Christine Dehm
Anthony G Domenicucci
George G Gifford
Stephen K Loh
Christopher Parks
Viraji Y Sardesai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
International Business Machines Corp
Original Assignee
Siemens AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, International Business Machines Corp filed Critical Siemens AG
Publication of DE69836117D1 publication Critical patent/DE69836117D1/de
Application granted granted Critical
Publication of DE69836117T2 publication Critical patent/DE69836117T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
DE69836117T 1997-09-23 1998-07-28 Stabilisierung von Titanpolyzid mittels einer porösen Sperrschicht Expired - Lifetime DE69836117T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/936,029 US6057220A (en) 1997-09-23 1997-09-23 Titanium polycide stabilization with a porous barrier
US936029 1997-09-23

Publications (2)

Publication Number Publication Date
DE69836117D1 true DE69836117D1 (de) 2006-11-23
DE69836117T2 DE69836117T2 (de) 2007-04-19

Family

ID=25468076

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69836117T Expired - Lifetime DE69836117T2 (de) 1997-09-23 1998-07-28 Stabilisierung von Titanpolyzid mittels einer porösen Sperrschicht

Country Status (4)

Country Link
US (1) US6057220A (de)
EP (1) EP0903776B1 (de)
JP (1) JP3103063B2 (de)
DE (1) DE69836117T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5998253A (en) * 1997-09-29 1999-12-07 Siemens Aktiengesellschaft Method of forming a dopant outdiffusion control structure including selectively grown silicon nitride in a trench capacitor of a DRAM cell
TW437010B (en) * 1998-09-08 2001-05-28 Siemens Ag A layer-arrangement with a material-layer and a diffusion-barrier against diffusable material-components
US6759315B1 (en) * 1999-01-04 2004-07-06 International Business Machines Corporation Method for selective trimming of gate structures and apparatus formed thereby
US6319784B1 (en) * 1999-05-26 2001-11-20 Taiwan Semiconductor Manufacturing Company Using high temperature H2 anneal to recrystallize S/D and remove native oxide simultaneously
US6380040B1 (en) 1999-08-02 2002-04-30 Advanced Micro Devices, Inc. Prevention of dopant out-diffusion during silicidation and junction formation
US6649543B1 (en) 2000-06-22 2003-11-18 Micron Technology, Inc. Methods of forming silicon nitride, methods of forming transistor devices, and transistor devices
US6686298B1 (en) * 2000-06-22 2004-02-03 Micron Technology, Inc. Methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates
US6833329B1 (en) * 2000-06-22 2004-12-21 Micron Technology, Inc. Methods of forming oxide regions over semiconductor substrates
US6660657B1 (en) * 2000-08-07 2003-12-09 Micron Technology, Inc. Methods of incorporating nitrogen into silicon-oxide-containing layers
US6878585B2 (en) 2001-08-29 2005-04-12 Micron Technology, Inc. Methods of forming capacitors
US6723599B2 (en) * 2001-12-03 2004-04-20 Micron Technology, Inc. Methods of forming capacitors and methods of forming capacitor dielectric layers
KR100802252B1 (ko) * 2001-12-26 2008-02-11 주식회사 하이닉스반도체 반도체 소자의 금속 배선 형성방법
TWI287826B (en) * 2005-06-30 2007-10-01 Chunghwa Picture Tubes Ltd Method of forming thin film transistor and method of repairing defects in polysilicon layer

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931411A (en) * 1985-05-01 1990-06-05 Texas Instruments Incorporated Integrated circuit process with TiN-gate transistor
US4690730A (en) * 1986-03-07 1987-09-01 Texas Instruments Incorporated Oxide-capped titanium silicide formation
US4784973A (en) * 1987-08-24 1988-11-15 Inmos Corporation Semiconductor contact silicide/nitride process with control for silicide thickness
EP0456318B1 (de) * 1990-05-11 2001-08-22 Koninklijke Philips Electronics N.V. CMOS-Verfahren mit Verwendung von zeitweilig angebrachten Siliciumnitrid-Spacern zum Herstellen von Transistoren (LDD) mit leicht dotiertem Drain
US5536947A (en) * 1991-01-18 1996-07-16 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom
JPH04290224A (ja) * 1991-03-19 1992-10-14 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
KR960011861B1 (ko) * 1993-06-10 1996-09-03 삼성전자 주식회사 반도체장치의 소자 분리 방법
JP3045946B2 (ja) * 1994-05-09 2000-05-29 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイスの製造方法
US5518958A (en) * 1994-07-29 1996-05-21 International Business Machines Corporation Prevention of agglomeration and inversion in a semiconductor polycide process
US5585300A (en) * 1994-08-01 1996-12-17 Texas Instruments Incorporated Method of making conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes
US5543362A (en) * 1995-03-28 1996-08-06 Motorola, Inc. Process for fabricating refractory-metal silicide layers in a semiconductor device
US5545574A (en) * 1995-05-19 1996-08-13 Motorola, Inc. Process for forming a semiconductor device having a metal-semiconductor compound
FR2742924B1 (fr) * 1995-12-22 1998-03-20 Jorge Luis Regolini Procede de depot selectif d'un siliciure de metal refractaire sur du silicium et plaquette de silicium metallisee par ce procede
US5874351A (en) * 1996-06-13 1999-02-23 Micron Tecnology, Inc. Sputtered metal silicide film stress control by grain boundary stuffing
US5739064A (en) * 1996-11-27 1998-04-14 Micron Technology, Inc. Second implanted matrix for agglomeration control and thermal stability
US5998253A (en) * 1997-09-29 1999-12-07 Siemens Aktiengesellschaft Method of forming a dopant outdiffusion control structure including selectively grown silicon nitride in a trench capacitor of a DRAM cell

Also Published As

Publication number Publication date
US6057220A (en) 2000-05-02
EP0903776B1 (de) 2006-10-11
JP3103063B2 (ja) 2000-10-23
EP0903776A3 (de) 1999-08-11
EP0903776A2 (de) 1999-03-24
JPH11135454A (ja) 1999-05-21
DE69836117T2 (de) 2007-04-19

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