DE69837674D1 - Doppeldamaszen-metallisierung - Google Patents

Doppeldamaszen-metallisierung

Info

Publication number
DE69837674D1
DE69837674D1 DE69837674T DE69837674T DE69837674D1 DE 69837674 D1 DE69837674 D1 DE 69837674D1 DE 69837674 T DE69837674 T DE 69837674T DE 69837674 T DE69837674 T DE 69837674T DE 69837674 D1 DE69837674 D1 DE 69837674D1
Authority
DE
Germany
Prior art keywords
metallisation
dual damascene
damascene
dual
damascene metallisation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69837674T
Other languages
English (en)
Other versions
DE69837674T2 (de
Inventor
Liang-Yuh Chen
Rong Tao
Ted Guo
Roderick Craig Mosely
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Application granted granted Critical
Publication of DE69837674D1 publication Critical patent/DE69837674D1/de
Publication of DE69837674T2 publication Critical patent/DE69837674T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
DE69837674T 1997-08-19 1998-08-17 Doppeldamaszen-metallisierung Expired - Fee Related DE69837674T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US914521 1997-08-19
US08/914,521 US5989623A (en) 1997-08-19 1997-08-19 Dual damascene metallization
PCT/US1998/017010 WO1999009593A1 (en) 1997-08-19 1998-08-17 Dual damascene metallization

Publications (2)

Publication Number Publication Date
DE69837674D1 true DE69837674D1 (de) 2007-06-06
DE69837674T2 DE69837674T2 (de) 2008-01-10

Family

ID=25434472

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69837674T Expired - Fee Related DE69837674T2 (de) 1997-08-19 1998-08-17 Doppeldamaszen-metallisierung

Country Status (6)

Country Link
US (2) US5989623A (de)
EP (1) EP1021827B1 (de)
JP (1) JP4615707B2 (de)
KR (1) KR100506139B1 (de)
DE (1) DE69837674T2 (de)
WO (1) WO1999009593A1 (de)

Families Citing this family (123)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475903B1 (en) * 1993-12-28 2002-11-05 Intel Corporation Copper reflow process
US6100196A (en) * 1996-04-08 2000-08-08 Chartered Semiconductor Manufacturing Ltd. Method of making a copper interconnect with top barrier layer
US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
US6731007B1 (en) * 1997-08-29 2004-05-04 Hitachi, Ltd. Semiconductor integrated circuit device with vertically stacked conductor interconnections
US6307267B1 (en) * 1997-12-26 2001-10-23 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US6140234A (en) * 1998-01-20 2000-10-31 International Business Machines Corporation Method to selectively fill recesses with conductive metal
WO1999040615A1 (en) 1998-02-04 1999-08-12 Semitool, Inc. Method and apparatus for low-temperature annealing of metallization micro-structures in the production of a microelectronic device
US7244677B2 (en) 1998-02-04 2007-07-17 Semitool. Inc. Method for filling recessed micro-structures with metallization in the production of a microelectronic device
US6025264A (en) * 1998-02-09 2000-02-15 United Microelectronics Corp. Fabricating method of a barrier layer
US6150706A (en) 1998-02-27 2000-11-21 Micron Technology, Inc. Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer
US6682970B1 (en) * 1998-02-27 2004-01-27 Micron Technology, Inc. Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer
US7034353B2 (en) * 1998-02-27 2006-04-25 Micron Technology, Inc. Methods for enhancing capacitors having roughened features to increase charge-storage capacity
JP3149846B2 (ja) * 1998-04-17 2001-03-26 日本電気株式会社 半導体装置及びその製造方法
EP1091024A4 (de) * 1998-04-30 2006-03-22 Ebara Corp Verfahren und vorrichtung zum beschichten von substraten
US6433428B1 (en) * 1998-05-29 2002-08-13 Kabushiki Kaisha Toshiba Semiconductor device with a dual damascene type via contact structure and method for the manufacture of same
US6475912B1 (en) * 1998-06-01 2002-11-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield
US6355562B1 (en) 1998-07-01 2002-03-12 Advanced Technology Materials, Inc. Adhesion promotion method for CVD copper metallization in IC applications
KR100265772B1 (ko) * 1998-07-22 2000-10-02 윤종용 반도체 장치의 배선구조 및 그 제조방법
JP3244058B2 (ja) * 1998-07-28 2002-01-07 日本電気株式会社 半導体装置の製造方法
US6093623A (en) * 1998-08-04 2000-07-25 Micron Technology, Inc. Methods for making silicon-on-insulator structures
US6284656B1 (en) 1998-08-04 2001-09-04 Micron Technology, Inc. Copper metallurgy in integrated circuits
JP2000068230A (ja) * 1998-08-25 2000-03-03 Mitsubishi Electric Corp 半導体装置、その製造装置、および、その製造方法
US6380083B1 (en) * 1998-08-28 2002-04-30 Agere Systems Guardian Corp. Process for semiconductor device fabrication having copper interconnects
JP3187011B2 (ja) * 1998-08-31 2001-07-11 日本電気株式会社 半導体装置の製造方法
US6288442B1 (en) * 1998-09-10 2001-09-11 Micron Technology, Inc. Integrated circuit with oxidation-resistant polymeric layer
US5994778A (en) * 1998-09-18 1999-11-30 Advanced Micro Devices, Inc. Surface treatment of low-k SiOF to prevent metal interaction
JP3180779B2 (ja) * 1998-10-05 2001-06-25 日本電気株式会社 半導体装置の製造方法
US6153528A (en) * 1998-10-14 2000-11-28 United Silicon Incorporated Method of fabricating a dual damascene structure
US6080663A (en) * 1998-11-13 2000-06-27 United Microelectronics Corp. Dual damascene
US6184137B1 (en) * 1998-11-25 2001-02-06 Applied Materials, Inc. Structure and method for improving low temperature copper reflow in semiconductor features
US6207568B1 (en) * 1998-11-27 2001-03-27 Taiwan Semiconductor Manufacturing Company Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer
US6596637B1 (en) * 1998-12-07 2003-07-22 Advanced Micro Devices, Inc. Chemically preventing Cu dendrite formation and growth by immersion
US6162728A (en) * 1998-12-18 2000-12-19 Texas Instruments Incorporated Method to optimize copper chemical-mechanical polishing in a copper damascene interconnect process for integrated circuit applications
US6288449B1 (en) 1998-12-22 2001-09-11 Agere Systems Guardian Corp. Barrier for copper metallization
KR100280288B1 (ko) 1999-02-04 2001-01-15 윤종용 반도체 집적회로의 커패시터 제조방법
SG90054A1 (en) * 1999-02-11 2002-07-23 Chartered Semiconductor Mfg A new process of dual damascene structure
US20020127845A1 (en) * 1999-03-01 2002-09-12 Paul A. Farrar Conductive structures in integrated circuits
KR100460746B1 (ko) * 1999-04-13 2004-12-09 주식회사 하이닉스반도체 반도체 소자의 구리 금속 배선 형성 방법
US6103624A (en) * 1999-04-15 2000-08-15 Advanced Micro Devices, Inc. Method of improving Cu damascene interconnect reliability by laser anneal before barrier polish
US6303496B1 (en) * 1999-04-27 2001-10-16 Cypress Semiconductor Corporation Methods of filling constrained spaces with insulating materials and/or of forming contact holes and/or contacts in an integrated circuit
US6251772B1 (en) * 1999-04-29 2001-06-26 Advanced Micro Devicees, Inc. Dielectric adhesion enhancement in damascene process for semiconductors
KR100333712B1 (ko) * 1999-06-24 2002-04-24 박종섭 반도체 소자의 상감형 금속배선 형성방법
US6251770B1 (en) * 1999-06-30 2001-06-26 Lam Research Corp. Dual-damascene dielectric structures and methods for making the same
EP1212788B1 (de) 1999-08-26 2014-06-11 Brewer Science Verbessertes füllmaterial für ein dual-damaszene-verfahren
US20040034134A1 (en) * 1999-08-26 2004-02-19 Lamb James E. Crosslinkable fill compositions for uniformly protecting via and contact holes
US6326297B1 (en) * 1999-09-30 2001-12-04 Novellus Systems, Inc. Method of making a tungsten nitride barrier layer with improved adhesion and stability using a silicon layer
US6423200B1 (en) * 1999-09-30 2002-07-23 Lam Research Corporation Copper interconnect seed layer treatment methods and apparatuses for treating the same
WO2001029891A1 (en) * 1999-10-15 2001-04-26 Asm America, Inc. Conformal lining layers for damascene metallization
US6361880B1 (en) * 1999-12-22 2002-03-26 International Business Machines Corporation CVD/PVD/CVD/PVD fill process
KR100338112B1 (ko) * 1999-12-22 2002-05-24 박종섭 반도체 소자의 구리 금속 배선 형성 방법
US6420262B1 (en) 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US7211512B1 (en) * 2000-01-18 2007-05-01 Micron Technology, Inc. Selective electroless-plated copper metallization
US6376370B1 (en) 2000-01-18 2002-04-23 Micron Technology, Inc. Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy
US7262130B1 (en) 2000-01-18 2007-08-28 Micron Technology, Inc. Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
US6355555B1 (en) 2000-01-28 2002-03-12 Advanced Micro Devices, Inc. Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer
US6303486B1 (en) 2000-01-28 2001-10-16 Advanced Micro Devices, Inc. Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer and an unconstrained copper anneal
US6573030B1 (en) 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
DE10008572B4 (de) * 2000-02-24 2007-08-09 Infineon Technologies Ag Verbindungseinrichtung für Leistungshalbleitermodule
US6384448B1 (en) * 2000-02-28 2002-05-07 Micron Technology, Inc. P-channel dynamic flash memory cells with ultrathin tunnel oxides
US6639835B2 (en) 2000-02-29 2003-10-28 Micron Technology, Inc. Static NVRAM with ultra thin tunnel oxides
US6486063B2 (en) * 2000-03-02 2002-11-26 Tokyo Electron Limited Semiconductor device manufacturing method for a copper connection
US6344125B1 (en) * 2000-04-06 2002-02-05 International Business Machines Corporation Pattern-sensitive electrolytic metal plating
US6674167B1 (en) * 2000-05-31 2004-01-06 Micron Technology, Inc. Multilevel copper interconnect with double passivation
US6423629B1 (en) * 2000-05-31 2002-07-23 Kie Y. Ahn Multilevel copper interconnects with low-k dielectrics and air gaps
US6258709B1 (en) 2000-06-07 2001-07-10 Micron Technology, Inc. Formation of electrical interconnect lines by selective metal etch
US6525425B1 (en) * 2000-06-14 2003-02-25 Advanced Micro Devices, Inc. Copper interconnects with improved electromigration resistance and low resistivity
US6346479B1 (en) 2000-06-14 2002-02-12 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device having copper interconnects
US6548395B1 (en) * 2000-11-16 2003-04-15 Advanced Micro Devices, Inc. Method of promoting void free copper interconnects
US6776893B1 (en) 2000-11-20 2004-08-17 Enthone Inc. Electroplating chemistry for the CU filling of submicron features of VLSI/ULSI interconnect
US7270724B2 (en) 2000-12-13 2007-09-18 Uvtech Systems, Inc. Scanning plasma reactor
KR100364260B1 (ko) * 2001-01-05 2002-12-11 삼성전자 주식회사 반도체 집적 회로의 제조 방법
US6773683B2 (en) 2001-01-08 2004-08-10 Uvtech Systems, Inc. Photocatalytic reactor system for treating flue effluents
US6383920B1 (en) 2001-01-10 2002-05-07 International Business Machines Corporation Process of enclosing via for improved reliability in dual damascene interconnects
KR100379551B1 (ko) * 2001-03-09 2003-04-10 주식회사 하이닉스반도체 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법
US7224063B2 (en) 2001-06-01 2007-05-29 International Business Machines Corporation Dual-damascene metallization interconnection
US20020192944A1 (en) * 2001-06-13 2002-12-19 Sonderman Thomas J. Method and apparatus for controlling a thickness of a copper film
US6849545B2 (en) * 2001-06-20 2005-02-01 Applied Materials, Inc. System and method to form a composite film stack utilizing sequential deposition techniques
US20030008243A1 (en) * 2001-07-09 2003-01-09 Micron Technology, Inc. Copper electroless deposition technology for ULSI metalization
US6692830B2 (en) * 2001-07-31 2004-02-17 Flex Products, Inc. Diffractive pigment flakes and compositions
US6607976B2 (en) 2001-09-25 2003-08-19 Applied Materials, Inc. Copper interconnect barrier layer structure and formation method
US6873027B2 (en) 2001-10-26 2005-03-29 International Business Machines Corporation Encapsulated energy-dissipative fuse for integrated circuits and method of making the same
KR100453957B1 (ko) * 2001-12-20 2004-10-20 동부전자 주식회사 듀얼 다마신을 이용한 전원 배선 제조 방법
US6620635B2 (en) 2002-02-20 2003-09-16 International Business Machines Corporation Damascene resistor and method for measuring the width of same
US6624515B1 (en) * 2002-03-11 2003-09-23 Micron Technology, Inc. Microelectronic die including low RC under-layer interconnects
US6541397B1 (en) 2002-03-29 2003-04-01 Applied Materials, Inc. Removable amorphous carbon CMP stop
US6518185B1 (en) * 2002-04-22 2003-02-11 Advanced Micro Devices, Inc. Integration scheme for non-feature-size dependent cu-alloy introduction
US6656840B2 (en) 2002-04-29 2003-12-02 Applied Materials Inc. Method for forming silicon containing layers on a substrate
US6620724B1 (en) * 2002-05-09 2003-09-16 Infineon Technologies Ag Low resistivity deep trench fill for DRAM and EDRAM applications
US6649513B1 (en) 2002-05-15 2003-11-18 Taiwan Semiconductor Manufacturing Company Copper back-end-of-line by electropolish
KR100456259B1 (ko) * 2002-07-15 2004-11-09 주식회사 하이닉스반도체 반도체 소자의 구리 배선 형성방법
US7030042B2 (en) 2002-08-28 2006-04-18 Micron Technology, Inc. Systems and methods for forming tantalum oxide layers and tantalum precursor compounds
US6784049B2 (en) * 2002-08-28 2004-08-31 Micron Technology, Inc. Method for forming refractory metal oxide layers with tetramethyldisiloxane
US6709970B1 (en) * 2002-09-03 2004-03-23 Samsung Electronics Co., Ltd. Method for creating a damascene interconnect using a two-step electroplating process
US6919639B2 (en) * 2002-10-15 2005-07-19 The Board Of Regents, The University Of Texas System Multiple copper vias for integrated circuit metallization and methods of fabricating same
US6980395B2 (en) * 2002-10-31 2005-12-27 International Business Machines Corporation Enhanced coplanar conductance structure for inductive heads
US20040108217A1 (en) * 2002-12-05 2004-06-10 Dubin Valery M. Methods for forming copper interconnect structures by co-plating of noble metals and structures formed thereby
US7273808B1 (en) 2003-02-03 2007-09-25 Novellus Systems, Inc. Reactive barrier/seed preclean process for damascene process
KR100576363B1 (ko) * 2003-05-30 2006-05-03 삼성전자주식회사 인시투 화학기상증착 금속 공정 및 그에 사용되는화학기상증착 장비
JP2005039142A (ja) * 2003-07-18 2005-02-10 Nec Electronics Corp 半導体装置の製造方法
US7220665B2 (en) 2003-08-05 2007-05-22 Micron Technology, Inc. H2 plasma treatment
US7026244B2 (en) * 2003-08-08 2006-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Low resistance and reliable copper interconnects by variable doping
US7064068B2 (en) * 2004-01-23 2006-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method to improve planarity of electroplated copper
KR100613283B1 (ko) 2004-12-27 2006-08-21 동부일렉트로닉스 주식회사 반도체 소자의 배선 형성방법
CN1983550A (zh) * 2005-12-14 2007-06-20 中芯国际集成电路制造(上海)有限公司 提高可靠性和成品率的消除铜位错的方法
US20070281456A1 (en) * 2006-05-30 2007-12-06 Hynix Semiconductor Inc. Method of forming line of semiconductor device
KR100750950B1 (ko) * 2006-07-18 2007-08-22 삼성전자주식회사 반도체 장치의 배선 구조물 및 그 형성 방법, 비휘발성메모리 장치 및 그 제조 방법
WO2008084524A1 (ja) * 2007-01-09 2008-07-17 Fujitsu Microelectronics Limited 半導体装置の製造方法、および半導体装置の製造装置
KR20090053991A (ko) * 2007-11-26 2009-05-29 주식회사 동부하이텍 반도체 소자의 제조방법
US20090168247A1 (en) * 2007-12-28 2009-07-02 Christian Rene Bonhote Magnetic head with embedded solder connection and method for manufacture thereof
US8252653B2 (en) * 2008-10-21 2012-08-28 Applied Materials, Inc. Method of forming a non-volatile memory having a silicon nitride charge trap layer
US8198671B2 (en) * 2009-04-22 2012-06-12 Applied Materials, Inc. Modification of charge trap silicon nitride with oxygen plasma
US8575000B2 (en) * 2011-07-19 2013-11-05 SanDisk Technologies, Inc. Copper interconnects separated by air gaps and method of making thereof
CN102332425A (zh) * 2011-09-23 2012-01-25 复旦大学 一种提升铜互连技术中抗电迁移特性的方法
US8796853B2 (en) 2012-02-24 2014-08-05 International Business Machines Corporation Metallic capped interconnect structure with high electromigration resistance and low resistivity
US8802558B2 (en) * 2012-11-07 2014-08-12 International Business Machines Corporation Copper interconnect structures and methods of making same
US8999767B2 (en) 2013-01-31 2015-04-07 International Business Machines Corporation Electronic fuse having an insulation layer
EP2779224A3 (de) * 2013-03-15 2014-12-31 Applied Materials, Inc. Verfahren zur Herstellung von Verbindungen in Halbleitervorrichtungen
JP6385856B2 (ja) * 2015-02-26 2018-09-05 東京エレクトロン株式会社 Cu配線の形成方法および半導体装置の製造方法
US20160276156A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing process thereof
US9704804B1 (en) * 2015-12-18 2017-07-11 Texas Instruments Incorporated Oxidation resistant barrier metal process for semiconductor devices
US11664271B2 (en) 2019-05-02 2023-05-30 International Business Machines Corporation Dual damascene with short liner
CN112825307B (zh) * 2019-11-21 2022-04-29 中芯国际集成电路制造(上海)有限公司 一种互连结构的形成方法及互连结构
CN113363204B (zh) * 2020-03-05 2022-04-12 中芯国际集成电路制造(深圳)有限公司 一种互连结构的形成方法

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010032A (en) * 1985-05-01 1991-04-23 Texas Instruments Incorporated Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects
JPS639925A (ja) * 1986-06-30 1988-01-16 Nec Corp 半導体装置の製造方法
JPS6373660A (ja) * 1986-09-17 1988-04-04 Fujitsu Ltd 半導体装置
US4960732A (en) * 1987-02-19 1990-10-02 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
JPS63229814A (ja) * 1987-03-19 1988-09-26 Nec Corp 半導体集積回路の製造方法
US4994410A (en) * 1988-04-04 1991-02-19 Motorola, Inc. Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process
US4938996A (en) * 1988-04-12 1990-07-03 Ziv Alan R Via filling by selective laser chemical vapor deposition
US4920072A (en) * 1988-10-31 1990-04-24 Texas Instruments Incorporated Method of forming metal interconnects
US4920073A (en) * 1989-05-11 1990-04-24 Texas Instruments, Incorporated Selective silicidation process using a titanium nitride protective layer
JPH038359A (ja) * 1989-06-06 1991-01-16 Fujitsu Ltd 半導体装置の製造方法
US5091339A (en) * 1990-07-23 1992-02-25 Microelectronics And Computer Technology Corporation Trenching techniques for forming vias and channels in multilayer electrical interconnects
US5250465A (en) * 1991-01-28 1993-10-05 Fujitsu Limited Method of manufacturing semiconductor devices
JP2533414B2 (ja) * 1991-04-09 1996-09-11 三菱電機株式会社 半導体集積回路装置の配線接続構造およびその製造方法
US5292558A (en) * 1991-08-08 1994-03-08 University Of Texas At Austin, Texas Process for metal deposition for microelectronic interconnections
JPH05206064A (ja) * 1991-12-10 1993-08-13 Nec Corp 半導体装置の製造方法
US5262354A (en) * 1992-02-26 1993-11-16 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
CA2082771C (en) * 1992-11-12 1998-02-10 Vu Quoc Ho Method for forming interconnect structures for integrated circuits
US5439731A (en) * 1994-03-11 1995-08-08 Cornell Research Goundation, Inc. Interconnect structures containing blocked segments to minimize stress migration and electromigration damage
KR0144956B1 (ko) * 1994-06-10 1998-08-17 김광호 반도체 장치의 배선 구조 및 그 형성방법
JPH0810693A (ja) * 1994-06-30 1996-01-16 Dainippon Screen Mfg Co Ltd レジスト膜の乾燥方法及び装置
US5521119A (en) * 1994-07-13 1996-05-28 Taiwan Semiconductor Manufacturing Co. Post treatment of tungsten etching back
JPH08181141A (ja) * 1994-12-21 1996-07-12 Yamaha Corp 配線形成法
DE69533823D1 (de) * 1994-12-29 2005-01-05 St Microelectronics Inc Elektrische Verbindungsstruktur auf einer integrierten Schaltungsanordnung mit einem Zapfen mit vergrössertem Kopf
KR100413890B1 (ko) * 1995-03-02 2004-03-19 동경 엘렉트론 주식회사 반도체장치의제조방법및제조장치
JP3266492B2 (ja) * 1995-03-02 2002-03-18 川崎マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP2728025B2 (ja) * 1995-04-13 1998-03-18 日本電気株式会社 半導体装置の製造方法
US5877087A (en) * 1995-11-21 1999-03-02 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
US5824599A (en) * 1996-01-16 1998-10-20 Cornell Research Foundation, Inc. Protected encapsulation of catalytic layer for electroless copper interconnect
US5895266A (en) * 1996-02-26 1999-04-20 Applied Materials, Inc. Titanium nitride barrier layers
US5814557A (en) * 1996-05-20 1998-09-29 Motorola, Inc. Method of forming an interconnect structure
US5693563A (en) * 1996-07-15 1997-12-02 Chartered Semiconductor Manufacturing Pte Ltd. Etch stop for copper damascene process
JP3261317B2 (ja) * 1996-08-30 2002-02-25 株式会社アルバック 銅配線製造方法、及び銅配線
JP3281816B2 (ja) * 1996-09-02 2002-05-13 株式会社アルバック 銅配線製造方法
WO1998027585A1 (en) * 1996-12-16 1998-06-25 International Business Machines Corporation Electroplated interconnection structures on integrated circuit chips
US5933753A (en) * 1996-12-16 1999-08-03 International Business Machines Corporation Open-bottomed via liner structure and method for fabricating same
KR100243272B1 (ko) * 1996-12-20 2000-03-02 윤종용 반도체 소자의 콘택 플러그 형성방법
US5858873A (en) * 1997-03-12 1999-01-12 Lucent Technologies Inc. Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof
US5930669A (en) * 1997-04-03 1999-07-27 International Business Machines Corporation Continuous highly conductive metal wiring structures and method for fabricating the same
JP3390329B2 (ja) * 1997-06-27 2003-03-24 日本電気株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US6207222B1 (en) 2001-03-27
KR100506139B1 (ko) 2005-08-05
EP1021827A1 (de) 2000-07-26
US5989623A (en) 1999-11-23
DE69837674T2 (de) 2008-01-10
JP2001516146A (ja) 2001-09-25
WO1999009593A1 (en) 1999-02-25
KR20010023055A (ko) 2001-03-26
EP1021827B1 (de) 2007-04-25
JP4615707B2 (ja) 2011-01-19

Similar Documents

Publication Publication Date Title
DE69837674D1 (de) Doppeldamaszen-metallisierung
DE69822740D1 (de) Verbinder
DE69704309T2 (de) Verbinder
DE69705170T2 (de) Verbinder
DE69819057D1 (de) Verbinder
BR9708471A (pt) Misturas lcp
DE69937218D1 (de) Verbinder
DE69834906D1 (de) Verbinder
DE69802367T2 (de) Plattierungsverfahren
EE200100339A (et) Kombineeritud kemoteraapia
DE69829560D1 (de) Verbinder
DE69920833D1 (de) Verbinder
DE69823611D1 (de) Verbinder
DE69838828D1 (de) Verbinder
DE69808820D1 (de) Geschirrspülmaschine
DE69839595D1 (de) Geschirrspüler
DE69705463D1 (de) Verbinder
DE69808562D1 (de) Verbinder
DE29722975U1 (de) Geschirrspülmaschine
DE19980732D2 (de) Dosierspender
DE59810662D1 (de) Koaxialverbinder
DE29619590U1 (de) Waschbecken
DE29716322U1 (de) Arbeitsplatte
DE19881798D2 (de) Waschtisch
DE29706333U1 (de) Ausgießer

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee