DE69841838D1 - Bitleitungsanordnung für DRAM - Google Patents

Bitleitungsanordnung für DRAM

Info

Publication number: DE69841838D1
Authority: DE; Germany
Prior art keywords: dram; bit line; line arrangement; arrangement; bit
Prior art date: 1997-06-30
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE69841838T

Other languages

English (en)

Inventor

Heinz Hoenigschmid

John Debrosse

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Infineon Technologies AG

International Business Machines Corp

Original Assignee

Infineon Technologies AG

International Business Machines Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1997-06-30

Filing date

1998-06-29

Publication date

2010-09-30

1998-06-29 Application filed by Infineon Technologies AG, International Business Machines Corp filed Critical Infineon Technologies AG

2010-09-30 Application granted granted Critical

2010-09-30 Publication of DE69841838D1 publication Critical patent/DE69841838D1/de

2018-06-30 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Links

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/905—Plural dram cells share common contact or common trench
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/907—Folded bit line dram configuration

DE69841838T 1997-06-30 1998-06-29 Bitleitungsanordnung für DRAM Expired - Lifetime DE69841838D1 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US08/884,853 US5821592A (en)	1997-06-30	1997-06-30	Dynamic random access memory arrays and methods therefor

Publications (1)

Publication Number	Publication Date
DE69841838D1 true DE69841838D1 (de)	2010-09-30

Family

ID=25385564

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69841838T Expired - Lifetime DE69841838D1 (de)	1997-06-30	1998-06-29	Bitleitungsanordnung für DRAM

Country Status (6)

Country	Link
US (1)	US5821592A (de)
EP (1)	EP0889528B1 (de)
JP (1)	JPH1187641A (de)
KR (1)	KR100570108B1 (de)
DE (1)	DE69841838D1 (de)
TW (1)	TW396608B (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH10144886A (ja) *	1996-09-11	1998-05-29	Toshiba Corp	半導体装置及びその製造方法
US6018480A (en) *	1998-04-08	2000-01-25	Lsi Logic Corporation	Method and system which permits logic signal routing over on-chip memories
US6326695B1 (en) *	1998-09-29	2001-12-04	Texas Instruments Incorporated	Twisted bit line structures and method for making same
JP2000228509A (ja) *	1999-02-05	2000-08-15	Fujitsu Ltd	半導体装置
DE19907176A1 (de) *	1999-02-19	2000-08-31	Siemens Ag	Decoder-Anschlußanordnung für Speicherchips mit langen Bitleitungen
DE19908428C2 (de) *	1999-02-26	2000-12-07	Siemens Ag	Halbleiterspeicheranordnung mit Bitleitungs-Twist
JP2001035941A (ja) *	1999-07-23	2001-02-09	Nec Corp	半導体記憶装置及びその製造方法
US6320780B1 (en) *	1999-09-28	2001-11-20	Infineon Technologies North America Corp.	Reduced impact from coupling noise in diagonal bitline architectures
US6282113B1 (en)	1999-09-29	2001-08-28	International Business Machines Corporation	Four F-squared gapless dual layer bitline DRAM array architecture
DE19948571A1 (de)	1999-10-08	2001-04-19	Infineon Technologies Ag	Speicheranordnung
US6504246B2 (en)	1999-10-12	2003-01-07	Motorola, Inc.	Integrated circuit having a balanced twist for differential signal lines
US7184290B1 (en) *	2000-06-28	2007-02-27	Marvell International Ltd.	Logic process DRAM
US6711044B2 (en) *	2001-07-02	2004-03-23	Matsushita Electric Industrial Co., Ltd.	Semiconductor memory device with a countermeasure to a signal delay
US7084413B2 (en) *	2002-08-08	2006-08-01	Micron Technology, Inc.	Photolithographic techniques for producing angled lines
JP2004158802A (ja)	2002-11-08	2004-06-03	Renesas Technology Corp	半導体記憶装置
KR100615575B1 (ko) *	2004-09-10	2006-08-25	삼성전자주식회사	반도체 메모리 장치 및 이 장치의 배치 방법
US20080035956A1 (en) *	2006-08-14	2008-02-14	Micron Technology, Inc.	Memory device with non-orthogonal word and bit lines
EP2015362A1 (de) *	2007-06-04	2009-01-14	STMicroelectronics (Crolles 2) SAS	Halbleitermatrix und deren Herstellungsverfahren
US20100044093A1 (en) *	2008-08-25	2010-02-25	Wilinx Corporation	Layout geometries for differential signals
JP2014225566A (ja) *	2013-05-16	2014-12-04	ピーエスフォールクスコエスエイアールエルＰＳ４ＬｕｘｃｏＳ．ａ．ｒ．ｌ．	半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH03278573A (ja) *	1990-03-28	1991-12-10	Mitsubishi Electric Corp	半導体記憶装置
US5107459A (en) *	1990-04-20	1992-04-21	International Business Machines Corporation	Stacked bit-line architecture for high density cross-point memory cell array
JPH0494569A (ja) *	1990-08-10	1992-03-26	Matsushita Electric Ind Co Ltd	半導体集積回路装置
KR950011636B1 (ko) *	1992-03-04	1995-10-07	금성일렉트론주식회사	개선된 레이아웃을 갖는 다이내믹 랜덤 액세스 메모리와 그것의 메모리셀 배치방법
JP3241106B2 (ja) *	1992-07-17	2001-12-25	株式会社東芝	ダイナミック型半導体記憶装置及びその製造方法
KR100285823B1 (ko) *	1992-08-10	2001-04-16	칼 하인쯔 호르닝어	디램 셀 장치
KR100215595B1 (ko) *	1993-09-21	1999-08-16	니시무로 타이죠	다이나믹형 반도체 기억장치

1997
- 1997-06-30 US US08/884,853 patent/US5821592A/en not_active Expired - Lifetime
1998
- 1998-06-15 TW TW087109459A patent/TW396608B/zh not_active IP Right Cessation
- 1998-06-22 KR KR1019980023340A patent/KR100570108B1/ko not_active IP Right Cessation
- 1998-06-29 DE DE69841838T patent/DE69841838D1/de not_active Expired - Lifetime
- 1998-06-29 EP EP98305124A patent/EP0889528B1/de not_active Expired - Lifetime
- 1998-06-30 JP JP10184054A patent/JPH1187641A/ja active Pending

Also Published As

Publication number	Publication date
JPH1187641A (ja)	1999-03-30
TW396608B (en)	2000-07-01
EP0889528B1 (de)	2010-08-18
EP0889528A2 (de)	1999-01-07
KR19990007194A (ko)	1999-01-25
EP0889528A3 (de)	2002-01-16
KR100570108B1 (ko)	2006-06-21
US5821592A (en)	1998-10-13

Publication	Publication Date	Title
DE69841838D1 (de)	2010-09-30	Bitleitungsanordnung für DRAM
DE69915704D1 (de)	2004-04-22	Ampic dram
DE69825458D1 (de)	2004-09-09	Speicheranordnung für wafer
DE69721891D1 (de)	2003-06-18	Deterministisches Kohärenzprotokoll für verteilten Multicache-Speicher
DE69933493D1 (de)	2006-11-23	Zugriffsstruktur für hochintegrierten Festwertspeicher
DE69941994D1 (de)	2010-03-25	Speicherverwaltung für Navigationssystem
DE69912572D1 (de)	2003-12-11	Ablageeinheit für ausgegebene Bögen
DE69822290D1 (de)	2004-04-15	Verbesserte reiniger für schneckenbohrer
DE60003426D1 (de)	2003-07-24	Statusbits für cachespeicher
DE69839380D1 (de)	2008-06-05	Ladeeinrichtung für Drehmaschinen
DE59814358D1 (de)	2009-05-14	Einbauten für stoffaustauschkolonnen
DE69529800D1 (de)	2003-04-10	Schlüsselbartstruktur für Kraftfahrzeug
DE69808755T2 (de)	2003-08-14	Vorprodukt für cvd
DE59808419D1 (de)	2003-06-26	Steckverbindung für Rohrleitungen
DE29515127U1 (de)	1995-11-23	Bohranordnung für Decken
DE29800782U1 (de)	1998-03-26	Vorratsbox für Kleinteile
DE29617559U1 (de)	1997-03-27	Steckverbindung für Rohre
DE59705907D1 (de)	2002-01-31	Wertscheinbehälter für wertscheinausgabeeinheit
DE69833901D1 (de)	2006-05-11	Verbesserte Aufbewahrungsstruktur für Speichermedium
DE69738971D1 (de)	2008-10-23	Wortleitungsanordnung für Halbleiter-Speicherbauteil
DE29819593U1 (de)	1999-01-14	Trennwand-Anordnung für Büroräume
DE29809340U1 (de)	1998-08-20	Verschlußstopfen für Rohre
DE29612094U1 (de)	1997-11-06	Aufbewahrungsvorrichtung für Werkzeugeinsätze
DE59908399D1 (de)	2004-03-04	Datenspeicher für Fahrzeuge
DE29706172U1 (de)	1997-05-28	Schachtel für Werkzeuge