DE69924475D1 - Multikanal-DMA mit Datenverkehrplanung auf die Ausgänge - Google Patents

Multikanal-DMA mit Datenverkehrplanung auf die Ausgänge

Info

Publication number
DE69924475D1
DE69924475D1 DE69924475T DE69924475T DE69924475D1 DE 69924475 D1 DE69924475 D1 DE 69924475D1 DE 69924475 T DE69924475 T DE 69924475T DE 69924475 T DE69924475 T DE 69924475T DE 69924475 D1 DE69924475 D1 DE 69924475D1
Authority
DE
Germany
Prior art keywords
outputs
traffic planning
channel dma
dma
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69924475T
Other languages
English (en)
Other versions
DE69924475T2 (de
Inventor
Laurent Six
Daniel Mozzocco
Armelle Laine
Gerald Ollivier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69924475D1 publication Critical patent/DE69924475D1/de
Application granted granted Critical
Publication of DE69924475T2 publication Critical patent/DE69924475T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
DE69924475T 1999-06-09 1999-06-09 Multikanal-DMA mit Datenverkehrplanung auf die Ausgänge Expired - Lifetime DE69924475T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP99401389A EP1059589B1 (de) 1999-06-09 1999-06-09 Multikanal-DMA mit Datenverkehrplanung auf die Ausgänge

Publications (2)

Publication Number Publication Date
DE69924475D1 true DE69924475D1 (de) 2005-05-04
DE69924475T2 DE69924475T2 (de) 2006-02-16

Family

ID=8242004

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69924475T Expired - Lifetime DE69924475T2 (de) 1999-06-09 1999-06-09 Multikanal-DMA mit Datenverkehrplanung auf die Ausgänge

Country Status (3)

Country Link
US (1) US6738881B1 (de)
EP (1) EP1059589B1 (de)
DE (1) DE69924475T2 (de)

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CN113687625A (zh) * 2021-10-26 2021-11-23 菲尼克斯(南京)智能制造技术工程有限公司 一种模拟量通道类型可配置的电路模块

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US9141572B2 (en) * 2006-12-15 2015-09-22 Microchip Technology Incorporated Direct memory access controller
US20080240324A1 (en) * 2007-03-27 2008-10-02 Microsoft Corporation Independent Dispatch of Multiple Streaming Queues Via Reserved Time Slots
US7917671B2 (en) * 2007-12-18 2011-03-29 Nvidia Corporation Scalable port controller architecture supporting data streams of different speeds
US8571834B2 (en) * 2010-01-08 2013-10-29 International Business Machines Corporation Opcode counting for performance measurement
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US8631213B2 (en) 2010-09-16 2014-01-14 Apple Inc. Dynamic QoS upgrading
KR101706201B1 (ko) * 2010-12-15 2017-02-15 한국전자통신연구원 다이렉트 메모리 액세스 컨트롤러 및 그것의 동작 방법
US9003369B2 (en) 2011-08-31 2015-04-07 Nvidia Corporation HDMI-muxed debug port methods and apparatuses
US8943238B2 (en) * 2012-05-18 2015-01-27 Atmel Corporation Operations using direct memory access
US9053058B2 (en) 2012-12-20 2015-06-09 Apple Inc. QoS inband upgrade
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US10025748B2 (en) * 2013-09-27 2018-07-17 Intel Corporation Lane division multiplexing of an I/O link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113687625A (zh) * 2021-10-26 2021-11-23 菲尼克斯(南京)智能制造技术工程有限公司 一种模拟量通道类型可配置的电路模块

Also Published As

Publication number Publication date
EP1059589A1 (de) 2000-12-13
EP1059589B1 (de) 2005-03-30
US6738881B1 (en) 2004-05-18
DE69924475T2 (de) 2006-02-16

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