DE69924486D1 - Spezielle schnittstellenarchitektur für eine hybride schaltung - Google Patents
Spezielle schnittstellenarchitektur für eine hybride schaltungInfo
- Publication number
- DE69924486D1 DE69924486D1 DE69924486T DE69924486T DE69924486D1 DE 69924486 D1 DE69924486 D1 DE 69924486D1 DE 69924486 T DE69924486 T DE 69924486T DE 69924486 T DE69924486 T DE 69924486T DE 69924486 D1 DE69924486 D1 DE 69924486D1
- Authority
- DE
- Germany
- Prior art keywords
- special interface
- interface architecture
- hybrid switching
- hybrid
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US69054 | 1998-04-28 | ||
| US09/069,054 US7389487B1 (en) | 1998-04-28 | 1998-04-28 | Dedicated interface architecture for a hybrid integrated circuit |
| PCT/US1999/007484 WO1999056394A1 (en) | 1998-04-28 | 1999-04-05 | Dedicated interface architecture for a hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69924486D1 true DE69924486D1 (de) | 2005-05-04 |
| DE69924486T2 DE69924486T2 (de) | 2006-02-16 |
Family
ID=22086436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69924486T Expired - Lifetime DE69924486T2 (de) | 1998-04-28 | 1999-04-05 | Spezielle schnittstellenarchitektur für eine hybride schaltung |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US7389487B1 (de) |
| EP (1) | EP1080531B1 (de) |
| DE (1) | DE69924486T2 (de) |
| WO (1) | WO1999056394A1 (de) |
Families Citing this family (46)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7389487B1 (en) | 1998-04-28 | 2008-06-17 | Actel Corporation | Dedicated interface architecture for a hybrid integrated circuit |
| US6333641B1 (en) | 1999-05-07 | 2001-12-25 | Morphics Technology, Inc. | Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array |
| DE60023882T2 (de) | 1999-05-07 | 2006-07-20 | Infineon Technologies Ag | System auf einem Chip mit reprogrammierbarem Testgerät, Fehlerbeseitiger und Busüberwachung |
| EP1177631B1 (de) | 1999-05-07 | 2005-12-28 | Infineon Technologies AG | Heterogenes programmierbares gatterfeld |
| US6769109B2 (en) | 2000-02-25 | 2004-07-27 | Lightspeed Semiconductor Corporation | Programmable logic array embedded in mask-programmed ASIC |
| US6694491B1 (en) * | 2000-02-25 | 2004-02-17 | Lightspeed Semiconductor Corporation | Programmable logic array embedded in mask-programmed ASIC |
| US7055125B2 (en) | 2000-09-08 | 2006-05-30 | Lightspeed Semiconductor Corp. | Depopulated programmable logic array |
| US6628140B2 (en) | 2000-09-18 | 2003-09-30 | Altera Corporation | Programmable logic devices with function-specific blocks |
| US6605962B2 (en) * | 2001-05-06 | 2003-08-12 | Altera Corporation | PLD architecture for flexible placement of IP function blocks |
| US7921323B2 (en) * | 2004-05-11 | 2011-04-05 | L-3 Communications Integrated Systems, L.P. | Reconfigurable communications infrastructure for ASIC networks |
| US8018248B2 (en) * | 2006-09-21 | 2011-09-13 | Quicklogic Corporation | Adjustable interface buffer circuit between a programmable logic device and a dedicated device |
| US7930336B2 (en) | 2006-12-05 | 2011-04-19 | Altera Corporation | Large multiplier for programmable logic device |
| US8386553B1 (en) | 2006-12-05 | 2013-02-26 | Altera Corporation | Large multiplier for programmable logic device |
| US9564902B2 (en) | 2007-04-17 | 2017-02-07 | Cypress Semiconductor Corporation | Dynamically configurable and re-configurable data path |
| US7737724B2 (en) * | 2007-04-17 | 2010-06-15 | Cypress Semiconductor Corporation | Universal digital block interconnection and channel routing |
| US8026739B2 (en) | 2007-04-17 | 2011-09-27 | Cypress Semiconductor Corporation | System level interconnect with programmable switching |
| US8516025B2 (en) | 2007-04-17 | 2013-08-20 | Cypress Semiconductor Corporation | Clock driven dynamic datapath chaining |
| US8111577B2 (en) | 2007-04-17 | 2012-02-07 | Cypress Semiconductor Corporation | System comprising a state-monitoring memory element |
| US7761690B2 (en) * | 2007-07-26 | 2010-07-20 | International Business Machines Corporation | Method, apparatus and computer program product for dynamically selecting compiled instructions |
| US7724032B2 (en) * | 2007-08-20 | 2010-05-25 | Altera Corporation | Field programmable gate array with integrated application specific integrated circuit fabric |
| US7865862B2 (en) * | 2007-11-08 | 2011-01-04 | International Business Machines Corporation | Design structure for dynamically selecting compiled instructions |
| US8959137B1 (en) | 2008-02-20 | 2015-02-17 | Altera Corporation | Implementing large multipliers in a programmable integrated circuit device |
| US8244789B1 (en) | 2008-03-14 | 2012-08-14 | Altera Corporation | Normalization of floating point operations in a programmable integrated circuit device |
| US8886696B1 (en) | 2009-03-03 | 2014-11-11 | Altera Corporation | Digital signal processing circuitry with redundancy and ability to support larger multipliers |
| US20100277201A1 (en) * | 2009-05-01 | 2010-11-04 | Curt Wortman | Embedded digital ip strip chip |
| US8397054B2 (en) * | 2009-12-23 | 2013-03-12 | L-3 Communications Integrated Systems L.P. | Multi-phased computational reconfiguration |
| US8368423B2 (en) * | 2009-12-23 | 2013-02-05 | L-3 Communications Integrated Systems, L.P. | Heterogeneous computer architecture based on partial reconfiguration |
| DE102010003521A1 (de) * | 2010-03-31 | 2011-10-06 | Robert Bosch Gmbh | Modulare Struktur zur Datenverarbeitung |
| EP2372490A1 (de) * | 2010-03-31 | 2011-10-05 | Robert Bosch GmbH | Schaltungsanordnung für ein Datenverarbeitungssystem und Verfahren zur Datenverarbeitung |
| US8862650B2 (en) | 2010-06-25 | 2014-10-14 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
| US8686753B1 (en) * | 2011-04-08 | 2014-04-01 | Altera Corporation | Partial reconfiguration and in-system debugging |
| US9600278B1 (en) | 2011-05-09 | 2017-03-21 | Altera Corporation | Programmable device using fixed and configurable logic to implement recursive trees |
| CN103534692B (zh) | 2011-05-17 | 2016-10-19 | 阿尔特拉公司 | 对接混合集成器件中的硬逻辑和软逻辑的系统和方法 |
| EP2710479B1 (de) * | 2011-05-17 | 2017-11-15 | Altera Corporation | Systeme und verfahren für schnittstellen zwischen harter und weicher logik in einer integrierten hybridvorrichtung |
| US8949298B1 (en) | 2011-09-16 | 2015-02-03 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
| US9053045B1 (en) | 2011-09-16 | 2015-06-09 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
| US9098332B1 (en) | 2012-06-01 | 2015-08-04 | Altera Corporation | Specialized processing block with fixed- and floating-point structures |
| US8996600B1 (en) | 2012-08-03 | 2015-03-31 | Altera Corporation | Specialized processing block for implementing floating-point multiplier with subnormal operation support |
| US9207909B1 (en) | 2012-11-26 | 2015-12-08 | Altera Corporation | Polynomial calculations optimized for programmable integrated circuit device structures |
| US9189200B1 (en) | 2013-03-14 | 2015-11-17 | Altera Corporation | Multiple-precision processing block in a programmable integrated circuit device |
| US9348795B1 (en) | 2013-07-03 | 2016-05-24 | Altera Corporation | Programmable device using fixed and configurable logic to implement floating-point rounding |
| US9379687B1 (en) | 2014-01-14 | 2016-06-28 | Altera Corporation | Pipelined systolic finite impulse response filter |
| US9214045B1 (en) | 2014-08-29 | 2015-12-15 | Freescale Semiconductor, Inc. | Flash memory express erase and program |
| US9684488B2 (en) | 2015-03-26 | 2017-06-20 | Altera Corporation | Combined adder and pre-adder for high-radix multiplier circuit |
| US10970119B2 (en) * | 2017-03-28 | 2021-04-06 | Intel Corporation | Technologies for hybrid field-programmable gate array application-specific integrated circuit code acceleration |
| US10942706B2 (en) | 2017-05-05 | 2021-03-09 | Intel Corporation | Implementation of floating-point trigonometric functions in an integrated circuit device |
Family Cites Families (88)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3473160A (en) | 1966-10-10 | 1969-10-14 | Stanford Research Inst | Electronically controlled microelectronic cellular logic array |
| US4433331A (en) | 1981-12-14 | 1984-02-21 | Bell Telephone Laboratories, Incorporated | Programmable logic array interconnection matrix |
| US4700088A (en) | 1983-08-05 | 1987-10-13 | Texas Instruments Incorporated | Dummy load controlled multilevel logic single clock logic circuit |
| US4870302A (en) | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
| US4642487A (en) | 1984-09-26 | 1987-02-10 | Xilinx, Inc. | Special interconnect for configurable logic array |
| US5225719A (en) | 1985-03-29 | 1993-07-06 | Advanced Micro Devices, Inc. | Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix |
| US5367208A (en) | 1986-09-19 | 1994-11-22 | Actel Corporation | Reconfigurable programmable interconnect architecture |
| US5015885A (en) | 1986-09-19 | 1991-05-14 | Actel Corporation | Reconfigurable programmable interconnect architecture |
| US5451887A (en) | 1986-09-19 | 1995-09-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
| US5187393A (en) | 1986-09-19 | 1993-02-16 | Actel Corporation | Reconfigurable programmable interconnect architecture |
| US4758745B1 (en) * | 1986-09-19 | 1994-11-15 | Actel Corp | User programmable integrated circuit interconnect architecture and test method |
| US5083083A (en) | 1986-09-19 | 1992-01-21 | Actel Corporation | Testability architecture and techniques for programmable interconnect architecture |
| US5172014A (en) | 1986-09-19 | 1992-12-15 | Actel Corporation | Programmable interconnect architecture |
| US4969121A (en) | 1987-03-02 | 1990-11-06 | Altera Corporation | Programmable integrated circuit logic array device having improved microprocessor connectability |
| JPH0254576A (ja) | 1988-08-18 | 1990-02-23 | Mitsubishi Electric Corp | ゲートアレイ |
| US5452231A (en) * | 1988-10-05 | 1995-09-19 | Quickturn Design Systems, Inc. | Hierarchically connected reconfigurable logic assembly |
| US4930097A (en) | 1988-12-30 | 1990-05-29 | Intel Corporation | Architecture for an improved performance of a programmable logic device |
| US5212652A (en) | 1989-08-15 | 1993-05-18 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure |
| US5400262A (en) | 1989-09-20 | 1995-03-21 | Aptix Corporation | Universal interconnect matrix array |
| DE4008791A1 (de) | 1990-03-19 | 1991-09-26 | Slt Lining Technology Gmbh | Anordnung zur abdeckung geneigter schuettstoffflaechen |
| US5198705A (en) | 1990-05-11 | 1993-03-30 | Actel Corporation | Logic module with configurable combinational and sequential blocks |
| US5073729A (en) | 1990-06-22 | 1991-12-17 | Actel Corporation | Segmented routing architecture |
| US5191241A (en) | 1990-08-01 | 1993-03-02 | Actel Corporation | Programmable interconnect architecture |
| DE69133311T2 (de) | 1990-10-15 | 2004-06-24 | Aptix Corp., San Jose | Verbindungssubstrat mit integrierter Schaltung zur programmierbaren Verbindung und Probenuntersuchung |
| US5224056A (en) * | 1991-10-30 | 1993-06-29 | Xilinx, Inc. | Logic placement using positionally asymmetrical partitioning algorithm |
| US5107146A (en) | 1991-02-13 | 1992-04-21 | Actel Corporation | Mixed mode analog/digital programmable interconnect architecture |
| US5313119A (en) | 1991-03-18 | 1994-05-17 | Crosspoint Solutions, Inc. | Field programmable gate array |
| US5187392A (en) | 1991-07-31 | 1993-02-16 | Intel Corporation | Programmable logic device with limited signal swing |
| US5317209A (en) | 1991-08-29 | 1994-05-31 | National Semiconductor Corporation | Dynamic three-state bussing capability in a configurable logic array |
| US5883850A (en) * | 1991-09-03 | 1999-03-16 | Altera Corporation | Programmable logic array integrated circuits |
| US5550782A (en) | 1991-09-03 | 1996-08-27 | Altera Corporation | Programmable logic array integrated circuits |
| JPH05252025A (ja) * | 1991-10-28 | 1993-09-28 | Texas Instr Inc <Ti> | 論理モジュールおよび集積回路 |
| JPH07502377A (ja) | 1991-12-18 | 1995-03-09 | クロスポイント・ソルーションズ・インコーポレイテッド | フィールドプログラマブルゲートアレイのための拡張アーキテクチャ |
| US5208491A (en) | 1992-01-07 | 1993-05-04 | Washington Research Foundation | Field programmable gate array |
| US5475830A (en) * | 1992-01-31 | 1995-12-12 | Quickturn Design Systems, Inc. | Structure and method for providing a reconfigurable emulation circuit without hold time violations |
| US5347181A (en) * | 1992-04-29 | 1994-09-13 | Motorola, Inc. | Interface control logic for embedding a microprocessor in a gate array |
| US5646547A (en) | 1994-04-28 | 1997-07-08 | Xilinx, Inc. | Logic cell which can be configured as a latch without static one's problem |
| US5317698A (en) | 1992-08-18 | 1994-05-31 | Actel Corporation | FPGA architecture including direct logic function circuit to I/O interconnections |
| GB9223226D0 (en) | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
| US5424589A (en) | 1993-02-12 | 1995-06-13 | The Board Of Trustees Of The Leland Stanford Junior University | Electrically programmable inter-chip interconnect architecture |
| JPH06275718A (ja) | 1993-03-19 | 1994-09-30 | Toshiba Corp | ゲートアレイ回路 |
| US5457410A (en) | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
| TW396312B (en) | 1993-12-30 | 2000-07-01 | At & T Corp | Method and apparatus for converting field-programmable gate array implementations into mask-programmable logic cell implementations |
| US5808351A (en) | 1994-02-08 | 1998-09-15 | Prolinx Labs Corporation | Programmable/reprogramable structure using fuses and antifuses |
| US5682107A (en) | 1994-04-01 | 1997-10-28 | Xilinx, Inc. | FPGA architecture with repeatable tiles including routing matrices and logic matrices |
| EP0755588B1 (de) | 1994-04-14 | 2002-03-06 | Btr, Inc. | Architektur und verbindungsschema für programmierbare logische schaltungen |
| US5689195A (en) | 1995-05-17 | 1997-11-18 | Altera Corporation | Programmable logic array integrated circuit devices |
| US5815003A (en) | 1994-11-04 | 1998-09-29 | Altera Corporation | Programmable logic integrated circuits with partitioned logic element using shared lab-wide signals |
| US5581199A (en) | 1995-01-04 | 1996-12-03 | Xilinx, Inc. | Interconnect architecture for field programmable gate array using variable length conductors |
| GB2297409B (en) | 1995-01-27 | 1998-08-19 | Altera Corp | Programmable logic devices |
| US5847577A (en) | 1995-02-24 | 1998-12-08 | Xilinx, Inc. | DRAM memory cell for programmable logic devices |
| US5701091A (en) | 1995-05-02 | 1997-12-23 | Xilinx, Inc. | Routing resources for hierarchical FPGA |
| US5850564A (en) | 1995-05-03 | 1998-12-15 | Btr, Inc, | Scalable multiple level tab oriented interconnect architecture |
| AU5718196A (en) | 1995-05-03 | 1996-11-21 | Btr, Inc. | Scalable multiple level interconnect architecture |
| US5625301A (en) | 1995-05-18 | 1997-04-29 | Actel Corporation | Flexible FPGA input/output architecture |
| US5640106A (en) | 1995-05-26 | 1997-06-17 | Xilinx, Inc. | Method and structure for loading data into several IC devices |
| US5631578A (en) | 1995-06-02 | 1997-05-20 | International Business Machines Corporation | Programmable array interconnect network |
| US5671432A (en) * | 1995-06-02 | 1997-09-23 | International Business Machines Corporation | Programmable array I/O-routing resource |
| US5732246A (en) | 1995-06-07 | 1998-03-24 | International Business Machines Corporation | Programmable array interconnect latch |
| US5838954A (en) | 1995-08-18 | 1998-11-17 | Xilinx, Inc. | Computer-implemented method of optimizing a time multiplexed programmable logic device |
| US5701441A (en) | 1995-08-18 | 1997-12-23 | Xilinx, Inc. | Computer-implemented method of optimizing a design in a time multiplexed programmable logic device |
| US5880492A (en) | 1995-10-16 | 1999-03-09 | Xilinx, Inc. | Dedicated local line interconnect layout |
| US5815004A (en) | 1995-10-16 | 1998-09-29 | Xilinx, Inc. | Multi-buffered configurable logic block output lines in a field programmable gate array |
| US5594367A (en) * | 1995-10-16 | 1997-01-14 | Xilinx, Inc. | Output multiplexer within input/output circuit for time multiplexing and high speed logic |
| US5870586A (en) | 1996-01-31 | 1999-02-09 | Xilinx, Inc. | Configuration emulation of a programmable logic device |
| US5744980A (en) | 1996-02-16 | 1998-04-28 | Actel Corporation | Flexible, high-performance static RAM architecture for field-programmable gate arrays |
| US5835998A (en) | 1996-04-04 | 1998-11-10 | Altera Corporation | Logic cell for programmable logic devices |
| US5869979A (en) * | 1996-04-05 | 1999-02-09 | Altera Corporation | Technique for preconditioning I/Os during reconfiguration |
| US5847441A (en) | 1996-05-10 | 1998-12-08 | Micron Technology, Inc. | Semiconductor junction antifuse circuit |
| US5894565A (en) * | 1996-05-20 | 1999-04-13 | Atmel Corporation | Field programmable gate array with distributed RAM and increased cell utilization |
| US5742181A (en) * | 1996-06-04 | 1998-04-21 | Hewlett-Packard Co. | FPGA with hierarchical interconnect structure and hyperlinks |
| US5825201A (en) | 1996-06-21 | 1998-10-20 | Quicklogic Corporation | Programming architecture for a programmable integrated circuit employing antifuses |
| US5828538A (en) | 1996-06-21 | 1998-10-27 | Quicklogic Corporation | Power-up circuit for field programmable gate arrays |
| US5859544A (en) | 1996-09-05 | 1999-01-12 | Altera Corporation | Dynamic configurable elements for programmable logic devices |
| US5880597A (en) | 1996-09-18 | 1999-03-09 | Altera Corporation | Interleaved interconnect for programmable logic array devices |
| US5825202A (en) | 1996-09-26 | 1998-10-20 | Xilinx, Inc. | Integrated circuit with field programmable and application specific logic areas |
| US5883526A (en) | 1997-04-17 | 1999-03-16 | Altera Corporation | Hierarchical interconnect for programmable logic devices |
| US5828230A (en) | 1997-01-09 | 1998-10-27 | Xilinx, Inc. | FPGA two turn routing structure with lane changing and minimum diffusion area |
| US5880598A (en) | 1997-01-10 | 1999-03-09 | Xilinx, Inc. | Tile-based modular routing resources for high density programmable logic device |
| US5959466A (en) * | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
| US5821776A (en) | 1997-01-31 | 1998-10-13 | Actel Corporation | Field programmable gate array with mask programmed analog function circuits |
| US5878051A (en) * | 1997-02-05 | 1999-03-02 | Lockheed Martin Corp. | Assembly-level bist using field-programmable gate array |
| US6150837A (en) * | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
| US5874834A (en) * | 1997-03-04 | 1999-02-23 | Xilinx, Inc. | Field programmable gate array with distributed gate-array functionality |
| US5991908A (en) * | 1997-09-29 | 1999-11-23 | Xilinx, Inc. | Boundary scan chain with dedicated programmable routing |
| US6334207B1 (en) * | 1998-03-30 | 2001-12-25 | Lsi Logic Corporation | Method for designing application specific integrated circuits |
| US7389487B1 (en) | 1998-04-28 | 2008-06-17 | Actel Corporation | Dedicated interface architecture for a hybrid integrated circuit |
| US6943583B1 (en) * | 2003-09-25 | 2005-09-13 | Lattice Semiconductor Corporation | Programmable I/O structure for FPGAs and the like having reduced pad capacitance |
-
1998
- 1998-04-28 US US09/069,054 patent/US7389487B1/en not_active Expired - Fee Related
-
1999
- 1999-04-05 EP EP99916389A patent/EP1080531B1/de not_active Expired - Lifetime
- 1999-04-05 WO PCT/US1999/007484 patent/WO1999056394A1/en active IP Right Grant
- 1999-04-05 DE DE69924486T patent/DE69924486T2/de not_active Expired - Lifetime
-
2008
- 2008-05-02 US US12/114,143 patent/US8990757B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE69924486T2 (de) | 2006-02-16 |
| US7389487B1 (en) | 2008-06-17 |
| EP1080531B1 (de) | 2005-03-30 |
| US20080204074A1 (en) | 2008-08-28 |
| US8990757B2 (en) | 2015-03-24 |
| EP1080531A1 (de) | 2001-03-07 |
| WO1999056394A1 (en) | 1999-11-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |