EP0015342B1

EP0015342B1 - Substrate bias regulator

Info

Publication number: EP0015342B1
Application number: EP79302875A
Authority: EP
Inventors: Jerry Dale Moench; Rodney Clair Tesch
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1979-03-05
Filing date: 1979-12-12
Publication date: 1984-01-25
Also published as: JPS55120158A; EP0015342A1; DE2966592D1

Description

This invention relates, in general, to semi- conductor substrate bias circuits, and more particularly, to a regulator to regulate substrate bias voltage generators.
To achieve high performing dynamic random access memories (RAM) a negative substrate voltage is required. In dynamic RAMs certain nodes are charged to a given voltage. These nodes do not have a current source and must therefore be periodically, e.g. every 2 milliseconds, refreshed or recharged. These nodes are capacitively coupled to the semiconductor substrate and since much of the capacitance associated with these nodes is substrate capacitance, the voltage on the nodes will change approximately directly with substrate voltage changes.
In the past, in some cases, a negative voltage was applied from an external power supply to the substrate. However, this required an extra power supply which was inconvenient, especially, for single power supply devices. To eliminate the requirement of an external power supply, ring oscillators were built on the substrate and used to drive a charge pump or bias voltage generator which would supply a negative voltage to the substrate. A disadvantage to this approach is that the substrate voltage would then vary when the semiconductor chip power supply varied. Sometimes the substrate bias voltage would tend to vary a greater amount than the power supply voltage variation.
Accordingly, it is an object of the present invention to provide an improved substrate bias regulator to regulate the substrate bias voltage of a semiconductor chip to a predetermined ratio of the power supply of the chip.
Another object of the present invention is to provide a substrate bias regulator which is useful in minimizing the high output impedance effects of a substrate bias voltage generator.
Yet another object of the present invention is to provide a substrate bias voltage which varies percentagewise the same amount as the supply voltage varies.
Substrate voltage regulators for regulating the substrate bias voltage are known from the following publications:-

1. Article entitled 'Substrate and Load Gate Voltage Compensation' by E. M. Blaser et al (1976 IEEE International Solid State Circuits Conference).
2. Article entitled 'Compensation for Depletion-Mode FET Circuits' (IBB Technical Disclosure Bulletin Vol. 19 No. 7 December 1976).
3. FR-A-2 235 417.

All three publications teach that an increase in threshold voltage can be used to advantage to sense the substrate voltage and the regulators described in these publications rely upon the change in an operating threshold voltage to regulate the substrate voltage. This is the converse of the present invention wherein the regulator will regulate to a predetermined substrate voltage in a manner which in independent of the threshold voltage.
According to the present invention there is provided a substrate bias voltage regulator for controlling a substrate bias voltage generator to provide a predetermined substrate bias voltage to a semiconductor substrate comprising a first field effect transistor having a first electrode and a gate electrode coupled to a first supply voltage and a second electrode; a second field effect transistor having a first electrode coupled to the second electrode of the first transistor, a second electrode connected directly to the substrate, and a gate electrode directly connected to ground without intervening elements, the second transistor developing a control voltage on the first electrode thereof which is related to the deviation from the predetermined substrate bias voltage of the bias voltage developed on the substrate by the substrate bias voltage generator and amplifying means for coupling the control voltage developed on the first electrode of the second transistor to the substrate bias voltage generator to control the operation thereof.
The invention will now be described by way of example only with particular reference to the accompanying drawings wherein:

Figure 1 illustrates in block diagram form a substrate bias generating system embodying the present invention;
Figure 2 illustrates in schematic form an embodiment of the present invention; and
Fig. 3 illustrates in schematic form another embodiment of the present invention.

The exemplifications set out herein illustrate the preferred embodiments of the invention in one form thereof, and such exemplifications are not to be construed as limiting in any manner.

Detailed description of the drawings

Referring first to Fig. 1, there is illustrated in block diagram form a system for generating a substrate bias voltage for substrate 10. Substrate 10 would typically be a substrate for a semiconductor chip. The circuitry for the semi- conductor chip is formed upon substrate 10. A variable output oscillator 12, such as a ring type oscillator, provides an output whose voltage varies in time thereby driving substrate bias voltage generator 13. Oscillators and bias generators useful for oscillator 12 and generator 13 are well known in the art. Bias generator 13 preferably generates a negative voltage which is coupled to substrate 10. Bias generator 13 can be of the type which couples the output of oscillator 12 through a capacitor to diodes arranged in a voltage doubling manner to generate a negative voltage. Substrate bias voltage regulator 11 monitors the negative voltage of substrate 10 through connection 14. Regulator 11 provides an output to oscillator 12 which can control the output of oscillator 12 by inhibiting the output from oscillator 12 or else by simply controlling one of the stages of oscillator 12 to thereby reduce its output. Although regulator 11 is illustrated as controlling oscillator 12 it will be understood that the output of regulator 11 could also be used to control the output from substrate bias generator 13. On a semiconductor chip having a single positive power supply, regulator 11 and oscillator 12 can be powered from the single supply and generator 13, which is powered by the oscillator, can be used to generate a negative voltage for substrate 10.
Fig. 2 illustrates in schematic form a regulator which can be used for substrate bias voltage regulator 11 of Fig. 1. The circuit of Fig. 2 shows two series connected transistors 16 and 17 which sense the voltage of substrate 10 and provide an output V1 bearing a relationship to the voltage of substrate 10. Transistor 17 has its gate and drain connected to voltage terminal V_DD. Transistor 17 has its source connected to the drain of transistor 16 forming a node providing output V1. The source of transistor 16 is used to sense the voltage of substrate 10. Transistor 16 has its gate connected to a reference potential terminal illustrated as ground. There are several advantages to using ground as a reference. The first is that the substrate bias voltage is not dependent upon threshold values of the transistors. Also the equations for calculating voltage V1 are easier to solve if the gate electrode of transistor 16 is tied to ground. And with the gate of transistor 16 tied to ground, transistor 16 operates in the saturated region as does transistor 17, and this makes the voltage equations solve nicely without being threshold dependent.
Voltage V1 is coupled to the gate electrode of transistor 18. Transistor 18 has its source connected to reference potential ground. Transistor 19 is connected in series with transistor 18 and has its gate and drain electrodes connected to voltage terminal V_DD. The source of transistor 19 is connected to the drain of transistor 18 to form a node from which voltage V2 is obtained. Voltage V2 is illustrated as going to a gate electrode of transistor 21. Transistors 21 and 22 are in series between reference potential ground and voltage terminal V_DD. Transistor 22 has its gate electrode connected to its drain electrode. Transistors 21 and 22 serve as a buffer and receive voltage V2 as an input and provide voltage V3 as an output. It should be noted that voltage V2 can serve as an output from the circuitry of Fig. 2 which would then be connected to oscillator 12 or generator 13. In other words, the inverting buffer provided by transistors 21 and 22 may not be required in certain applications. Transistor 18 is preferably of a larger size than transistor 19 to provide a gain through transistors 18 and 19. Transistors 18 and 19, as illustrated, serve as an inverting amplifier by amplifying voltage V1 and providing it as an inverted voltage V2.
The circuit illustrated in Fig. 2 will provide an output voltage of approximately minus V_DD divided by 2. When voltage V1 is higher than the threshold voltage of transistor 18, transistor 18 will conduct thereby making voltage V2 low, which will inhibit the conduction of transistor 21 to provide a high output voltage V3. When voltage V1 is below the threshold voltage of transistor 18 then transistor 18 will not be enabled and voltage V2 will be high, or in other words, equal to the voltage appearing at terminal V_DD minus the threshold voltage of transistor 19. When voltage V2 is high, transistor 21 will be enabled thereby rendering voltage V3 low or approximately equal to the voltage at the source of transistor 21, which, as illustrated, is ground.
The circuit of Fig. 2 provides the most useful regulating output when voltage V1 equals the threshold voltage plus a small AV. The AV is caused by the ratio of transistors 18 and 19 and can therefore be minimized by selection of the ratio. The current through transistor 17 can be approximated by the following equation:
where I₁₇ equals the current through transistor 17; K₁₇ is a constant associated with transistor 17 which is determined by width, length, and other parameters of transistor 17; V_DD is the voltage at terminal V_DD; V_T is the threshold voltage of transistor 17; and AV is a slight increase of voltage needed over the threshold voltage to make transistor 18 conduct. The current through transistor 16 will be the same as the current through transistor 17 since they are both in series and can be setout as:
where I₁₆ equals the current through transistor 16; K₁₆ is the constant associated with transistor 16; and V_SUB is the voltage in substrate 10; and V, is the threshold voltage of transistor 16. If transistors 16 and 17 are made such that K₁₆ equals 4K17 the two equations can be combined as follows:
If the square root of each side of the equation is taken and K₁₇ is cancelled on each side, then we have:
The 2V_T from each side of the equation can be cancelled and the equation can be reduced to
If transistor 19 is made much, much smaller than transistor 18 then AV will be much, much smaller than V_DD and the equation can be further reduced to
The above equations are only approximately valid and do not include all physical aspects of the transistors, however, they are close enough for practical considerations.
When the substrate voltage V_SUB is more positive than minus V_DD over two V_DD/2, V1 will be greater than a threshold voltage U_T; this produces a high voltage V3 allowing the substrate generator to pump to a more negative voltage. When the substrate voltage V_SUB is more negative than minus V_DD over two V_DD/2, V1 will be less than a threshold voltage V_T. This produces a low voltage V₃, disabling the generator which then ceases to pump the substrate to a more negative voltage. With the generator disabled transistors 16 and 17 provide a current path to the substrate charging the substrate back to minus V_DD over two V_DD/2. At this voltage the generator will be enabled again. This feature of forcing the substrate to minus V_DD over two (V_DD/2) from either direction, a higher substrate voltage or a lower substrate voltage, results in minimization of the high output impedance of the substrate voltage generator.
As can be seen from the above equation, the substrate voltage can be controlled to within approximately one-half of the voltage applied to terminal V_DD. With the regulator of Fig. 2 the substrate voltage can be controlled to within the same percentage as the voltage V_DD. For example, if voltage V_DD changes 10 percent the substrate voltage will change 10 percent also.
Fig. 3 illustrates another embodiment for the substrate bias voltage regulator 11 in Fig. 1. The regulator of Fig. 3 is capable of regulating the substrate voltage to approximately a negative V_DD. Three series transistors 31, 32, and 33 are connected between substrate 10 and voltage terminal V_DD to provide an output at node 35 which can be used to regulate the voltage at substrate 10. Transistor 31 has its source coupled to substrate 10 and its gate and drain electrodes connected together to form node 34. Transistor 32 has its source connected to node 34 and its gate electrode connected to reference potential ground. Transistor 33 has its drain and gate electrodes connected to voltage terminal V_DD and its source electrode connected to the drain electrode of transistor 32 to form node 35.
Transistors 36 and 37 are in series and take the signal at node 35 which is coupled to the gate electrode of transistor 37 and provide an amplified inverted output at node 40. The drain of transistor 37 is tied to the source of transistor 36 to form node 40. Transistor 36 has its gate and drain electrodes connected to voltage terminal V_DD. Transistors 38 and 39 form a buffer for the signal at node 40 and provide output V_o. The output V_o will be in-phase with the signal at node 35. If the in-phase signal is not needed to control an oscillator or voltage bias generator then the output from node 40 can be used.
The equations determining the substrate voltage that will be provided by the regulator of Fig. 3 are similar to the equations for Fig. 2. If transistor 31 is much greater in physical size than transistor 32 the voltage at node 34 will equal the substrate 10 voltage plus the threshold voltage of transistor 31. The slight increase of voltage needed to overcome the threshold voltage will be neglected since as shown hereinbefore it is much much smaller than V_DD. The current through transistor 33 can be expressed by the following equation:
where K₃₃ is the constant for transistor 33; V_DD is the voltage at voltage terminal V_DD; and V, is the threshold voltage. The current through transistor 32 will equal the current through transistor 33 and can be expressed by the following equation:
K₃₁ is the constant for transistor 32; V_SUB is the voltage of substrate 10; and V_T is the transistor threshold. If K₃₃ equals K₃₂ the equations can be quickly reduced in the same manner as the equation of Fig. 2 were reduced to show that V_DD equals approximately minus V_SUB.
By now it should be appreciated that there has been provided a regulator circuit which will regulate the substrate voltage in a semi- conductor chip. By using the substrate bias voltage regulator the high output impedance associated with substrate bias voltage generators is overcome. When the voltage regulator is regulating no current is drawn from the substrate bias voltage generator and its output voltage will remain constant. Because of the high output impedance associated with substrate voltage generators, if current is drawn from the output, the output voltage will decrease. Another advantage resulting from the use of the substrate bias voltage regulator, of the present invention, is that when the semi-conductor chip is still a part of a silicon wafer, probe test can be performed on the chip in a much more reliable fashion since the probe test operator will know the value of substrate voltage to apply to the wafer. Although only two embodiments of the substrate bias voltage regulator are illustrated, it will be apparent to those skilled in the art that other values of substrate voltage can be obtained by following the teachings of the present invention.

Claims

1. A substrate bias voltage regulator (11) for controlling a substrate bias voltage generator (13) to provide a predetermined substrate bias voltage to a semi-conductor substrate (10) comprising a first field effect transistor (17) having a first electrode and a gate electrode coupled to a first power supply voltage terminal (V_DD), and a second electrode; a second field effect transistor (16) having a first electrode coupled to the second electrode of the first transistor (17), a second electrode connected directly to the substrate, and a gate electrode directly connected to ground without intervening elements, the second transistor (16) developing a control voltage on the first electrode thereof which is related to the deviation from the predetermined substrate bias voltage of the bias voltage developed on the substrate by the substrate bias voltage generator (13) and amplifying means (18, 19) for coupling the control voltage developed on the first electrode of the second transistor (16) to the substrate bias voltage generator (13) to control the operation thereof.

2. A substrate bias voltage regulator as claimed in claim 1 wherein the amplifying means (18, 19) further comprises a third field effect transistor (19) having a first electrode and a gate electrode coupled to the first power supply voltage terminal (Vpp), and a second electrode; and a fourth field effect transistor (18) having a first electrode coupled to the second electrode of the third transistor (19), a second electrode coupled to ground, and a gate electrode coupled to the first electrode of the second transistor (16), the fourth transistor (18) developing an output voltage on the first electrode thereof which is coupled to the substrate bias voltage generator (13) to control the operation thereof.

3. A substrate bias voltage regulator (11) for controlling a substrate bias voltage generator (13) to provide a predetermined substrate bias voltage to a semiconductor substrate (10), comprising a first field effect transistor (33) having a first electrode and a gate electrode coupled to a first power supply voltage terminal (V DD), and a second electrode; a second field effect transistor (32) having a first electrode coupled to the second electrode of the first transistor (33), a gate electrode directly connected to ground without intervening elements, and a second electrode; a third field effect transistor (31) having a gate and a first electrode coupled to the second electrode of the second transistor (32), and a second electrode connected directly to the substrate (10) to sense the substrate voltage, wherein the second transistor (32) develops a control voltage on the first electrode thereof which is related to the deviation from the predetermined substrate bias voltage of the bias voltage developed on the substrate by the substrated bias voltage generator (13) and amplifying means (36, 37) for coupling the control voltage developed on the first electrode of the second transistor (32) to the substrate bias voltage generator (13) to control the operation thereof.