EP0173808A1 - Control circuit for liquid-crystal displays - Google Patents

Control circuit for liquid-crystal displays Download PDF

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Publication number
EP0173808A1
EP0173808A1 EP85107726A EP85107726A EP0173808A1 EP 0173808 A1 EP0173808 A1 EP 0173808A1 EP 85107726 A EP85107726 A EP 85107726A EP 85107726 A EP85107726 A EP 85107726A EP 0173808 A1 EP0173808 A1 EP 0173808A1
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EP
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Prior art keywords
display
voltage
segment
segments
lines
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EP85107726A
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German (de)
French (fr)
Inventor
Friedrich Füldner
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Deutsche Thomson Brandt GmbH
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Deutsche Thomson Brandt GmbH
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/18—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible a small local pattern covering only a single character, and stepping to a position for the following character, e.g. in rectangular or polar co-ordinates, or in the form of a framed star

Definitions

  • the invention is based on a circuit arrangement as defined in the preamble in the claim.
  • LC displays which consist of many segments, are controlled in multiplex mode.
  • the individual segments and their counter electrodes are combined in a matrix.
  • each individual segment can be displayed by applying an alternating voltage, in that two opposing segments are activated simultaneously.
  • Microprocessors are used to control the segments of the LC display, and the corresponding control voltages are applied to their outputs.
  • the control voltages reach the LC display unit via LCD driver ICs.
  • the advantage of the invention lies in the low manufacturing costs and in a higher reliability.
  • FIG. 1a shows the electrodes of the same shape opposite the segments of FIG. 1a, which can be controlled via so-called common lines C1 to C4, these segments also being combined into groups.
  • the lines S1 to S10 and C1 to C4 are arranged in a matrix, so that each individual element of the display can be controlled separately and individually. Only the element to which the corresponding control voltage is present via lines S1 to S10 and C1 to C4 is always displayed.
  • FIGS. 2a-h The control voltages for the segment lines S1 and S2 and the common lines C1 to C4 are shown in FIGS. 2a-h.
  • a character formed from the segments can be displayed by the phase relationship of the signals on lines S1 and S2 with respect to the phase relationship of the signals on lines C1 to C4.
  • the mark "TUNING” and "FM” will come to the display, since the voltages according to Figures 2a and 2e, and FIG have mutually 2b and 2e the right for a display Phesenlage. (Fig.g, h)
  • FIG. 3 a Heidelberg constructed according to the feature of the invention is shown.
  • An LC display 1 with the inputs C1 to C4 and S1 to S10 is connected to a control unit 2.
  • At the output A1 of the microprocessor 2 there is a square wave of constant amplitude and phase, which are switched cyclically via the analog switch 3 to the inputs C1 to C4 of the LC display.
  • the analog switches 3 are controlled via control outputs A2 to A5, as a result of which the display is multiplexed.
  • the example shown is a microprocessor with open-drain outputs, for which a pull-up resistor 4 is required.
  • voltage dividers 5 are connected to the operating voltage, at the dividing points of which the output A1 of the control unit 2 is connected via the analog switch 3.
  • the analog switches 3 shown can be omitted if a microprocessor with tri-state outputs is used.
  • the inputs S1 to S10 of the display are connected to the outputs B1 to B10 of the microprocessor.
  • the inputs S1 to S10 are connected to taps of voltage dividers 6 and via resistors 7 to the outputs B1 to B10 of the control unit 2.
  • the LC display is effective at a certain voltage UD between the intersection of a segment line and a common line and e.g. switched off at 1/3 of this voltage UD. This is called 1/3 bias.
  • the voltage dividers 5 for the common lines C1 to C4 and the voltage dividers 6 for the segment lines S1 to S10 are to be dimensioned such that a voltage swing of 4/3 of the voltage UD arises at the taps for the common lines C1 to C4, so that between common - And segment line either the full display voltage UD or 1/3 UD arises.
  • a display voltage UD of e.g. 3 volts the potential on the common line must change between 4 volts and 0 volts if the potential of the segment line changes between 1 volt and 3 volts.
  • FIG. 4 shows a dimensioning example for the voltage dividers 5 and 6, with which the required voltages can be generated.
  • the A outputs and the B outputs are connected to the taps of the voltage dividers 5 and 6.
  • the resistors 14 and 7 are, depending on the switching state of the stages 12 ', 13' at the outputs A and B, at the positive operating voltage + U in parallel with the resistor 8 or 10, or in parallel with the reference potential Resistors 9 and 11 or the resistors 14 and 7 are switched off with a high homing.
  • the voltage swing on the common line 4/3 is the display voltage UD, i.e. 4 volts. Since the undervoltage only drops to 0.5 volts, the upper voltage has to be raised to 4.5 volts.
  • the example shown relates to an LC display with 4 common and 10 segment lines. Of course, any combination of the number of segment and common lines can be used.

Abstract

A control circuit for controlling an LC display. Between the control unit controlling the LC display and the LC display, passive voltage dividers are connected to generate the control voltages for the LC display. <IMAGE>

Description

Die Erfindung geht aus von einer Schaltungsanordnung wie sie im Patentanspruch im Oberbegriff bezeichnet ist.The invention is based on a circuit arrangement as defined in the preamble in the claim.

Bekanntlich werden LC-Anzeigen, die aus vielen Segmenten bestehen, im Muliplex-Betrieb angesteuert. Hierzu werden die einzelnen Segmente sowie ihre Gegenelektroden matrixartig zusammengefasst. Dadurch kann durch Anlegen einer Wechselspannung jedes einzelne Segment zur Anzeige gebracht werden, indem zwei sich gegenüberliegende Segmente gleichzeitig angesteuert werden. Zur Ansteuerung der Segmente der LC-Anzeige werden Mikroprozessoren verwendet, an deren Ausgängen die entsprechenden Ansteuerspannungen anliegen. Die Ansteuerspannungen gelangen über LCD-Treiber-ICs an die LC-Anzeigeeinheit. (Programmer' s Reference Manual, Hitachi, Ausgabe Juli 1981, 40-1-12, Seite 42 "Liquid Crystal Display, Circuit-Block Diagram ). Diese Treiber-ICs sind teure Bauelemente und es liegt der Erfindung die Aufgabe zugrunde diese einzusparen. Die Aufgabe wird durch die im Patentanspruch 1 angegebene Erfincdng gelöst.It is known that LC displays, which consist of many segments, are controlled in multiplex mode. For this purpose, the individual segments and their counter electrodes are combined in a matrix. As a result, each individual segment can be displayed by applying an alternating voltage, in that two opposing segments are activated simultaneously. Microprocessors are used to control the segments of the LC display, and the corresponding control voltages are applied to their outputs. The control voltages reach the LC display unit via LCD driver ICs. (Programmer's Reference Manual, Hitachi, July 1981 edition, 40-1-12, page 42 "Liquid Crystal Display, Circuit Block Diagram). These driver ICs are expensive components and the object of the invention is to save them. The object is achieved by the invention specified in claim 1.

Der Vorteil der Erfindung liegt in den niedrigen Herstellungskosten und in einer höheren Zuverlässigkeit.The advantage of the invention lies in the low manufacturing costs and in a higher reliability.

Nachstehend sei das Wesentliche der Erfindung an einem Ausführungsbeispiel erläutert.The essence of the invention is explained below using an exemplary embodiment.

  • Figur 1 zeigt die Anordnung der Segmente und Steuerleitungen einer LC-Anzeige:Figure 1 shows the arrangement of the segments and control lines of an LC display:
  • Figur 2 zeigt die Kurvenverläufe der für eine Anzeige notwendigen Steuerspannungen ;Figure 2 shows the curves of the control voltages necessary for a display;
  • Figur 3 zeigt die Schaltungsanordnung zur Ansteuerung der Anzeige;Figure 3 shows the circuit arrangement for controlling the display;
  • Figur 4 zeigt die Schaltungsanordnung zur Ansteuerung der Anzeige ;Figure 4 shows the circuit arrangement for driving the display;
  • Figur 5 zeigt ein weiteres Dimensionierungsbeispiel für eine Schaltungsanordnung mit Tri-State-Ausgängen.FIG. 5 shows a further dimensioning example for a circuit arrangement with tri-state outputs.

In Figur a u. bist ein Anzeigefeld dargestellt zur Anzeige von Ziffern und Symbolen. In Figur 1a sind mehrere Segmente zu Gruppen zusammengefasst und über Segmentleitungen S1 bis S10 ansteuerbar. In Figur 1b sind die den Segmenten der Figur 1a gegenüberliegends' Elektroden der gleichen Form dargestellt, die über sogenannte Common-Leitungen C1 bis C4 ansteuerbar sind, wobei auch diese Segmente zu Gruppen zusammengefasst sind. Die Leitungen S1 bis S10 und C1 bis C4 sind matrixartig angeordnet, so daß jedes einzelne Element der Anzeige getrennt und einzeln ansteuerbar ist. Es wird immer nur das Element zur Anzeige gebracht, an welchem über die Leitung S1 bis S10 und C1 bis C4 die entsprechende Ansteuerspannung anliegt.In Figure a u. a display field is shown to display numbers and symbols. In FIG. 1a, several segments are combined into groups and can be controlled via segment lines S1 to S10. FIG. 1b shows the electrodes of the same shape opposite the segments of FIG. 1a, which can be controlled via so-called common lines C1 to C4, these segments also being combined into groups. The lines S1 to S10 and C1 to C4 are arranged in a matrix, so that each individual element of the display can be controlled separately and individually. Only the element to which the corresponding control voltage is present via lines S1 to S10 and C1 to C4 is always displayed.

In Figur 2a-h sind z.B. die Steuerspannungen für die Segmentleitungen S1 und S2 und die Commonleitungen C1 bis C4 dargestellt. Durch die Phasenlage der Signale auf den Leitungen S1 und S2 in Bezug auf die Phasenlage der Signale auf den Leitungen C1 bis C4 kann ein aus den Segmenten gebildetes Zeichen zur Anzeige gebracht werden. Im dargestellten Beispiel nach den Figuren 1 und 2 werden die Zeichen "TUNING" und "FM" zur Anzeige kommen, da die Spannungen nach Figur 2a und 2e sowie Figur 2b und 2e die für eine Anzeige richtige Phesenlage zueinander besitzen. (Fig.g,h)The control voltages for the segment lines S1 and S2 and the common lines C1 to C4 are shown in FIGS. 2a-h. A character formed from the segments can be displayed by the phase relationship of the signals on lines S1 and S2 with respect to the phase relationship of the signals on lines C1 to C4. In the example shown in Figures 1 and 2, the mark "TUNING" and "FM" will come to the display, since the voltages according to Figures 2a and 2e, and FIG have mutually 2b and 2e the right for a display Phesenlage. (Fig.g, h)

In Figur 3 ist eine nach dem Merkmal der Erfindung aufgebaute Schaltong dargestellt. Eine LC-Anzeige 1 mit den Eingängen C1 bis C4 und S1 bis S10 ist an eine Steuereinheit 2 angeschlossen. Am Ausgang A1 des Mikroprozessors 2 liegt eine Rechteckschwingung konstanter Amplitude und Phase, die zyklisch über die Analogschalter 3 an die Eingänge C1 bis C4 der LC-Anzeige geschaltet sind. Die Analogschalter 3 werden über Steuerausgänge A2 bis A5 gesteuert, wodurch ein Multiplex-Betrieb der Anzeige erzielt wird. Bei dem gezeigten Beispielhendelt es sich um einen Mikroprozessor mit Open-Drain-Ausgängen, wozu ein Pull-Up-Widerstand 4 erforderlich ist. Zur Erzeugung der richtigen Ansteuerspannung für die Eingänge C1 bis C4 werden Spannungsteiler 5 an die Betriebsspannung gelegt, an dessen Teilerpunkten der Ausgang A1 der Steuereinheit 2 über die Analogschalter 3 gelegt ist. Die gezeigten Analogschalter 3 können entfallen, wenn ein Mikroprozessor mit Tri-State-Ausgängen verwendet wird. Die Eingänge S1 bis S10 der Anzeige sind an die Ausgänge B1 bis B10 des Mikroprozessors geschaltet. Hierzu liegen die Eingänge S1 bis S10 an Abgriffen von Spannungsteilern 6 und über Widerstände 7 an den Ausgängen B1 bis B10 der Steuereinheit 2.In Figure 3 a Schaltong constructed according to the feature of the invention is shown. An LC display 1 with the inputs C1 to C4 and S1 to S10 is connected to a control unit 2. At the output A1 of the microprocessor 2 there is a square wave of constant amplitude and phase, which are switched cyclically via the analog switch 3 to the inputs C1 to C4 of the LC display. The analog switches 3 are controlled via control outputs A2 to A5, as a result of which the display is multiplexed. The example shown is a microprocessor with open-drain outputs, for which a pull-up resistor 4 is required. To generate the correct control voltage for the inputs C1 to C4, voltage dividers 5 are connected to the operating voltage, at the dividing points of which the output A1 of the control unit 2 is connected via the analog switch 3. The analog switches 3 shown can be omitted if a microprocessor with tri-state outputs is used. The inputs S1 to S10 of the display are connected to the outputs B1 to B10 of the microprocessor. For this purpose, the inputs S1 to S10 are connected to taps of voltage dividers 6 and via resistors 7 to the outputs B1 to B10 of the control unit 2.

Die LC-Anzeige ist bei einer bestimmten Spannung UD zwischen dem Kreuzungspunkt einer Segmentleitung und einer Commonleitung wirksam und z.B. bei 1/3 dieser Spannung UD ausgeschaltet. Dieses wird mit 1/3 - Bias bezeichnet. Die Spannungsteiler 5 für die Common- leitungen C1 bis C4 und die Spannungsteiler 6 für die Segmentleitungen S1 bis S10 sind derart zu dimensionieren, daß an den Abgriffen für die Commonleitungen C1 bis C4 ein Spannungshub von 4/3 der Spannung UD entsteht, damit zwischen Common- und Segmentleitung entweder die volle Anzeigespannung UD bzw. 1/3 UD entsteht. Bei einer Anzeigespannung UD von z.B. 3 Volt muß sich das Potential auf der Commonleitung zwischen 4 Volt und 0 Volt ändern, wenn sich das Potential der Segmentleitung zwischen 1 Volt und 3 Volt ändert.The LC display is effective at a certain voltage UD between the intersection of a segment line and a common line and e.g. switched off at 1/3 of this voltage UD. This is called 1/3 bias. The voltage dividers 5 for the common lines C1 to C4 and the voltage dividers 6 for the segment lines S1 to S10 are to be dimensioned such that a voltage swing of 4/3 of the voltage UD arises at the taps for the common lines C1 to C4, so that between common - And segment line either the full display voltage UD or 1/3 UD arises. With a display voltage UD of e.g. 3 volts the potential on the common line must change between 4 volts and 0 volts if the potential of the segment line changes between 1 volt and 3 volts.

In Figur 4 ist ein Dimensionierungsbeispiel für die Spannungsteiler 5 und 6 angegeben, mit denen die geforderten Spannungen erzeugt werden können.FIG. 4 shows a dimensioning example for the voltage dividers 5 and 6, with which the required voltages can be generated.

An den Ausgang A1 des Mikroprozessors 2 ist, wie in Figur 2 dargestellt, das Netzwerk für die Commonleitung C1 gelegt. Je nach Schaltzustand der im Mikroprozessor 2 angeordneten Schaltstufe 12 und des Analagschalters 3 ergeben sich auf der Commonleitung C1 folgende Spannungen:

  • a.)Analogschalter 3 hochohmig : 2 Volt
  • b.)Analogschalter 3 niederohmig, Schaltstufe 12 niederohmig : 0 Volt
  • c.) Analogschalter 3 niederohmig, Schaltstufe 12 hochohmig : 4 Volt.
As shown in FIG. 2, the network for the common line C1 is connected to the output A1 of the microprocessor 2. Depending on the switching state of the switching stage 12 arranged in the microprocessor 2 and the analog switch 3, the following voltages result on the common line C1:
  • a.) Analog switch 3 high-resistance: 2 volts
  • b.) Analog switch 3 low-resistance, switching stage 12 low-resistance: 0 volt
  • c.) Analog switch 3 low-resistance, switching stage 12 high-resistance: 4 volts.

An den Ausgang B1 des Mikroprozessors 2 ist das Netzwerk für die Segmentleitung S1 gelegt. Je nach Schaltzustand der im Mikroprozessor 2 angeordneten Schaltstufe 13 ergeben sich infolge der in Figur 4 angegebenen Widerstandswerte auf der Segmentleitung S1 folgende Spannungen:

  • a.) Schaltstufe 13 hochohmig : 3 Volt,
  • b.) Schaltstufe 13 niederohmig : 1 Volt.
The network for segment line S1 is connected to output B1 of microprocessor 2. Depending on the switching state of the switching stage 13 arranged in the microprocessor 2, the following voltages result on the segment line S1 as a result of the resistance values indicated in FIG. 4:
  • a.) Switching stage 13 high-resistance: 3 volts,
  • b.) Switching stage 13 low-resistance: 1 volt.

Wenn der Mikroprozessor Tri-state-Ausgänge besitzt, so daß die Analcgschalter 3 entfallen können, liegen die A-Ausgänge wie die B-Ausgänge an den Abgriffen der Spannungsteiler 5 bzw. 6.If the microprocessor has tri-state outputs so that the analog switch 3 can be omitted, the A outputs and the B outputs are connected to the taps of the voltage dividers 5 and 6.

In Figur 5 ist ein entsprechender Aufbau mit der erforder- . lichen Dimensionierung angegeben. Bei den Tri-state-Ausgängen liegen die Widerstände 14 und 7 je nach Schaltzustand der Stufen 12', 13' an den Ausgängen A und B an der positiven Betriebsspannung +U parallel zu dem Widerstand 8 bzw. 10, oder auf Bezugspotential parallel zu den Widerständen 9 bzw. 11 oder die Widerstände 14 und 7 liegen hochhomig abgeschaltet. Auch bei dieser Schaltung ist der Spannungshub auf der Commonleitung 4/3 der Anzeigespannung UD, d.h. 4 Volt. Da die Unterspannnung nur auf 0,5 Volt absinkt, muss die Oberspannung auf 4,5 Volt angehoben werden.In Figure 5, a corresponding structure with the required. dimensioning specified. In the tri-state outputs, the resistors 14 and 7 are, depending on the switching state of the stages 12 ', 13' at the outputs A and B, at the positive operating voltage + U in parallel with the resistor 8 or 10, or in parallel with the reference potential Resistors 9 and 11 or the resistors 14 and 7 are switched off with a high homing. In this circuit too, the voltage swing on the common line 4/3 is the display voltage UD, i.e. 4 volts. Since the undervoltage only drops to 0.5 volts, the upper voltage has to be raised to 4.5 volts.

Das gezeigte Beispiel bezieht sich auf eine LC-Anzeige mit 4 Common- und 10 Segmentleitungen. Selbstverständlich körnen beliebige Kombinationen der Anzahl von Segment- und Commonleitungen benützt werden.The example shown relates to an LC display with 4 common and 10 segment lines. Of course, any combination of the number of segment and common lines can be used.

Claims (3)

1. Schaltungsanordnung zur Ansteuerung einer aus mehreren Segmenten bestehenden Flüssig-Kristell-Anzeige CLC-Anzeige), bei welcher die Segmente in mehrere Gruppen zusammengeschaltet sind und mit einer Wechselspannung über Segmentleitungen ansteuerbar sind undmit den Segmenten gegenüberliegenden diesen in der Form angepassten Gegenelektroden, die ebenfalls in mehrere Gruppen zusammengeschaltet sind und die über Common-Leitungen im Multiplexbetrieb zyklisch ansteuerbar sind, wobei die Segmente und Gegenelektroden matrixartig derart zusammengefasst sind, daß jedes einzelne Segment zur Anzeige gebracht werden kann, wobei die Schaltspannungen für die Segment- und Common-Leitungen von den Ausgängen einer Steuereinheit geliefert bzw. gesteuert werden, dadurch gekenn- zeichnet, daß.zwischen die die Schaltspannungen liefernden bzw. steuernden Ausgänge (A, B) der Steuer- einheit (2) und die Segment- und Commonleitungen (C, S) der LC-Anzeige (1) passive Spannungsteiler (5, 6) geschaltet sind.1.Circuit arrangement for controlling a liquid crystal display consisting of several segments (CLC display), in which the segments are interconnected in several groups and can be controlled with an alternating voltage via segment lines, and with the segments opposite them in the form of these, which are also adapted are interconnected in several groups and can be cyclically controlled via common lines in multiplex operation, the segments and counter electrodes being combined in a matrix such that each individual segment can be displayed, the switching voltages for the segment and common lines from the Outputs of a control unit are supplied or controlled, characterized in that between the outputs (A, B) of the control unit (2) which supply or control the switching voltages and the segment and common lines (C, S) of the LC -Display (1) passive voltage dividers (5, 6) are switched. 2. Schaltungsanordnung nach Anspruch 1, dadurch gekennzeichnet, daß die passiven Spannungsteiler (5, 6) derart dimensioniert sind, daß sie in Abhängigkeit vom Schaltzustand der Ausgänge (A, B) der Steuereinheit (2) die Ansteuerspannungen für die Segmentleitungen (S) und Commonleitungen (C) liefern.2. Circuit arrangement according to claim 1, characterized in that the passive voltage dividers (5, 6) are dimensioned such that they, depending on the switching state of the outputs (A, B) of the control unit (2), the drive voltages for the segment lines (S) and Deliver common lines (C). 3. Scheltungsanordnung nach Anspruch 1, dadurch gekennzeichnet, daß zwischen der Betriebsspannung (U) und Erdpotential Spannungsteiler (5, 6) geschaltet sind, deren Teilerpunkte mit den Common- bzw. Segmentleitungen (C bzw. S) verbunden sind und daß die Abgriffe der an den Commonleitungen (C) liegende Spannungsteiler (5) zyklisch an den mit einer rechteckförmigen Wechselspannung beaufschlagten Ausgang (A1) der Steuereinheit (2) gelegt sind und daß die mit den Segmentleitungen (S) verbundenen Abgriffe der Spannungsteiler (6) über Vorwiderstände (7) mit den die Wechselspannung für die Segmente der LC-Anzeige (1) liefernden Ausgängen (B) der Steuereinheit (2) verbunden sind, wobei die Widerstände (8, 9) der Spannungsteiler (5) und die Widerstände (10, 11) der Spannungsteiler (6) und die Vorwiderstände (7) derart dimensioniert sind, daß an den Abgriffen der Spannungsteiler (5, 6) in Abhängigkeit von der Ausgangsimpedanz der Ausgänge (A, B) (hochohmig oder niederohmig) die für die Anzeige der ausgewählten Segmente erforderlichen Potentiale entstehen.3. A circuit arrangement according to claim 1, characterized in that voltage dividers (5, 6) are connected between the operating voltage (U) and earth potential, the divider points of which are connected to the common or segment lines (C or S) and that the taps of the Voltage dividers (5) on the common lines (C) are cyclically connected to the output (A1) of the control unit (2) to which a rectangular alternating voltage is applied and that the taps of the voltage dividers (6) connected to the segment lines (S) are connected via series resistors (7 ) are connected to the outputs (B) of the control unit (2) providing the AC voltage for the segments of the LC display (1), the resistors (8, 9) of the voltage dividers (5) and the resistors (10, 11) of the Voltage dividers (6) and the series resistors (7) are dimensioned such that at the taps of the voltage dividers (5, 6) depending on the output impedance of the outputs (A, B) (high-resistance or low-resistance) which are required for the display d the potential required for selected segments.
EP85107726A 1984-07-28 1985-06-22 Control circuit for liquid-crystal displays Withdrawn EP0173808A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3427986 1984-07-28
DE19843427986 DE3427986A1 (en) 1984-07-28 1984-07-28 CIRCUIT ARRANGEMENT FOR CONTROLLING LIQUID CRYSTAL DISPLAYS

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