EP0255436A1 - Graphics board with keyboard and mouse interface - Google Patents

Abstract

The present invention relates to an interface and graphics board between a central processor 1 communicating asynchronously with this board via an external bus and the video monitor 9 characterised in that it comprises: - a set of video-memories 45, 46 with capacity equal to at least the number of desired display points on the monitor 9, - at least one group of random-access memories 43, 44 or 41, 42 for storing graphics application software, - a circuit 40 controlling the video system, and managing the addresses of the various memories with a view to refreshing the memories and the video display, and updating the data or the programs and delivering the video signals; - a circuit 60 for serialising the data delivered by the video memory 45, 46 in step with a video clock H1; - a graphics processor 30 kept in step by a clock H0 and operating in synchronism with the circuit 40 of the controller of the video system so as to execute the software programs contained in the group of random-access memories; - an interface circuit 20 to 22 between the external bus and the buses of the board and a circuit 23 to 27 for arbitration between the graphics processor 30, the video-system controller 40 and the external bus. <IMAGE>

Description

The present invention relates to an interface graphics card, keyboard, mouse. There are keyboard interface cards, mouse interface cards, graphics cards which are generally all connected to the buses of a central processor with which they cooperate to constitute a microcomputer having a certain number of functionalities. In this type of solution the central processor is occupied not only with managing the operating programs of the system but also with managing the inputs and outputs between the various keyboard, mouse and graphical interfaces for display.

A first object of the invention is also to propose an electronic card making it possible to control a graphic screen with a resolution of 1024 X 768 points and to interface with a bus external to the card of the type or similar, or compatible with a bus. VME type so that it can be connected to all types of central processor units having such an interface.

This first object is achieved by the fact that the graphics card and interface between a central processor (1) communicating asynchronously with this card by an external bus and a video monitor (9) characterized in that it comprises:
- a set of video memories (45, 46) of capacity at least equal to the number of display points desired on the monitor (9),
- at least one group of random access memories (43, 44 or 41, 42) for storing graphics application software,
- a circuit (40) controller of the video system, managing the addresses of the different memories in order to refresh the memories, the video display and the updates of the data or programs and delivering the video signals;
- a circuit (60) for serializing the delivered data by the video memory (45, 46) in cadence with a video clock H1;
- a graphics processor (30) clocked by a clock (HO) and working in synchronism with the circuit (40) of the video system controller so as to execute the software programs contained in the random access memory group;
- an interface circuit (20 to 22) between the external bus (VME) and the card buses and an arbitration circuit (23 to 27) between the graphics processor (30), the video system controller (40 ) and the external bus (VME);

A second object of the invention is to propose a graphics card, interface, mouse keyboard which makes it possible to unload the central unit from the management of the display and the mouse, while having a high graphic resolution and by inserting on the same card, keyboard interface and sound generator.

This second object is achieved by the fact that the card further comprises: an input-output interface circuit (70) between a mouse (71), a keyboard (72) and the graphics processor (30) or the bus external (VME), this circuit being clocked by a third clock (H2).

A third goal is to relieve the processor of mouse management.

This third goal is achieved by the fact that the circuit (70) of the video system controller generates interruptions due to an action on the keyboard directly on the external bus (VME) and interruptions due to an action on the mouse in the direction of the graphics processor (30).

A fourth goal is to provide a graphics card that allows changes to the display graphics either by using the card's microprocessor or by a circuit specialized in block modifications.

This fourth object is achieved by the fact that the card comprises a logic block transfer circuit (50) controlled by logic (51), selected by the most significant address line (A23), and circuits logic (47 to 49) for selecting memories (41 to 46), the logic (51) ensuring sequencing control to transform a memory read-write instruction into a read-modify-write instruction by the circuit (50) and means (31) for isolating the graphics processor (31) from the memories.

A fifth object of the invention is to allow the loading and initialization of the system to be controlled from the central processor.

This fifth object is achieved by the fact that the card comprises a control register (29) making it possible, during the initialization of the system, to load the memories of the card and to load the different registers of the different circuits (50, 30, 40, 70).

A final goal is to ensure that during the serialization of the information to be transmitted to the graphic monitor, the blocking of the serialization of the data is carried out in time.

This latter object is achieved by the fact that the circuit (60) for serializing the data for the video display comprises an input for loading (LD) the data to be serialized from the registers of the video memory (45-46), allowing d '' invalidate the loading by the erasure signal (BLANK) coming from the circuit (40) of the video system controller.

• La figure 1 représente une vue schématique des fonctions essentielles de la carte coopérant avec le bus VME et le processeur central;
• La figure 2 représente le schéma électronique des circuits d'entrée de la carte;
• La figure 3 représente le schéma du branchement du microprocesseur graphique de la carte;
• La figure 4 représente le schéma électronique du branchement de l'unité de contrôle du système vidéo et des mémoires associées;
• La figure 5 représente le schéma électronique du circuit de transformation des informations graphiques;
• La figure 6 représente le schéma électronique du circuit de sérialisation des données grahiques à transmettre au moniteur;
• La figure 7 représente l'interface clavier, souris de la carte;
• La figure 8 représente le schéma électronique des circuits générateurs de sons.

Other advantages and characteristics of the present invention will appear more clearly on reading the description below made in the appended drawings in which:

• FIG. 1 represents a schematic view of the essential functions of the card cooperating with the VME bus and the central processor;
• FIG. 2 represents the electronic diagram of the input circuits of the card;
• FIG. 3 represents the diagram of the connection of the graphics microprocessor of the card;
• FIG. 4 represents the electronic diagram of the connection of the control unit of the video system and of the associated memories;
• FIG. 5 represents the electronic diagram of the circuit for transforming graphic information;
• FIG. 6 represents the electronic diagram of the circuit for serializing the graphic data to be transmitted to the monitor;
• FIG. 7 represents the keyboard, mouse interface of the card;
• FIG. 8 represents the electronic diagram of the sound generating circuits.

In FIG. 1, the central processor (1) is in communication with the card which is the subject of the invention by means of a bus external to the card of the type (VME) or similar or compatible with a bus of the VME type constituted an address bus (A) comprising 24 address lines, a data bus (D) comprising 16 data lines and a control bus (C) comprising the control lines. This central unit (1) operates with a clock working at a rate different from that of the graphic interface card, keyboard and mouse, object of the invention. This interface card is connected to the data bus of the external bus (VME) by a buffer (20), to the lines (1 to 20) of the address bus (A) by a buffer (21), lines (21 to 23) of the address bus and lines of the control bus by an arbitration and synchronization logic ( 23 to 27). The buffer (20) is connected by a video data bus (VBD) comprising 16 lines numbered from 0 to 15, on the one hand to a set of random access memories (41, 42, 43, 44) and on the other to through a buffer (31), to a 16-bit microprocessor (30) sold by the MOTOROLA company under the reference (MC6810). The video data bus (VBD) is also connected to a second set of random access memories (45, 46) will constitute what will be called hereinafter the "VIDEO RAM" which are used to store bit by bit graphic information. The first two groups of memories (41, 42); (43,44) are connected by a memory address bus (AM) of 9 lines, to a circuit (40) controller of the video system marketed by the firm TEXAS INSTRUMENT under the reference "TMS9161". The group of video memories (45, 46) is connected to 8 lines of the 9 bus lines (AM). The microprocessor (30) and the controller (40) are synchronized with each other by a clock signal (SHO) delivered by a common clock (HO) operating at a frequency of 10 MHZ. The video system controller (40) is connected to the video address bus (VBA) and to the given video bus (VBD) as described later with reference to FIG. 4. A clock (H1) delivers on the one hand the clock signal to a serializer (60), on the other hand, this same signal to a logic circuit (62, 65) whose output (VH1) is connected to the video clock input of the circuit (40). This circuit (40) also delivers the horizontal and vertical synchronization signal necessary for the display. The erasure signal (BLANK) is delivered to a control logic (61) which is itself connected by its output to the circuit (60), serializing the information to be displayed. The serializer (60) is connected by 16 lines of video data (VD) to the group of video random access memories (45, 46), and serializes the data signals for deliver them to a video monitor (9) responsible for displaying them. The arbitration logic (23 to 27) is connected on the one hand to the graphics processor unit (30) constituted by the microprocessor (68010) and on the other hand through a control register (29) to this microporcessor (30). A logic circuit for processing the interruptions (73) is connected on the one hand to the microprocessor (30), on the other hand to the outputs of a circuit (70) asynchronous communication interface adapter. On this circuit (70) are connected as input a mouse (71) and a keyboard (72). This adapter (70) is connected by 8 lines to the data bus (VBD) and by 5 address lines to the address bus (VB1) of the card, and receives a clock H2. A sound generator circuit (80, 82) is also connected to a number of data bus lines (VBD). A bit block transfer circuit (50) is connected on the one hand by 16 lines to the data bus (VDB) on the other hand by 3 control lines to the address bus (VBA) and at the end by lines control to a logic (51) for controlling the block transfer circuit (50). This control logic (51) being selected by line 23 of the address bus (VBA), and receiving on another input the signal HO.

The card represented in FIG. 1 therefore essentially comprises the following functions:
interface with a standard bus (VME);
video controller operating at 10 MHZ;
1 mega bit video memory;
1 mega byte RAM memory;
microprocessor (68010) for discharging the central microprocessor for graphics functions;
a serial interface circuit (70) constituted by a circuit marketed by the firm MOSTEK under the reference (MK68564) operating as a serial interface for a mouse and a keyboard;
a sound generator constituted by a circuit marketed by the firm TEXAS INSTRUMENT under the reference (SN 76496N);
a bit block transfer circuit (50) sold by the firm PACIFIC MOUNTAIN RESEARCH INC under the reference (PMR 96016).

All the connections of the various circuits presented in the general diagram of FIG. 1 will now be described in connection with FIGS. 2 to 8. The 16 lines of the data bus (VME) (BDO: 16) are connected to the bus of card internal data (VBDO: 16) by a directional buffer (20) validated as input to the card by a signal (ENAVME /) for validation of the external VME bus and validated as output to the external bus (VME) by a signal (VCBWR). The notation (ENAVME /) means that this signal is the inverse of the signal (ENAVME) and it is the same for the other signals of the description. 24 lines of the address bus (VME) sixteen (BAO1: 16) are sent on a unidirectional buffer (21) whose output is connected to the 16-bit video address bus (VBA01: 16). This unidirectional circuit (21) is validated as an input by the signal (ENAVME /). The following 4 lines of the address bus (VME) (BA17: 4) are connected, by a unidirectional buffer (22) operating as input to the card, to the lines (VBAM17: 4) which ensures through the video controller circuit ( 40) the selection of memory groups. The input of addresses to the video controller circuit is validated by the signal (ENAVME /). The last 3 lines of the address bus (VME) (BA21: 3) as well as the line (IACK /, interrupt acknowledgment) of the control bus (VME) and the line (BAS /, validation of bus addresses) of this control bus (C) are connected to the inputs (1, 2, 3) of a programmable logic network (23) (PAL). This circuit (23) also receives the input signals (MPUBGT /, CSREG /, ENAVME /, VSCALE /, VCBWR /, DTA1 /, DTA2 /,) whose meaning we will see later. This circuit (23) outputs a signal (MPUBRQ /), indicating a bus request from the central processor (1), this signal being sent to the input (BR) (bus request, bus request) of the microprocessor (68010) represented by the circuit (30) of FIG. 3. The output signals (BGA /) (bus tuned) (VCBAS /) (validation of the addresses of the bus) (ENADS /) (validation of the data) and ( ENDTA2 /) are synchronized by a circuit (24) constituted by a set of flip-flops receiving the same clock signal (SCLOCK /) coming from the output (2810) of the clock circuit (28). The programmable logic network (23) also receives as input the signal (MPUDTAC /) generated by the output of a 3-state buffer circuit (268) of FIG. 2B. A buffer circuit (25) for memorizing the input of the control signals from the external control bus (VME) receives on its inputs the lines (BDS0, BDS1 /) and (WRITE /) and delivers during validation by the signal (ENAVME /) the card control signals (VCBDS0 /, VCBDS1 /) which are used respectively to distinguish the most significant and the least significant data and the signal (VCBWR /) which is sent to an inverter (251) to generate the signal (VCBWR) validating a data output towards the external bus (VME). A fourth input (254) of the buffer (25) receives the signal (VMEDTAC /) and outputs a signal (BDTACK) to the control bus (VME) this signal indicating an acknowledgment of the data. The signals (SYSRESET /) from the control bus (VME) is sent to two inverters (255, 256) connected in series. The output of the inverter (256) generates the signal (RESET /), which is the system reset signal. A buffer (257) whose output is connected to the line (BIRQ /) of the bus (VME), transmits the interruption requests provided by the signal (INTRQ /), signal delivered by the output (IT /) of the input-output serial interface (70 fig. 7). The outputs (VCBDSO /) and (VCBDS1 /) of the buffer (25) are sent on two OR doors with two inputs respectively (258, 259) one of the two inputs of which is provided by the output (Q3) of the register (24) whose input (I3) receives the data validation signal (ENADS /). The output of the OR gate (258) delivers the validation signal for low addresses (VCBCEL /), which is sent on the one hand to the input (CEL) of the circuit (40) formed by the video system controller and d on the other hand on an entry of an OR gate (261) with two entries. The output of the OR gate (259), delivering the signal for enabling high addresses (VCBCEH /), is sent to the input (CEH) of the circuit (40). The address lines (VBAM17 to 20) are connected to a NAND gate (260) with four inputs, the output of which is itself connected to the second input of the OR gate (261). The output of the AND gate (260) is also connected to an inverter (262) which outputs the signal (CSVSC /), signal for selection of the video system controller (40). This signal (CSVSC /) is sent to the selection input of the circuit (CS /), of the circuit (40) constituting the video system controller. The output of the OR circuit (261) delivers the signal (CSREG /) signal for selecting the registers, which is sent to the input for disabling a decoder (263). This decoder (263) receives on its two inputs (A1, AO) the lines (VBAM16) and (VBAM15) respectively. The output (Q0) of this decoder (263) delivers the signal (CSMAR /), signal for selection of the control register (29). The output (Q1) of this decoder (263) delivers the signal (2631) which is transmitted to the input of the inverter (264 Fig. 2B), the output of which is connected to an input of a NAND gate (265) with two inputs, the second input of which receives the signal (VCBWR) supplied by the bus (VME). This NAND gate (265) delivers a signal (CSBLT /) which is the selection signal for the bit block transfer circuit (50 FIG. 5). The output (Q2) of this decoder (263) delivers the signal (CSON /) which is the signal for selecting the circuit sound generator (80 Fig. 8). The output (Q3) of the decoder (263) delivers the signal (CSSIO /) which is the selection signal of the input-output serial interface circuit (70 Fig. 7). The activation of the signals (CSMAR /, CSBLT /, CSSON /, CSSIO /), for selection of the respective boxes (29, 50, 80, 70) is given by the table below.

The output (CSREG /) of the OR circuit (261) is also connected to an OR gate (266) with two inputs, the second input of which receives the signal (VBAM16). The output of this OR circuit (266) is connected to the input (NS) (setting a flip-flop (267) to 1 whose clock input (H) receives the signal (SNDTAC /) from the circuit ( 80) of the sound generator and the reset input (NR) receives the signal (VCBAS) for validation of the addresses of the bus coming from the circuit (23). The output (Q /) of this flip-flop (267) is sent on the validation input of a 3-state buffer (268), the input of which receives a logic level 0 and the output provides the signal (MPUDTAC /) data acknowledgment signal for the microprocessor (1) and for the circuit input-output serial interface (70). This signal (MPUDTAC /) is sent on the one hand on the input (DK) of the serial input-output interface (70) on the other hand on an input of an OR gate (36) with two inputs, the second input of which receives the signal (ENADTA), signal which comes from (to be completed). output from the OR gate (36) delivers a signal to the input (DK) of the microprocessor (30) data acknowledgment signal for the microprocessor. The signal (VCBAS /) of the circuit (23) is sent to the input of the inverter (340) whose output delivers the signal (VCBAS) to the loading input (PL) of a counter (34) of which the clock input (CP) receives the signal (E) delivered by the output (E) of the microprocessor (30). This output (E) delivers a validation signal whose clock period is equal to 10 clock periods of input from the microprocessor. The output (TC) of this counter (34) delivers the signal (BERR /) to the input (BERR) of the microprocessor (30), this input informing the processor that a problem has occurred in the running cycle. . This signal (BERR /) (bus error) makes it possible to prohibit read access to the control register (29), the bit block transfer circuit (50) and the sound generator (80). When trying to read one of these registers, the signal (CSREG /) is active and the signal (VCBAS /) is also active. This signal (VCBAS) resets the flip-flop (267) to 0 and consequently prevents the generation of the signal (MPUDTAC) which is the data acknowledgment signal for the microprocessor. This signal (MPUDTAC) not being generated the input (DK) of the microprocessor (30) does not receive the acknowledgment signal and therefore after ten periods the signal (E) is generated by the microprocessor ( 30) and will generate through the counter (34) validated by the signal (VCBAS), the signal (BERR /) indicating to the microprocessor (30) indicating an error.

The output (CSMAR /) of the decoder (263) is sent to the input of an inverter (291) whose output is connected to an input of a NAND gate (290). The second input of the NAND gate (290) receives the signal (VCBWR) which comes from the output of the inverter (251 Fig.2A). The output from the NAND gate (290 Fig. 2B) delivers the signal (WRMAR /) write signal from the control register (29) consisting of a set of eight selectively addressable flip-flops. The signal (WRMAR /) is sent to the validation input of all eight flip-flops (29). The reset input (NR /) to "0" of the flip-flops of the circuit (29) receives the signal (RESET /) from the output of the inverter (256 fig.2A). The inputs (A0 to A3) for selective addressing of the flip-flops of the circuit (29) receive the address lines (VBAO1 to 03). These address lines make it possible to individually select each of the flip-flops (Q0 to Q7). The value provided by the seventh line (7) of the data bus (VBDO7) makes it possible to position the output of the selected flip-flop at 0 or 1. To make one of the flip-flops active, the signal (CSMAR /) for selecting the register (29) must be made active. For this it is necessary that the address lines (VBAM17 to 20) are at level 1 and that the address lines (15 and 16) (VBAM15, 16) are at level "0". This corresponds to an address (7EOOOX) in hexadecimal value, X representing the values that can be coded by the lines of the address bus (BVA01 to 03). The functions of the flip-flops and the signals delivered by the outputs of the latter are given by the following table:

The signal (MPUHLT /) delivered by the output (Q2) of the third flip-flop of the register (29) is sent to the input validation (I) of a buffer (35) whose data input (IO) receives a logic "0" and the output (5) transmits the signal (HT) to the input (HT) of the microprocessor (30 ). This signal (MPUHLT) is used to stop the processor at the end of the current bus cycle.

In Figure 3 there is shown the graphics microprocessor (30) which works with a signal (SCLOCK) of 10 Mega Hertz provided by a clock (H0) operating at 20 mega Hertz connected to the clock input of a flip-flop ( 281) whose output (Q) delivers the signal (SCLOCK) at the frequency of 10 Mega Hertz. The output (SCLK) of the 20 Mega Hertz oscillator (HO) is also sent to the clock input of a second flip-flop (282) whose validation input (D) receives the signal (BGACK /) for acknowledging the allocation of the bus and the output (Q) delivers the signal (ENAVME /) validation signal from the external bus (VME) enabling the buffers (20, 21, 22, 25) of the card to be validated graphic. The 16 data inputs / outputs (D0 to DF) of the graphics processor (30) are decoupled, by a bidirectional buffer (31) from the data bus (VBD0: 16) of the graphics card. The purpose of this buffer (31) is to isolate the graphics processor (30) from the card's data bus for block transfer operations during the use of the circuit (50) as will be seen below. To do this, the output (AN) corresponding to the address bits (VA23) of the graphics processor (30) is sent to the blocking input (CD) of the buffer (31). Activation of this line (VA23) causes blocking of the buffer (31) and isolation of the data bus of the graphics card (VBDO: 16) of the 16 input lines of the graphics processor (D0 to DF). The 20 address input-outputs (A1-AK) are connected on the one hand to the internal address bus on the card (VBA01: 16) coming from the buffer (21) and on the other hand to the memory address bus from the card (VBAM17: 4). The outputs (US, LS) corresponding to the validation of the upper data, respectively lower, are respectively connected to the buffers (252, 251) to deliver the respective signals (VCDBS1 /, VCDBS0 /). The address validation output (AS) is connected to the output of the circuit (23) delivering the signal (VCBAS /). The output (WR) (read, write) is connected to the output of the buffer (253) delivering the signal (VCBWR). This signal (VCBWR) indicates a write or a read. The input (BR) of the circuit (30) indicating a bus request receives the signal (MPUBRQ /) coming from the circuit (23) and indicating to the microprocessor (30) a bus request from the external bus (VME) and of the unit centered on 1 (CPU). The output (BG) indicates to the requesting circuit (23) that the microprocessor (30) has taken into account its request presented on the input (BR) and signals that it will cede the buses at the end of the current bus cycle. This output is sent to the input (MPUBGT /) of the circuit (23). The outputs (CO, C1, C2) of the microprocessor (30) indicate the state of the processor as to whether it is in user mode, in supervisor mode or in interrupt recognition. These outputs are sent to a NAND gate (32) with four inputs, the fourth input of which receives the signal (VCBAS) supplied by the output of the inverter (340). The output of this NAND gate (32) is sent to the input (PA) of the processor (30) and constitutes the signal (MPUVPA /). This signal (MPUVPA /) valid peripheral address indicates to the microprocessor that the data transfer will be synchronized with the signal (E) because a peripheral wishes to converse with the processor synchronously. This entry also indicates that the processor will be in autovectorized mode in the event of an interruption. This is the case when the processor (30) receives an interrupt request from the system video controller circuit (40) or an interrupt from the mouse (71) or an interrupt from the control register (29) issued by the output (Q4) from this register and caused by the CPU (1) at through the external bus (VME). In this case, the outputs (C0, C1, C2) are at level "1" and the signal (VCBAS) is also at level "1", which activates the signal (MPUVPA /) which puts the processor in mode autovectorized. In this autovectorized mode, the interrupt vector number is generated internally depending on the level. The interrupt levels are determined by the interrupt inputs (LO, L1, L2), the input (L0) corresponds to level 1 and receives the signal (VSCINT) which represents the interruptions generated by the video controller (40) . The input (L1) corresponds to the level 2 interruptions and receives the signal coming from the output (Q /) of a rocker (73) indicating an interruption coming from the second channel (B) of the serial line of the circuit (70) , this channel (B) corresponding to the mouse. The input (L2) corresponds to level 4 and receives the signal (MPUINT /) coming from the output (Q4) of the register (29), this signal indicating an interruption generated by the control register of the card, this interruption being activated on the bus (VME). Consequently, there is no priority encoder on the interruptions and the presence of a level 2 and 4 interruption at the same time corresponds to a level 6 interruption. The elimination of the encoder therefore makes it possible to gain space on the card so that you can have all the functions you want to put on this card.

The connections of the video controller (40) with the memory groups (41 to 46), the arbitration logic and the graphics processor (30) will now be described in connection with FIG. 4. The video system controller circuit (40 ) receives on its clock input (CLK) the clock signal (SCLOCK) coming from the output (Q) of the flip-flop (281) and delivering a synchronous signal of the clock signal of the graphics processor (30). The outputs (BLANK, HSYNC, VSYNC) respectively deliver the signals erase, horizontal sync, and vertical sync to the video monitor. The inputs (CAD to 7) are connected to the address lines (01 to 08) of the address bus (VBAO1: 8). The ninth address input (CA8) receives the signal (VBAM 18) from the output of the buffer (22). These eight inputs (CA01 to 8) are multiplexed on the outputs of the memory addresses (MAO to MA8) during the column address intervals. The inputs (RAO to RA8) receive the lines (VBA9 to VBA17) from the internal address bus of the card. These nine address inputs are multiplexed to the outputs (MAO to MA8) during the line address intervals. The inputs (RS0 and RS1) of the box used to determine which of the 4 line address validation signals, provided by the outputs (RAS0 to RAS3) of the circuit (40) are active. These inputs (RS0, RS1) receive the address lines (VBAM19 and VBAM20) respectively. The input (CEL) for validation of the low column addresses receives the signal (VCBCEL) coming from the output of the OR gate (258). The input (CEH) for validation of the tall column addresses receives the output of the OR gate (259) constituting the signal (VCBCEH). The input (R / W) receives the signal (VCBWR /) coming from the output of the buffer (253). The address lock validation input (ALE), used to initialize the controller cycle specified by the values present at the inputs (CS, RA0 to 8, CA0 to 8, RS1, RS0 and FS0 to FS2), receives the signal (VSCALE /) from the output of the register (242). The active edges of this signal are synchronous but offset by half a period with respect to the active edges of the clock signal (SCLOCK) of the video controller (30). The data inputs (D0 to D7) of the video controller (40) are connected to the data bus (VBD0: 8). These inputs are used exclusively to load the internal registers of the video controller during card initialization. The output (RDY) of the circuit (40) is connected to the output (MPUDTAC) of the buffer (268) and to the input of the OR gate (36) to indicate an acknowledgment of data reception to the processor (30) since the latter has requested a memory cycle. This output (RDY) is also connected to the input (DK) of the input-output serial interface (70) and to an input (4) of the circuit (23) as well as to the input of the register (244 ) of the circuit (24). The input (HOLDACK) of the circuit (40) being at logic level "1" indicates that the signal (RDY) is active at the low level. The output (INT /) indicating interrupt requests is connected to the input (LO) of the processor (30) corresponding to the level 1 interrupts. This input (LO) and the input (L2) are each connected by a resistance R at a reference voltage +5 volts, this assembly having the aim of guaranteeing the high logic level as a rest state. The input (RESET) of the circuit (40) is connected to the output of the inverter (256) of FIG. 2A. The input (VIDCLK) of the circuit (40) receives the signal (SVIDCLK) coming from the output of the circuit (65) of figure 6. This input makes it possible to supply the video clock signal which is responsible for the generation of the synchronization for synchronization and erasure signals and also logic for generating internal requests for refresh of the display and random access memories. The outputs (CASLO and CASH1) of the circuit (40) make it possible to select in a memory group the bits which correspond to the most significant or the least significant, that is to say the data from 0 to 8 or from 8 to 16. The output (CASLO) is connected to an input of an OR gate (48), a second input of which receives the signal (ENACAS /), delivered by an output (510) of a programmable logic circuit (51) FIG. 5A for controlling the bit block transfer circuit (50). The output of the OR gate (48) is connected to each of the inputs (CS) for selecting the memory boxes corresponding to the boxes of the least significant bits of each memory group. The output (CASH1) is connected to an input of an OR gate (49), a second input of which also receives the signal (ENACAS /). The output of the OR gate (49) is connected to each of the memory box selection inputs (CS) corresponding to the most significant bits in each memory group. Thus the output of the OR gate (49) is connected to the inputs (CS) of the memory boxes (42, 44 and 46). While the output (48) is connected to the memories (41, 43, 45). The output (RAS0) of the box (40) makes it possible to select the first group of memories constituted by the boxes (41 and 42). The output (RAS1) makes it possible to select the second set of memories constituted by the boxes (43, 44). The output (RAS2) makes it possible to select the third group of memories constituted by the video random access memories (45, 46). Each memory receives on its input (W) the signal coming from an OR gate (47) of which a first input receives the output (W /) of the box (40) and the second input the signal (ENAWR /) coming from the output (511) of the logic circuit (51) controlling the bit block transfer circuit (50). The nine outputs (MAO to MA8) of the box (40) are connected to each of the nine or eight input lines of the memory boxes. The output (TRQE) of the circuit (40) is connected to the inputs of the same name of the groups (45, 46) of the video random access memories. This output (TRQE) delivers the transfer signals from the registers and validation of the outputs which allow direct control of the output buffers of these video RAMs. The memories are organized into two groups of 256 KMOTS of 16 bits each. Each group consists of 16 dynamic memory boxes of 256 Kbits mounted on two bars (41, 42) of eight boxes each for the first group and on two other bars (43, 44) of eight boxes each for the second group of memories vivid. The video memories (45, 46) form a third group which consists of 16 dual access memory boxes of 64 Kbits marketed by TEXAS INSTRUMENTS under the reference "TMS4161" and mounted on four bars (45, 46) of four boxes. The addresses (VBAM17 and VBAM18) are connected respectively to the inputs (RA8, and CA8) of the system video controller (40) to have a continuous address space with the different memory organizations, depending on what we are dealing with. first and second group of random access memories (41, 42, 43, 44) or to the group of video memories (45, 46) of 64 K-Bits. In this case (CA8) and (RA8) are not taken into account by the memories (45, 46) of this group because they have only 16 address bits (CA0 to CA7) and (RA0 to (RA7) The selection of a group of memories among the three is done with the address lines (VBAM19 and VBAM20) according to the table below which gives the organization of the address space of the card seen by the bus. (VME).

The video memories (45 and 46) comprise, as can be seen in FIG. 4, two types of outputs, a first set of outputs (VDBO: 8) and (VBD08: 8) connected to the internal bus of the card (VBD0: 16 ) and a second set of outputs consisting of 250-bit shift registers used to transfer the content of the memory to the video serializer (60) figure 6. These outputs are noted (VD OO: 8) and (VDO8: 8) and are connected to the inputs (D0 to D15) of the serializer (60). The sequencing is controlled by the output (TRQE) of the circuit (40) and the clock input (SHCLK) coming from the output of the circuit (66). The video controller (40) has three inputs (FS0, FS1, FS2) which make it possible to identify and fix the memory access modes, which can be direct and also the accesses to the internal registers of the circuit (40). The input (FS2) is permanently wired at a logic level "0" and the other inputs (FS1, FS0) respectively receive the outputs (Q1 and Q2) from a decoder (48) which generates the signals (VSCFS1 and VSCFS0 ) according to the address bits (17, 18). The inputs (A0 and A1) of the decoder (480) are respectively connected to the lines (VBAM17 and VBAM18). The decoder validation input (480) is connected to the output of a NAND gate (470) which receives the lines (VBAM19 and VBAM20) on its two inputs. The table below gives the values present at the inputs (FS0 and FS1) as a function of the values on the address lines (VBAM), that is to say the hexadecimal addresses sent on the bus (VME). Depending on the values (FS0 and FS1) one obtains either direct accesses of the graphics processor (30) on the memories or the video memories either indirect accesses, or accesses registers. The table below diagrams the operation of the decoding and of the video circuit (40).

• 1^o) Accès en lecture ecriture du Méga-Octet de mémoires vives et du Méga-Bits de mémoires vidéo;
• 2^o) Génération de cycles de refraichissement pour ces mémoires. Le contrôleur vidéo est programmé pour générer ses cycles de rafraichissement dans chaque retour de ligne vidéo.
• 3^o) Génération de cycles de rafraichissement pour l'écran graphique par transfert du contenu de la mémoire vidéo vers le sérialisateur vidéo par les sorties (VD) des registres à décalage des mémoires (45, 46).
• 4^o) Génération des signaux de synchronisation horizontale et verticale et d'effacement pour l'interface vidéo.

The video controller (40) essentially performs four functions on the card:

• 1 ^o ) Access in read and write mode of the Mega-Byte of live memories and of the Mega-Bits of video memories;
• 2 ^o ) Generation of cooling cycles for these memories. The video controller is programmed to generate its refresh cycles in each video line feed.
• 3 ^o ) Generation of refresh cycles for the graphic screen by transferring the content of the video memory to the video serializer by the outputs (VD) of the memory shift registers (45, 46).
• 4 ^o ) Generation of horizontal and vertical synchronization and erasure signals for the video interface.

The bit block transfer circuit (50) and the command and control circuit (51) of this circuit will now be described in connection with FIG. 5A. The command and control circuit (51) constituted by a logic and programmable network which receives on its clock input the output signal of an inverter (513) whose input receives the signal (SCLK) coming from the output of the clock (H0). This programmable logic network (51) synchronized on the clock (H0) receives on a first input the signal (BGACK /) of acknowledgment of receipt of the provision of the bus, on a second input the signal (VCBAS /) indicating the validation of the addresses of the bus, on a third input the signal (VA23) coming from the processor (30), on a fourth input the signal (VCBWR) coming from the output of the inverter (251) figure 2.A. On a fifth input the signal (DTA1 /) coming from the output of the fifth register of the circuit (24) of figure 2.A. On the sixth input the signal (MPUDTAC /) coming from the output of the buffer (268). The output (514) delivering the signal (LDSCR /) indicating the loading of the source address is sent to the input (LDSRC /) (500) of the circuit (50). The output (515) delivering the signal (LDDEST /) indicating the loading of the destination address is delivered to the input (LDDEST /) (501) of the circuit (50). The output (516) delivering the signal (BLTOE /) is sent to the input (OE /) (502) input for enabling the block outputs. The circuit (50) receives on its inputs (A1 to A3) the signals (VBAO1: 3) and on its inputs (DO to D15) the sixteen lines of the data bus (VBD 0: 16). The inputs (A1 to A3) of the circuit (50) make it possible to select the internal registers of this circuit and the data inputs (DO to D15) make it possible to work on the memory data addressed by the processor (30). The circuit (50) receives on its input (503) (CS /) for selecting the circuit the signal (CSBLT /) coming from the output of the door (265) in FIG. 2A.

This transfer circuit makes it possible to modify the data generated in writing by the processor (30) and by the use of suitable software makes it possible to accelerate the operations of screenshots. To do this, these circuits load the data indicated by a source address transform them according to established rules and send this data to a destination address in the video memory. This circuit (50) comprises a certain number of registers which can be initialized by accesses to determined addresses so as to effect certain transformations such as rotation or video reversal or other more complex functions, according to the programming of the registers. of the circuit (50). The access addresses to these registers, seen from the bus (VME) are between the values (7E1000 and 7E800E) in hexadecimal or between the values (1E8000 and 1E800E) in hexadecimal for the graphics processor of the card. The different registers of the bit block transfer circuit (50) are addressed according to the table below:

• 1^o) Lecture des données de l'adresse source;
• 2^o) Lecture des données de l'adresse de destination;
• 3^o) Modifications des données de la destination;
• 4^o) Ecriture à l'adresse à destination;

Pour valider la fonction de transfert de blocs de bits le processeur (30) exécute une instruction du type "MOVE SOURCE DESTINATION" qui est une instruction de déplacement du contenu de l'adresse spécifiée par SOURCE vers l'adresse spécifiée par DESTINATION. Cette fonction est exécutée par le processeur (30) en même temps que l'instruction "MOVE", en positionnant le bit d'adresse (VA23) à la valeur 1, les poids faibles contenant l'adresse des mots mémoire sélectionnés. Ceci revient à dire que dans le cas de l'utilisation de la fonction transfert de blocs on travaille sur la zone d'adresse vue du bus externe (VME) comprise entre et 16 Méga bits alors que sans la fonction de blocs de transfert on travaille sur la zone d'adresse comprise entre 0 et 8 Méga bits. Cette instruction "MOVE SOURCE DESTINATION" comprend une lecture du contenu de l'adresse spécifié par SOURCE puis une écriture de ce contenu à l'adresse spécifié par DESTINATION. Avec la fonction transfert de blocs de bits cette instruction est modifiée pour fonctionner de la façon équivalente à une instruction lecture modification écriture. Cette transformation va maintenant va être explicitée en liaison avec la figure 5B qui est une représentation des diagrammes temporels des différents signaux intervenant dans un transfert de blocs de bits.Once the registers have been addressed, they are initialized with the desired values to operate the circuit (50) in the desired manner with the appropriate data values from the data bus (VBD). Once the register initialized, the graphics processor (30) of the card can access the video memory (45, 46) with the bit block transfer function. From this moment each bit block transfer cycle consists of four phases:

• 1 ^o ) Reading of the source address data;
• 2 ^o ) Reading of the destination address data;
• 3 ^o ) Modification of the destination data;
• 4 ^o ) Write to the destination address;

To validate the bit block transfer function, the processor (30) executes an instruction of the "MOVE SOURCE DESTINATION" type which is an instruction to move the content of the address specified by SOURCE to the address specified by DESTINATION. This function is executed by the processor (30) at the same time as the "MOVE" instruction, by positioning the address bit (VA23) at the value 1, the least significant ones containing the address of the selected memory words. This amounts to saying that in the case of the use of the block transfer function, one works on the address area seen from the external bus (VME) between and 16 Mega bits while without the transfer block function one works on the address area between 0 and 8 Mega bits. This "MOVE SOURCE DESTINATION" instruction includes reading the content of the address specified by SOURCE and then writing this content to the address specified by DESTINATION. With the bit block transfer function, this instruction is modified to function in the same way as a read modification write instruction. This transformation will now be explained in connection with FIG. 5B which is a representation of the time diagrams of the various signals involved in a transfer of bit blocks.

The first phase of the block transfer cycle consisting of a source read appears as a normal memory read cycle for the processor (30) except that the signal (LDSRC /) is activated by the programmable logic network (51) following the presence of the signals (VA 23) and (VCBAS /). The active signal (LDSRC /) loads the source data into the circuit (50) when the data read is stabilized on the internal data bus (VBD). During the following phases the processor (30) writes to the destination address. In this phase, the data buffer (31) remains in the high impedance state following the activation of the signal (VA23) on the invalidation input of this buffer (31). The programmable logic network (50) puts at level "1" the output (511) representing the signal (ENAWR /), signal for disabling writing in the memories. This signal (ENAWR /) deactivates the signal (RAMWR /) via the gate (47). In this way, the write cycle of the processor (30) is transformed into a memory read cycle for the second phase of the bit block transfer cycle. The stabilization of the data is signaled by the activation of the signal (MPUDTAC /) by the circuit (40) and this signal sent to an input of the circuit (51) generates the signal (LDDEST /) which loads the destination data in the circuit ( 50) transfer of bit blocks. The second phase corresponds to arrow 2 in the diagram in Figure 5.B. After the activation of the signal (MPUDTAC /) the signal (DTA1 /) becomes active on the second falling clock edge following this activation. This corresponds to the wiring diagrams in the register (244). Following the activation of the signal (DTA1), this signal sent to the input of the register (51) causes the deactivation of the signal (LDDEST /) (arrow 5 in FIG. 5B) and the rising clock edge which follows this deactivation causes signal level 1 (ENACAS /). This signal (ENACAS /) sent to the inputs of the doors (48, 49) of Figure 4, causes the blocking of the column address validation signals (RAMCAS0 /, RAMCAS1 /). This third phase indicated by arrow 3 in Figure 5.B ends the reading cycle on the memory and one enters the data writing cycle, modified by the circuit (50), which is constituted by phase 4. After phase 3 at the falling clock edge following this phase the circuit (51) activates the signal (BLTOE /) and deactivates the signal (ENAWR /) so as to validate the write signal (RAMWR /). During this time the circuit (50) executes the functions programmed in advance on the destination data. When the modified destination data is stabilized on the bus, i.e. on the rising clock edge following the activation of (BLTOE) the circuit (51) again activates the signal (ENACAS /) to select at memory again. During this time, the write signal (RAMWR /) remains validated and consequently, the writing to the destination address of the modified data is executed. The passage to "0" of the signal (ENACAS /) allows the falling clock edge following this passage to let the microprocessor finish its destination write cycle in a normal manner. Following the signal rise (VCBAS /) and consequently the deactivation of (VCBCEL /), the circuit (40) deactivates the signal (W /) which itself will cause the deactivation of the circuit output (BLTOE /) PAL (51) and therefore the end of data output for the block transfer circuit (50). Consequently, with this circuit, it was possible to carry out modifications on sets of 16-bit words contained in the memories by a simple instruction to move from one address to another address, modified by the circuit into a read-modify instruction. -writing. Since this circuit (50) can perform relatively complex functions, we understand the advantage of such a device because it allows modifications to the video display on 16-bit word blocks without directly involving the processor (30 ) associated with a word modification program which would be more complex and therefore longer to execute. On the other hand, when one will have to make modifications of the information stored in memories on a part of a word or a block it will be possibly more interesting to do it directly by the microprocessor (30) since in this case there n It is not necessary to initialize the circuit (50) which each time requires a certain number of program instructions for the microprocessor. This circuit (50) makes it possible to obtain a merged source word by specifying which bits are selected from the registers containing the source word and the previous source word. The shift register indicates by its bits that it is a right or left rotation and the amount of rotation. The function register specifies the Boolean function which will combine the merged source word, the semitone register and the data of a register containing the destination address information. Finally, the merge mask register specifies the part of the word contained at the destination address which must be modified.

The interface circuit (70) parallel input-output will be described with the help of FIG. 7. This interface circuit (70) receives on its input (RS) reset to "0" the signal (RESET / ) from the output of the inverter (256) of Figure 2.A. Its input (CS) for selecting the box receives the signal (CSSIO /) coming from the output Q3 of the decoder (263) of FIG. 2.A, which delivers the signal for selecting the box. The input (RW) receives the erection or read signal of the box coming from the output of the buffer (253) which delivers the signal (VCBWR /). The input (X1) of the baud rate generator receives the output of an oscillator (H2) working at a frequency of 2.45 Mega hertz. The inputs (A1 to A5) of the box (70) are connected to the lines (VBAO1 to VBAO5) of the address bus of the card so as to address each of the 25 internal registers of the housing. The data inputs (DO to D7) of the circuit (70) are connected to the lines (VBD0 to VBD07) of the internal bus of the card in a way, on the one hand, of being able to load the internal registers with the desired values and d On the other hand, being able to receive and transmit data to the input and output devices that are the keyboard and the mouse. The input (RDA) receives the input data from the keyboard and is connected to the differential amplifier (720) whose inputs are connected to the positive and negative connection terminals for data transmission from the keyboard. The input (RDB) of the circuit (70) receives the data coming from the mouse through a differential line receiver (710). The output (TDB) of the housing (70) is connected by a differential line receiver (711) and by a register (712) to the data reception input for the mouse. The output (TDB) transmits the data to be transmitted to the mouse. The inputs (DTRA / and DTRB /) of the circuit (70) are respectively connected to the outputs (Q4 and Q2) of the flip-flops of the circuit (29) of FIG. 2 delivering the signals (MPUINT /) and (MPUHLT /). The output (IT) indicating an interrupt request is sent to the input (INTRQ /) of the flip-flop (257) connected to the bus (VME) of FIG. 2.A. The output (RRDYB /) delivers the signal (MOUSIT) which after inversion by the inverter (74) is sent to the input (NS) of the scale (73). The input (SYNCB /) receives the signal (INTVME /) coming from the output (Q6) of the register (29) of figure 2.B. The interrupt acknowledgment input (IK) receives the signal (VCBIAC /) from the output of the same name of the circuit (23) of Figure 2.A. The output (DK) acknowledgment of data is connected to the circuit delivering the signal (MPUDTAC). This output (DK) delivers a signal which indicates to the processor (30) that the data is ready or that the interface circuit (70) has accepted the data. The clock clock input (CK) of the circuit (70) receives the signal (SIOCLK) from the output of the register (248) of figure 2.A, register whose output is looped back to the input via an inverter so as to constitute a frequency divider by 2. The output of this register (248) therefore delivers a signal (SIOCLK) with a frequency of 10 Mega Hertz since the clock of the register (CLOCK) has a frequency of 20 Mega Hertz. It emerges from the above description that the input-output interface (70) is connected to function as a serial-parallel interface with two separate channels, one for the keyboard and the other for the mouse, and generates interruptions to the bus. (VME). When the keyboard or mouse wants to send data. The differential line receiver (720) of the keyboard channel makes it possible to adapt the level of data transmitted to the level of the circuit (70). The circuit (70) is normally programmed to generate an interrupt by the output (IT) to the bus, upon receipt of a character. In response the signal (VCBIAC /) of acknowledgment of receipt of the interrupt from the bus (VME) is generated, which allows the circuit (70) to transmit an interrupt vector on the 8 weight bits weak data bus. If this interruption vector indicates that it is an interruption in the reception of a character, an interruption that could be called normal, the character received, which during this time there was stored in the internal register of the circuit (70), can then be read by the bus (VME). The channel (B) of the circuit (70) manages the inputs and outputs of the mouse, the circuit (70) is programmed so that, when receiving a character from the mouse, the output (RRDYB) is activated and generates through the flip-flop (73) a level 2 interrupt on the input (L1) of the processor (30). This interrupt, thereafter, will be processed by the processor.

An interrupt to the bus (VME) can be generated by the local processor (30) by activating the input (SYNCB /) of the circuit (70) via the signal (INTVME /) of the register (29) of Figure 2.B. (How?). The two bus interruptions (VME) to the local processor (30) through the signal (INTVME) and local processor (30) to bus (VME) by means of the signal (MPUDTAC) transformed in the circuit (23) into (VMEDTAC) and returned to the bus (VME) by the buffer (254) in the form of the signal (BDTACK), allow synchronization of the local processor (30) with the central processor (1).

The sound generator circuit (80) represented in FIG. 8 receives on its inputs (DO to D7) the lines (VBDO to VBDO7) of the internal data bus of the card. The circuit input (DO) is connected to the line (VBD07) while the input (D7) is connected to the line (VBD00) of the data bus. The input (WE) for writing the internal registers of the circuit (80) receives the signal (VCBWR /) from the buffer (253) of FIG. 2.A. The input (CE) for selecting the circuit (80) receives the signal (CSON /) delivered by the output (Q2) of the decoder (263) of FIG. 2.A. The clock input (CLK) of the circuit (80) receives the output of a NAND gate (81) one of the inputs of which receives the signal (ENASON /) delivered by the output (Q3) of the control register ( 29) and the other input receives the clock signal (SERCK) from the clock (H2) with a frequency of 2.45 Mega-Hertz which serves as a clock for the serial output input interface. The signal (ENASON /) allows the power-up not to validate the clock signal for the circuit (80) therefore, to prevent the generation of a fortuitous sound as soon as the system is started up.

The video interface circuit comprising the serializer (60) shown in FIG. 6 has a clock generator (H1) stabilized by a 90 Mega-Hertz quartz whose signal is sent to the input (DCLK) of the serializer ( 60). This frequency is divided by 16 by the circuit (63) to generate the video clock (VIDCLOK) of the video controller (40). This clock is the basis for the generation of horizontal and vertical synchronization and erase signals. The serializer (60) receives the 16 bits (VDOO: 8, VDO8: 8) on its data inputs (D0 to D15) in parallel to send them in series to the graphic screen at the clock frequency (H1) . Two flip-flops (D61, D62) generate the sequencing constituted by the loading of the circuit (60) and the data shifts for the video memory (45, 46). The flip-flop (62) delivers, through the amplifier (66), the signal (SHCLK) for shifting the data from the video memory. The flip-flop (61) delivers the signal (SHRGLD) to the input (LD /) of the circuit (60) to trigger the loading of the data supplied by the lines (VD) of the registers of the video memories into a buffer register of the circuit (60). The flip-flop (61) is validated by the output of the amplifier (64) which receives on its two inputs the signal (BLANK /) supplied by the corresponding output of the circuit (40) of the video controller and the signal (ENAVID /) of validation of the video supplied by the output (Q0) of the control register (29) of FIG. 2.A. The output of the circuit (64) is sent to the input for setting "1" (S1) of the flip-flop (61) so as to block this flip-flop to prevent the loading of the data supplied by the lines (VBD) of the memory video during the horizontal and vertical return of the spot. This therefore prevents the offset of the data supplied by the video memory and replaces this data by a logic value "1" which is loaded at the input (SIN), serial input of the circuit (60) so that when the data supplied on the bus (VBD) are not loaded, the circuit (60) continues to serialize values "1" at the frequency set by the clock (H1). This arrangement makes it possible to suppress the video signal during the horizontal and vertical return of the spot and has the advantage, taking into account the high frequency of serial shift of the data, to intervene on the loading signal which is at a frequency 16 times lower, which makes it possible to be sure that the erasure signal (BLANK) will be taken into account in time by the serializer because this signal is supplied by the circuit (40) which works with the clock (VIDCLOK ). The output (Q1) of the circuit (61) is also sent to the input (CE2 /) of the circuit (62) to invalidate the output (Q2) of the flip-flop (62). This output (62) provides the signal (SHCLK) which blocks the shift of the registers of the video memories (45, 46).

Thus, by the arrangement described in connection with FIGS. 2 to 8, we have succeeded in accommodating on a single card of the Europe format a set of functions which allow on the one hand to manage automatically the video display and on the other hand to take into account interrupts generated by a mouse in order to manage multi-windows using the processor (30) and the first and second memory groups (41, 42, 43, 44). The circuit (40) performs automatic addressing on the one hand to generate the video and on the other hand the address multiplexing for the dynamic memories (41, 42, 43, 44) by means of the signals (RAS0,1 , 2, CASLO, CASH1). The bit block transfer circuit (50) selected by the address line (23) makes it possible to transform a read-write write cycle of the microprocessor (30) into a read-modify-write cycle when one is on the page. address range from 9 to 16 Mega bits. The software for managing interruptions, controlling the video display and managing the multi-window will be stored in the memory groups (1 and 2). Memory groups 1 and 2 also allow the storage of hidden bitmaps. On this card everything has been done to obtain operation at the highest possible speed with the microprocessor (30) which is installed. This is achieved by the fact that the microprocessor (30) and the video system controller are synchronized by the same clock and by the fact that it there is a phase inversion between the signals from the bus (VME) and the bus (CPU) synchronized by the signal (SCLOCK /) and the signals from the video controller (40) are synchronized by the signal (SCLOCK). This saves a waiting time in operation. The total synchronism of the processor (30) with the controller (40) makes it possible to avoid a synchronization logic which is time consuming and at the same time occupies space on the card. Only the processor (30) of the card sees the information as it is displayed on the screen. The main processor (CPU) (1) will never see the screen as it is and will always go through the intermediate memories (41, 42, 43, 44). The keyboard as long as it is seen by interruption by the central processor (1) while the mouse can be alternately under the control of the microprocessor (30) or under the control of the central processor (1). In addition, we used the output (RRDYB /) of the circuit (70) which sends the direct memory access requests to generate an interrupt on the processor (30) following a mouse call on the input (RDB) . This allows the mouse to wake up the graphics processor (30) by interruption. The control register (29) plays the following role:
when the system is started, the register is set to "O" and the processor (30) is reset to "O" by this register via the output (MPRST /) and (MPUHLT /). The processor (30) is kept stopped by the output (MPUHLT /). At this time the central processor (1) can load the software necessary for the processor (30) into the memory (41 to 44) at the location where the latter must find it. After this loading operation, the processor (30) is released by deactivating the signals (MPURST / and MPUHLT /) and begins, as during a classic reinitialization, by going to address 0 for the pointer of the first instruction of the program. When we want to modify the software in use we send by the register (29) the active signal (MPUHLT /) so as to stop the software processor to be modified and then reactivate the operation of the processor (30). Thus this register (29) makes it possible to control from the main processor (1) the processor (30). The signal (ENAVIB) from the register (29) makes it possible to block the video interface, which is very useful during the entire initialization phase of the video controller (40), which is gradually initialized by the software as the 30 registers of this circuit are filled. During this period of time the video signal can be anything and to avoid that these signals do not deteriorate the very sharp video monitor we are led to block during this phase the video signal by the signal (ENAVID /). Likewise, the output (ENASON /) prevents the sound generator from emitting as soon as the power is turned on. Finally, this control register can be used to measure software performance. For example, it can be used to see the time taken by the central processor (1) to fill the memory of the card. In this case it is made to fill the memory without stopping and each time we reverse the output of the generator (200) which causes the sound signal to be emitted which can be analyzed in a conventional manner.

The operation of the arbitration and box selection logic will now be described with the aid of the figures (2C to 2E). FIG. 2C represents the arbitration of the bus, while FIG. 2D represents a read / write cycle by the central processor (1) and FIG. 2E represents the memory write / read cycle by the graphics processor (30). For the explanations we will use the table giving the organization of the address space of the card seen by the bus (VME) table appearing above on page of the text, and the table below giving the organization of the address space seen by the graphics processor (30) of the BITMAP card.

The interface card works practically only in slave mode, i.e. it only requests access to the external bus (VME), only in the event of an interruption caused by the keyboard or in the case of an interruption caused by the mouse, passed on by the processor (30) to the external bus (VME). The arbitration principle chosen requires that access via the external bus (VME) has priority. When an external bus access request (VME) is detected by the arbitration logic, it is transmitted to the graphics processor (30) and in the case where the processor (30) occupies the internal bus of the card, it ends its cycle in progress and frees the buses at the end of this cycle. At this time the buffers (20,21) are validated and the external bus (VME) has access to the internal bus of the card. When the access of the external bus (VME) is finished the buffers of the bus (VME) are put back in high impedance state by the signal (ENAVME) and the local processor (30) resumes its activity. To do this, the circuit (23) monitors the addresses (BA21 to BA23) of the bus (VME) and triggers the arbitration sequence when a hexadecimal address (6XXXXX) or (7XXXXXX) or an acknowledgment signal (IACK /) receive reception is generated on the bus. In the case of the appearance of the address signals on the bits (21 to 23) and the activation of the signal (BAS /), the circuit (23) generates the signal (MPUBRQ /) which, sent to the processor ( 30), signals to him on the input (BR) that another intelligent unit wishes to access the internal bus of the card. This is represented by arrow 1 in Figure 2.C. The processor (30) responds by validating the signal (MPUBGT /) which indicates to the requesting circuit that the request has been taken into account and that the microprocessor (30) will assign the buses at the end of the current bus cycles. The presence of the signal (BAS) and the signal (MPUBGT /) at the input of the circuit (23) makes it possible to deactivate the signal (VCBAS /) and activate the signal (BGA /) as indicated by the arrows 2 and 3, figure 2.C. Following the activation of the signal (BGA), the circuit (24) on the falling clock face following this activation, activates (arrow 4) the signal (BGACK /) which arrives on the pin (BK) of the circuit ( 30) confirms on behalf of the requesting circuit the taking of the buses and their control. The signal (BGACK /) makes it possible to generate, on the rising clock edge following its activation, the activation of the signal (ENAVME /) as represented by the arrow 5, FIG. 2C. As long as (BGACK /) is active, the processor (30) maintains its outputs at high impedance, which allows the external bus (VME) to access the internal bus of the card. The address validation signal (VSCALE /) for the video system controller (40) is generated on the falling edge of the clock after the activation of the signal (BGACK /) as represented by arrow 6. This ensures the stabilization of the addresses on the internal bus, of the signals (VSCFSO, 1) and (CSVSC /) and of the signal (VSCALE /). Following the activation of the signal (VSCALE /), the signal (MPUBRQ /) is deactivated as shown in arrow 7, then follows the deactivation of (BAS /, BGA /, BGACK /, ENAVME /, VCBAS / and VSCALE / ). In the event of an interruption caused by either the mouse or the keyboard, the external bus (VME) emits the signal (IACK /), which causes the same arbitration at the level of the signals (MPUBRQ, BGACK) and the validation of the signal (VCBIAC /) after the validation of the signal (MPUBGT /) to allow the circuit 70 to take possession of the internal bus and to transmit, during the signal validation (VCBWR /) following validation of the signal (ENAVME /), the data from the internal bus (VBD) to the external data bus (VME).

In the case of a read-write-memory cycle executed by the central processor 1, reference is made to FIG. 2D in which the arrows carrying the same figures correspond to the already described stages of the arbitration. The validation of the signal (ENAVME /) causes the activation of the signal (VCBAS /) as represented by the arrow 8 in the 2D figure from which follows the activation of the signal (VSCALE /) of validation of the addresses for the video controller. Activation of this signal causes the following falling clock edge to activate the signals (VCBCEL / and VCBCEH /). In fact, (VSCALE /) is returned to the circuit (23) which activates the signal (ENADS /) which will activate through the flip-flop (243) the signals (VCBCEL and VCBCEH). this step is represented by the arrow 9 in FIG. 2D. Data writing is performed when the signal is activated (RAMRAS /) and following this writing the circuit (40) activates the signal (MPUDTAC /). This signal causes successive activation of the signals (DTA1 / and DTA2 /) represented by arrows 10 and 12. The signal (DTA2 /) being activated on the falling edge following activation of the signal (ENDTA2 /) which is activated by the circuit (23) on the activation of the signal (DTA1 /). The activation of (DTA2 /) in the circuit (23) will cause the activation of the signal (VMEDTAC /) which is returned to the scale (425) which will cause the activation of the signal (BDTACK /). This step is represented by arrow 13 on the diagram in FIG. 2D. During activation of (BDTACK /), the data from the memory is read by the central processor (1). At the end of this reading, the signal (VCBAS /) is deactivated by the signal (BAS /) and this deactivation causes the deactivation of the signal (BDTACK /) as represented by the arrow 14. The invalidation of (VCBAS /) is synchronous invalidation of the signals (VCBDS0 / and VCBDS1 /) which cause the deactivation of the signals (VCBCEL / and VCBCEH /). This step deactivates the signal (VSCALE /) as shown in arrow 15 and the signal (RAMCAS0 /, 1 /) as shown in arrow 17. Inactivation of (VSCALE /) subsequently deactivates the signal (MPUDTAC /) (arrow 19) then deactivation of (DTA1 /) (arrow 20) and also deactivation of (RAMRAS /) (arrow 18). As can be seen in this 2D figure, the signal (MPUDTAC /) is activated without waiting cycle to allow the processor (30) to work at maximum speed, but as this signal arrives too early for the bus (VME) , since the data is not yet stabilized, this signal is delayed by the signals (DTA1 /, DTA2 /) to generate the acknowledgment signal (BDTACK /) for the bus (VME).

A read-write-memory cycle by the graphics processor (30) of the card will now be explained in connection with FIG. 2E. In this case, after the processor (30) has positioned the address lines (VCBADR), it generates by the output AS the signal (VCBAS /) which will generate as in step 6 of FIG. 2D the signal ( VSCALE /). The signal (VCBDS0 /, 1 /) is generated by the outputs (LS, US) of the circuit (30) according to the sequencing specific to a read-memory instruction of the microprocessor. The signal (VCBWR /) is made inactive by the output (WR) of the processor (30) and therefore indicates a reading. After validation of the address lines by the signal (VCBAS /) for the box (30) and (VSCALE /) for the box (40), the box (40) is selected by the signal (CSVSC /) and the access mode is indicated by the signals (VSCFS0 and VSCFS1) whose values are determined as we has already seen by the values of the address lines (VBAM17 to 20). Thereafter, the signal (ENADS /) is activated then the signals (RAMRAS / and RAMCAS0 /, 1 /) are activated as for figure 2D. The signal (MPUDTAC /) is activated by the circuit (40) before the data becomes available on the data bus (VBD). The activation of this signal (MPUDTAC /) introduces four waiting cycles which are linked to the operation of the video controller circuit (40). Once the signal (MPUDTAC /) is active, it activates the signal (DK /) (arrow 22) at the input of the circuit (30) which restarts the rest of the read-memory cycle for the processor. After reading the data, the processor 30 invalidates the signals (VCBAS / and VCBDS0 /, 1 /) and consequently the signals (ENADS / and RAMCAS0 /, 1 /). The DK signal is also disabled by VCBAS /. After the cycle S7 of FIG. 2E begins the cycle S0 of a write-memory by the processor 30. During this cycle, the signal (VCBWR /) is activated in the cycle S1 and its activation causes the deactivation of the signals (RAMRAS / and MPUDTAC /), as shown by the arrows 21. Thereafter, the signals (VCBAS /, VSCALE / etc) are activated in the same way as for a reading of data-memory. The only difference lies in the fact that the data lines of the bus (VBD) are positioned at their value at the end of the cycle S2 of the processor (30). In the data cycle, we see at the bottom of Figure 2E the line (LDSRC /) which corresponds to the load signal from the source register of the bit block transfer circuit (50). We see in the case of the use of this circuit that the loading of the source register takes place after the activation of the signal (MPUDTAC /) as represented by the arrow 23 in the figure. This allows you to come and read given by the circuit (50) before the end of a write cycle of the processor as we have already seen. The signal (LDSRC) is deactivated by UCBAS /.

The operation thus described made it possible to highlight the advantages of the invention. It is obvious that any modification within the reach of the skilled person is also part of the spirit of the invention.

Claims (12)

1. Graphics card and interface between a central processor (1) communicating asynchronously with this card by an external bus and a video monitor (9) characterized in that it comprises:
- a set of video memories (45, 46) of capacity at least equal to the number of display points desired on the monitor (9),
- at least one group of random access memories (43, 44 or 41, 42) for storing graphics application software,
- a circuit (40) controller of the video system, managing the addresses of the different memories in order to refresh the memories, the video display and the updates of the data or programs and delivering the video signals;
- a circuit (60) for serializing the data delivered by the video memory (45, 46) in cadence with a video clock H1;
- a graphics processor (30) clocked by a clock (H0) and working in synchronism with the circuit (40) of the video system controller so as to execute the software programs contained in the random access memory group;
- an interface circuit (20 to 22) between the external bus and the card buses and an arbitration circuit (23 to 27) between the graphics processor (30), the video system controller (40) and the external bus; 2. Interface card according to claim 1, characterized in that it further comprises an input-output interface circuit (70) between a mouse (71), a keyboard (72) and the processor or graphics (30) or the external bus, this circuit being clocked by a third clock (H2). 3. Interface card according to claim 2, characterized in that the circuit (70) of the controller of the video system generates interruptions due to an action on the keyboard directly on the external bus and interruptions due to an action on the mouse towards the graphics processor (30) via logic (73); 4. Interface card according to one of claims 1 to 3, characterized in that it comprises a sound generator (80). 5. Interface card according to one of the preceding claims, characterized in that it comprises a bit block transfer circuit (50) controlled by a logic (51) and selected by the most significant address line (A23). 6. Interface card according to one of the preceding claims, characterized in that it comprises a control register (29) making it possible, during the initialization of the system, to load the memories of the card and to load the various registers of the different circuits (50, 30, 40, 70). 7. Interface card according to one of the preceding claims, characterized in that the processor data lines (30) are isolated from the data lines of the internal data bus (VBD) of the card by a buffer circuit (31) of which the isolation is controlled by the most significant address line of the processor (A23). 8. Interface card according to claim 7, characterized in that the bit block transfer circuit (50) is controlled by a sequencing control logic (51) for transforming a read-write-memory instruction from the processor. graph (30) into a read-modify-write instruction for the circuit (50). 9. Card according to claim 8, characterized in that a logic circuit (47 to 49) for selecting memories and blocking exchanges between the graphics processor (30) and memories (41-42, 43-44, 45- 46) allows the modification of the read-write cycle to a read-modification-write cycle by the bit block transfer circuit (50). 10. Interface card according to one of the preceding claims, characterized in that the processor (30) works in slave mode for the allocation of the internal buses (VBD, VBA) relative to the external bus and to the central processor (1) and in auto-vector mode for handling interrupts without decoding priority levels. 11. Interface card according to claim 10, characterized in that the graphics processor (30) receives three types of interruption, the input channel interruptions for the mouse (71), from the input interface output (70), the interrupts of the video system controller circuit (40) and the interruptions triggered by the external bus and transmitted by the control register (29). 12. Interface card according to a preceding claim, characterized in that the circuit (60) for serializing the data for the video display comprises a loading input (LD) for the data to be serialized from the registers of the video memory (45 -46), enabling the loading to be disabled by the erasure signal (BLANK) coming from the circuit (40) of the video system controller.

Images