EP0266429A1 - Display system of plasma display - Google Patents

Display system of plasma display Download PDF

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Publication number
EP0266429A1
EP0266429A1 EP87902718A EP87902718A EP0266429A1 EP 0266429 A1 EP0266429 A1 EP 0266429A1 EP 87902718 A EP87902718 A EP 87902718A EP 87902718 A EP87902718 A EP 87902718A EP 0266429 A1 EP0266429 A1 EP 0266429A1
Authority
EP
European Patent Office
Prior art keywords
data
plasma display
shift register
ram
display system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP87902718A
Other languages
German (de)
French (fr)
Other versions
EP0266429A4 (en
Inventor
Seiichi Hattori
Kunio Kanda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Publication of EP0266429A1 publication Critical patent/EP0266429A1/en
Publication of EP0266429A4 publication Critical patent/EP0266429A4/en
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes

Definitions

  • the present invention relates to a display system for a plasma display unit for use in a numerical control apparatus or the like, and more particularly to a display system for plasma display unit in which the transfer of display data and the plasma display are independently effected.
  • Plasma display units are widely used in the art since they are thinner than CRT display units.
  • the plasma display units are particularly advantageous in that the outer shape is thin, the cabinet is small, and the weight of the overall unit is small.
  • the conventional circuit includes a CPU 20, a ROM 21 for storing, a control program, a work RAM 22, a video RAM 23 for storing video information, a display control circuit 24 for reading video information from the video RAM 23 and writing the video information in a plasma display unit 25.
  • the display control circuit 24 reads video information from the video RAM 23 at constant periods and writes the video information in the plasma display unit 25 in repeated cycles.
  • the video R A M 23 is always accessed by the display control circuit 24.
  • the CPU 20 and the display control circuit 24 should be synchronized with each other so that they will not access the video RAM 23 at the same time.
  • the circuit arrangement for achieving this is howver complex.
  • a display system for a plasma display unit for displaying characters and graphics comprising means for transferring data from a-RAM which stored data to be displayed and for generating a transfer completion signal when the data transfer is completed, a shift register for serially receiving the trnsferred data, and a timing generator circuit for generating write timing pulses at constant periods and for writing the data from said shift register in the plasma display unit in response to a timing pulse following said transfer completion signal.
  • plasma display unit itself has a storage capability, it is not necessary to always write display data, but new data stored in RAMs can be displayed at all times by writing the data at a timing following the transfer of the display data.
  • FIG. 1 shows in block form a display system according to an embodiment of the present invention.
  • the display system includes a CPU 1, a ROM 2 for storing a control program, a character RAM 3 for storing character information, a character generator 4 for converting character information to display data, a graphic RAM 5 for storing graphic information, and a combining circuit 6 for combining character data and graphic data.
  • the display system also includes a plasma display unit 10 for displaying data with drive signals in X- and Y-axis directions, a shift register 11 for serially receiving display data and, at the same time, for synchronously determining data positions in the X-axis direction in the plasma display unit, and a driver 12 for receiving the display data from the shift register 11 and for driving the plasma display unit 10.
  • the display system has an address generator 13 for the Y-axis direction in the plasma display unit 10, the address generator 13 being arranged to receive address signals in the Y-axis direction at the same time that the display data is transferred to the shift register 11, and a driver 14 responsive to a signal from the address generator 13 for driving a corresponding Y-axis line in the plasma display unit 10.
  • a timing generator circuit 15 generates timing pulses at constant periods. When the timing generator circuit 15 receives an input signal W.END, it issues a signal BUSY to a bus line, issues a next timing pulse as a write signal HSYNC for the plasma display unit 10, and thereafter drops the signal BUSY.
  • FIG. 2 shows a timing chart of operation of the display system.
  • a signal HT are composed of timing pulses which are automatically generated at constant periods in the timing generator circuit 15.
  • a signal HSYNC is a timing signal for writing display data from the shift register 1 in the plasma display unit 10.
  • a signal DATA is a signal indicating that the CPU 1 reads a display data signal from the combining circuit 6 and writes the display data signal in the shift register 11.
  • the signal DATA includes a portion R representative of the reading of the display data signal and a portion W representative of the writing (serial input) of the data signal in the shift register 11.
  • a signal W.END is a signal for informing the timing generator circuit 15 of the completion of the writing of the data after the CPU 1 has written the display data in the shift register 11.
  • a signal BUSY is a signal indicating that a next data transfer signal cannot be received until the timing generator circuit 15 generates a write signal in response to the data transfer completion signal W.END.
  • the CPU 1 reads display data at a time t l and transfers the display data to the shift register 11 at a time t 2 .
  • the data transfer is completed, whereupon the transfer completion signal W.END is delivered to the timing generator circuit 15.
  • the timing generator circuit 15 From a time t 4 until a next write signal HSYNC is produced, the timing generator circuit 15 generates a signal BUSY indicating that next data cannot be accepted even if it is transferred in the meantime.
  • a next timing pulse HT is written and issued as a signal H SYNC to enable the driver 12 to display the display data from the shift register 11 on the plasma display unit 10.
  • the signal BUSY is turned off at a time t s , thus waiting for next display data to be transferred.
  • the display data is transferred at one time to all bits of the shift register 11. However, the display data may be transferred to a few bits at a time.
  • the transfer and display of display data are separately perormed, utilizing the storage capability of the plasma display unit. Since the CPU can transfer display data irrespective of the display operation of the plasma display unit, the arrangement of hardware is simplified, the processing speed of the CPU is increased, and compatibility can be established between the CPU and the plasma display unit.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

A plasma display system which displays characters and graphics. Data are transferred from RAM's (3, 5) that store data to be displayed to a shift register (11) via a character generator (4) and a synthesizing circuit (6). When the transfer of data is finished, a transferfinish signal (W. END) is given to a timing generating circuit (15) which is so constructed as to generate a write timing pulse to the plasma display upon receipt of the transfer finish signal (W. END) and to write the data of the shift register (11) onto the plasma display. Since the display device itself has a storage function, the data to be displayed need not be written ont the plasma display (10) at all times. If the data is written at a timing next to the timing when the data is to be displayed is transferred to the shift register (11), the new data stored in the RAM's (3, 6) can be displayed.

Description

    Technical Field
  • The present invention relates to a display system for a plasma display unit for use in a numerical control apparatus or the like, and more particularly to a display system for plasma display unit in which the transfer of display data and the plasma display are independently effected.
    • Background Art
  • Plasma display units are widely used in the art since they are thinner than CRT display units. The plasma display units are particularly advantageous in that the outer shape is thin, the cabinet is small, and the weight of the overall unit is small.
  • One conventional circuit shown in FIG. 3 of the accompanying drawings has been used as a display system for a plasma display unit. The conventional circuit includes a CPU 20, a ROM 21 for storing, a control program, a work RAM 22, a video RAM 23 for storing video information, a display control circuit 24 for reading video information from the video RAM 23 and writing the video information in a plasma display unit 25.
  • The display control circuit 24 reads video information from the video RAM 23 at constant periods and writes the video information in the plasma display unit 25 in repeated cycles.
  • Therefore, the video RA M 23 is always accessed by the display control circuit 24. In order for the CPU 20 to access the video RAM 23, the CPU 20 and the display control circuit 24 should be synchronized with each other so that they will not access the video RAM 23 at the same time. The circuit arrangement for achieving this is howver complex.
    • Disclosure of the Invention
  • It is an object of the present invention to provide a display system for a plasma display unit, which will solve the aforesaid problem and is of a simple circuit arrangement utilizing the storage capability of the plasma display unit.
  • In order to eliminate the above conventional problem, there is provided in accordance with the present invention a display system for a plasma display unit for displaying characters and graphics, the display system comprising means for transferring data from a-RAM which stored data to be displayed and for generating a transfer completion signal when the data transfer is completed, a shift register for serially receiving the trnsferred data, and a timing generator circuit for generating write timing pulses at constant periods and for writing the data from said shift register in the plasma display unit in response to a timing pulse following said transfer completion signal.
  • According to the present invention, since plasma display unit itself has a storage capability, it is not necessary to always write display data, but new data stored in RAMs can be displayed at all times by writing the data at a timing following the transfer of the display data.
    • Brief Description of the Drawings
    • FIG. 1 is a block diagram of an embodiment of the present invention;
    • FIG. 2 is a timing chart of operation of the embodiment of the present invention; and
    • FIG. 3 is a block diagram of a conventional display system for a plasma display unit.
    Best Mode for Carrying Out the Invention
  • An embodiment of the present invention will hereinafter be described in specific detail with reference to the drawings.
  • FIG. 1 shows in block form a display system according to an embodiment of the present invention. The display system includes a CPU 1, a ROM 2 for storing a control program, a character RAM 3 for storing character information, a character generator 4 for converting character information to display data, a graphic RAM 5 for storing graphic information, and a combining circuit 6 for combining character data and graphic data.
  • The display system also includes a plasma display unit 10 for displaying data with drive signals in X- and Y-axis directions, a shift register 11 for serially receiving display data and, at the same time, for synchronously determining data positions in the X-axis direction in the plasma display unit, and a driver 12 for receiving the display data from the shift register 11 and for driving the plasma display unit 10. Moreover, the display system has an address generator 13 for the Y-axis direction in the plasma display unit 10, the address generator 13 being arranged to receive address signals in the Y-axis direction at the same time that the display data is transferred to the shift register 11, and a driver 14 responsive to a signal from the address generator 13 for driving a corresponding Y-axis line in the plasma display unit 10. A timing generator circuit 15 generates timing pulses at constant periods. When the timing generator circuit 15 receives an input signal W.END, it issues a signal BUSY to a bus line, issues a next timing pulse as a write signal HSYNC for the plasma display unit 10, and thereafter drops the signal BUSY.
  • Operation of the display system will be described below. FIG. 2 shows a timing chart of operation of the display system. In FIG. 2, a signal HT are composed of timing pulses which are automatically generated at constant periods in the timing generator circuit 15. A signal HSYNC is a timing signal for writing display data from the shift register 1 in the plasma display unit 10. A signal DATA is a signal indicating that the CPU 1 reads a display data signal from the combining circuit 6 and writes the display data signal in the shift register 11. The signal DATA includes a portion R representative of the reading of the display data signal and a portion W representative of the writing (serial input) of the data signal in the shift register 11. A signal W.END is a signal for informing the timing generator circuit 15 of the completion of the writing of the data after the CPU 1 has written the display data in the shift register 11. A signal BUSY is a signal indicating that a next data transfer signal cannot be received until the timing generator circuit 15 generates a write signal in response to the data transfer completion signal W.END.
  • The CPU 1 reads display data at a time tl and transfers the display data to the shift register 11 at a time t2. At a time t3, the data transfer is completed, whereupon the transfer completion signal W.END is delivered to the timing generator circuit 15. From a time t4 until a next write signal HSYNC is produced, the timing generator circuit 15 generates a signal BUSY indicating that next data cannot be accepted even if it is transferred in the meantime. At a time t5, a next timing pulse HT is written and issued as a signal HSYNC to enable the driver 12 to display the display data from the shift register 11 on the plasma display unit 10. The signal BUSY is turned off at a time ts, thus waiting for next display data to be transferred.
  • While in the above embodiment character information and graphic information are combined and displayed, only one of such two forms of information can be displayed. The display data is transferred at one time to all bits of the shift register 11. However, the display data may be transferred to a few bits at a time.
  • With the present invention, as described above, the transfer and display of display data are separately perormed, utilizing the storage capability of the plasma display unit. Since the CPU can transfer display data irrespective of the display operation of the plasma display unit, the arrangement of hardware is simplified, the processing speed of the CPU is increased, and compatibility can be established between the CPU and the plasma display unit.

Claims (5)

1. A display system for a plasma display unit for displaying characters and graphics, said display system comprising:
means for transferring data from a RAM which stored data to be displayed and for generating a transfer completion signal when the data transfer is completed;
a shift register for serially receiving the trnsferred data; and
a timing generator circuit for generating write timing pulses at constant periods and for writing the data from said shift register in the plasma display unit in response to a timing pulse following said transfer completion signal.
2. A display system according to claim 1, wherein said RAM comprises a RAM for storing characters and a RAM for storing graphics.
3. A display system according to claim 2, further including a combining circuit for combining outputs from said RAM for storing characters and said RAM for storing graphics.
4. A display system according to claim 1, wherein the data is transferred, all bits at a time, to said shift register.
5. A display system according to claim 1, wherein the data is transferred, partial bits at a time, to said shift register.
EP19870902718 1986-04-24 1987-04-10 Display system of plasma display. Withdrawn EP0266429A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP95403/86 1986-04-24
JP61095403A JPS62251792A (en) 1986-04-24 1986-04-24 Display system for plasma display

Publications (2)

Publication Number Publication Date
EP0266429A1 true EP0266429A1 (en) 1988-05-11
EP0266429A4 EP0266429A4 (en) 1989-04-12

Family

ID=14136701

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19870902718 Withdrawn EP0266429A4 (en) 1986-04-24 1987-04-10 Display system of plasma display.

Country Status (3)

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EP (1) EP0266429A4 (en)
JP (1) JPS62251792A (en)
WO (1) WO1987006755A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4266225A (en) * 1978-12-05 1981-05-05 Burnett Bradley W Display panel interface circuit
EP0108516A2 (en) * 1982-10-09 1984-05-16 Sharp Kabushiki Kaisha Data selection circuit for the screen display of data from a personal computer
EP0121070A2 (en) * 1983-03-07 1984-10-10 International Business Machines Corporation Plasma display management systems
EP0162605A1 (en) * 1984-04-25 1985-11-27 Sony Corporation Sequential selection circuits

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS557596B2 (en) * 1973-11-15 1980-02-26
JPS5260031A (en) * 1975-11-12 1977-05-18 Fujitsu Ltd Graphic display system
JPS54162930A (en) * 1978-06-14 1979-12-25 Fujitsu Ltd Display system for low-speed display unit
JPS572089A (en) * 1980-06-06 1982-01-07 Nippon Electric Co Plasma display information transfer control ststem
US4445501A (en) * 1981-05-07 1984-05-01 Mccormick Laboratories, Inc. Circuits for determining very accurately the position of a device inside biological tissue
JPS58105191A (en) * 1981-12-17 1983-06-22 富士通株式会社 Driving of ac type plasma display panel
JPS6088666U (en) * 1983-11-19 1985-06-18 三洋電機株式会社 display device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4266225A (en) * 1978-12-05 1981-05-05 Burnett Bradley W Display panel interface circuit
EP0108516A2 (en) * 1982-10-09 1984-05-16 Sharp Kabushiki Kaisha Data selection circuit for the screen display of data from a personal computer
EP0121070A2 (en) * 1983-03-07 1984-10-10 International Business Machines Corporation Plasma display management systems
EP0162605A1 (en) * 1984-04-25 1985-11-27 Sony Corporation Sequential selection circuits

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO8706755A1 *

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Publication number Publication date
WO1987006755A1 (en) 1987-11-05
JPS62251792A (en) 1987-11-02
EP0266429A4 (en) 1989-04-12

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Inventor name: HATTORI, SEIICHI

Inventor name: KANDA, KUNIO