EP0278194A1 - Electroluminescent display device with memory effect controlled by multiple dephased sustain voltages - Google Patents

Abstract

According to the invention, the display device comprises at least one layer having an electrooptical property with memory effect, flanked by a first (12) and a second family (18) of electrodes. The display device further comprises a generator able to generate several dephased voltages. At least one of the families (12) of electrodes is subdivided into at least two sub-families of parallel electrodes receiving respectively sustaining voltages which are phase-shifted relative to one another. This results in a noticeable reduction in electrical consumption, an improvement in manufacturing efficiency, the possibility of producing display devices of larger size and the increasing of the speed of writing an image, etc. <IMAGE>

Description

The invention finds an application in opto-electronics in the production of electroluminescent displays with memory effect.

The invention is applicable to any type of electroluminescent display with memory effect. An electroluminescent display is said to have a memory effect when the electro-optical property of the display has a hysteresis loop comprising two stable operating states. In Figure 1a, there is shown schematically the hysteresis loop of the electro-optical property of an electroluminescent display with memory effect. On the ordinate axis is shown the luminance L of the display and on the abscissa axis is represented the electric voltage V applied to the display. The brightest state L _a is said to be on, the other L _e is said to be off. To switch the display from the off state to the on state, the voltage applied to the display is temporarily increased to a value S _a located beyond the hysteresis loop. Conversely, the display is turned off simply by temporarily decreasing the applied voltage. A voltage V _e , called maintenance, is permanently applied to the entire display in order to maintain all the pixels in their state.

Currently, there are two types of electroluminescent displays with memory effect: the inherent memory effect display, obtained when the display comprises an electroluminescent layer based for example on zinc sulfide activated by manganese, sandwiched between two dielectric layers, and the extrinsic memory effect display, obtained when the display comprises an electroluminescent layer and a photoconductive layer superimposed.

FIG. 1b shows, by way of example, a photoconductive electroluminescent display. The experimental data described below come from such a type of display. But the inherent memory effect display behaves similarly.

A photoconductive electroluminescent display comprises a transparent substrate 10, a first set of parallel transparent electrodes or line electrodes 12 (the perspective section shown is assumed to be made along one of these lines), an electroluminescent layer 14, a photoconductive layer 16 and a second set of parallel transparent electrodes or column electrodes 18, perpendicular to the line electrodes 12.

The row and column electrodes are supplied from an alternating voltage generator 20. More specifically, the row electrodes 12 are connected to this generator 20 via a line addressing circuit 22 _ℓ and the column electrodes 18 by a column addressing circuit 22 _c . The observation is preferably carried out through the substrate 10, at 23.

The display screen is made up of pixels, each of which is defined by the overlap area of a particular row electrode and a particular column electrode.

The actual display is, for example of the PC-EL type, that is to say made up of two layers 14 and 16, one troluminescent (EL) and the other photoconductive (PC). It is understood that, when the electroluminescent layer is excited, the light it emits increases the conductivity of the photoconductive layer, and consequently the conductivity of the PC-EL display itself at the level of the pixel considered. Thus, once a pixel has been excited, it suffices to apply a maintenance voltage to it to maintain its luminescence, and consequently the display of this pixel.

First of all, the addressing circuits 22 _ℓ and 22 _c permanently apply to all the pixels of the screen an alternating voltage V _e called the maintenance voltage, and drawn from the generator 20. More precisely, the circuit row addressing 22 _ℓ applies a potential U _ℓ to the row electrodes while the addressing circuit 22 _c applies a potential U _c to the column electrodes. The voltage across the pixel is then U _ℓ -U _c = V _e . Thereafter, we will take U _c as potential reference or "mass", therefore U _c = 0.

The structure of the displayed image is defined and / or modified by the addressing function itself.

A conventional addressing method consists in sequentially scanning the line electrodes of the memory display. Instead of the potential U _ℓ , the selected line electrode is subjected to a potential U _ℓa , greater than U _ℓ .

At the same time, the addressing circuit 22 _c applies a potential U _ca less than U _c than those of the column electrodes which cross the excited line electrode at the level of the pixels to be lit. One makes so that U _ℓa -U _ca is higher than a threshold S _a , allowing the lighting of an extinct pixel, that is to say at the level of which the photoconductive layer is not very conductive. Thereafter, the alternating maintenance voltage V _e is sufficient to maintain the ignition of the pixels thus excited.

Conversely, to turn off a pixel, just apply at the selected row electrode a potential U _ℓe less than U _ℓ , and / or at the corresponding column electrode a potential U _ce greater than U _c , and this for a short time. The total voltage applied to the pixels then drops for a short time below a second threshold S _e (less than S _a ), which has the effect of turning off the pixel. The maintenance voltage then has no effect on the pixel, taking into account the increased resistance of the photoconductive layer, following the extinction of the pixel.

Since the voltages considered are alternative, the threshold conditions to be satisfied are of course appreciated at the level of their peak values.

Memory effect electroluminescent displays have much longer switch-off times, much more than 1 millisecond, than switch-on times, less than 100 microseconds. The optimal pixel extinction method is therefore different from the ignition method described above. For example, it is more judicious to proceed to the simultaneous and total extinction of several lines by acting directly on the maintenance voltage before writing any message. To simplify the description, however, we will limit ourselves to that of a sequential extinction method even if the invention is applicable to both methods.

The various values of the voltage which must be applied to the pixels are associated with currents, the peak value of which is an essential factor with regard to the performance of the memory display and its price. Indeed, the voltage drop along the electrodes, coming from their resistance, must not exceed certain limits, and the size of the screen is therefore limited. On the other hand, the cost of electronic addressing circuits largely results from the value of the current that they must be able to modulate.

The alternating maintenance voltage V _e produces a current maintenance through the memory display. This maintenance current is broken down into a displacement current I _d independent of the pixel ignition rate, and into a conduction current I _c which, on the contrary, is proportional to the number of pixels lit. These two currents pass through the addressing circuits 22. The maximum value of the total current I _t (t) = I _c (t) + I _d (t) is obtained when all the pixels are lit.

FIG. 2 is a timing diagram illustrating, for a pixel, on the one hand the alternating maintenance voltage V _e , on the other hand the corresponding total maintenance current I _t , the pixel being assumed to be on.

A maintenance cycle corresponds to a period of the alternating voltage V _e , that is to say for example to the time interval between the instants 0 and T₂. T₂ is for example of the order of 1 millisecond.

In a maintenance cycle, the alternating voltage V _e reaches its peak value twice, once in negative and once in positive. In theory, we could therefore address two lines sequentially during a period of the maintenance voltage. For an addressing rate of 1 kHz, we can then consider a writing speed of 2000 lines per second. However, for practical reasons, some of the current addressing integrated circuits can only switch unipolar voltages. One can only use one of the peaks of the alternating voltage Ve during a period of the latter. The maximum writing speed is therefore only 1000 lines per second.

It should now be taken into account that the row electrodes are generally made of aluminum, the column electrodes made of tin and indium oxide. The line electrodes can also be made of tin and indium oxide if it is desired to produce a completely transparent display. However, the resistance of the transparent electrodes 12, made of oxide of tin and indium, is not negligible. If, on the other hand, reference is made to FIG. 2, it can be seen that during the maintenance of all the pixels defined by the zone of overlap of the column electrodes by a line electrode, the peak value of the total current I _t se is roughly in phase with the maintenance voltage V _e if all the pixels are lit. Consequently, a voltage drop occurs on the column electrode 18 concerned, the value of which is maximum when the maintenance voltage V _e reaches its maximum value.

We will now examine what happens when the extreme potentials U _ℓa and U _{ca are applied} to the boundaries of the pixel (s) that we want to excite. To the excess potentials U _ℓa -U _ℓ on the one hand (for the line), U _c -U _ca on the other hand (for the column), there corresponds a switching current I _co . We now limit ourselves to the study of the currents flowing, during the switching of the pixels, in the column electrodes, which it is recalled that they are more resistive because of their constitution as tin and indium oxide.

The potential U _c of the column electrodes of the pixels which one does not wish to light up is taken as the reference potential, it is for example equal to 0. On the other hand, the column electrodes of the pixels which one wishes to light up are brought at the negative potential U _ca in a time T _c . We denote by C the capacity per unit area of an extinct pixel. The switching current I _co of a column electrode therefore has the value defined by formula (I) (which can be found in an appendix to this description, with the other formulas). This current I _{co is} added to the maintenance current I _c (t) + I _d (t) defined above. It would therefore be desirable to offset the moment of switching of the column electrodes and the row electrodes, with respect to the peaks of the maintenance voltage V _e , in order to minimize the peak value of the overall current flowing in the display at memory, and therefore reduce the maximum current level specified for these circuits. This will also limit the voltage drop induced by this global current, from one end to the other of the resistive electrodes tives, in particular column electrodes 18.

In FIG. 2, it appears that it is not possible to avoid the overlap of the maintenance current with the switching current I _co : indeed, there is no interval in which the switching of the pixels can take place. occur when the maintenance current is zero. The voltage drop from one end of the column electrodes to the other is therefore increased by switching in the same proportion as the peak value of the overall current.

The calculation of the relative voltage drop from one end to the other of a resistive electrode is relatively easy in the case of a sinusoidal maintenance voltage. This voltage drop is expressed in the attached formula II, in which R is the surface resistance in ohms / square, L the length of the electrodes in centimeters, ω the angular pulsation of the maintenance voltage, C the surface capacity of a pixel off in nanofarads per square centimeter, and finally, k is the multiplier of this capacity when the pixel is on.

If it is now accepted that this relative voltage drop must remain below a maximum A, the maximum height L _M that the display screen can have is given by the attached formula III. It follows, first of all, that the constraints linked to the maintenance and / or the switching of the pixels limit the size of the display screen.

Furthermore, the voltage drop which exists from one end to the other of the resistive electrodes (in particular electrodes 18 of tin and indium oxide) has the disadvantage of producing a heterogeneity of the ignition characteristics and extinction of the pixels, at different points on the surface of the memory display. This heterogeneity can go so far as to cause stray ignitions or, on the contrary, ignition faults on the matrix screen.

The present invention provides a solution to this problem.

An object of the invention is to reduce, in a memory display, the peak value of the currents flowing in the column addressing circuits and in the column or row and column electrodes.

The invention also aims to increase the speed of writing an image.

It applies to an electroluminescent display with memory effect of any type (PC-EL, inherent, etc.). The memory structure is surrounded by a first and a second family of electrodes orthogonal to each other. A display point or pixel is defined by the crossing zone of a particular electrode of one family and a particular electrode of the other family. The display also includes a generator capable of producing an alternating maintenance voltage for the electrodes, as well as addressing means for selectively applying voltage variations relative to the maintenance voltage to electrodes of the two families, in order to to allow the addressing of one or more particular pixels.

According to a general characteristic of the invention, the generator is able to produce several alternating phase-shifted maintenance voltages of the same frequency, and at least one of the two families of electrodes is subdivided into at least two sub-families of electrodes each receiving one of these phase-shifted maintenance voltages.

Reducing the peak value and the average value of the currents flowing in the column addressing circuit and in the column electrodes offers several advantages. First of all, the energy consumption of the display is reduced. Then, reducing the current flowing through the addressing circuits makes it possible to resort to circuits and more common and less expensive connectors, which results in a significant reduction in manufacturing costs of the complete display.

Another substantial advantage resides in the increase in the maximum possible length for the resistive electrodes (in particular the resistive electrodes 18 in tin and indium oxide), and consequently the maximum height of the display screen.

Finally, reducing the current also makes it possible to increase the speed of writing an image by increasing the frequency of the maintenance voltage V _e .

According to a particular embodiment of the invention, the layer has an electro-optical property with a memory effect resulting from the superposition of a photoconductive layer and an electroluminescent layer. The latter can be produced so as to emit any color, the photoconductive layer having the suitable composition.

According to yet another particular embodiment of the invention, the material of the layer having an electro-optical property with a memory effect is for example zinc sulphide activated by manganese or any other material having an inherent memory effect.

According to a particular embodiment, two maintenance voltages are in phase opposition with respect to each other, and each applied to one of the two sub-families of electrodes.

According to another particular embodiment, four maintenance voltages are in phase quadrature with respect to each other, and each applied to one of the four sub-families of electrodes.

Another interesting variant of the invention consists in use three maintenance voltages phase shifted by 120 electrical degrees with respect to each other, and three sockets of electrodes.

Whatever the number of sub-families of electrodes and therefore of different phase-shifted voltages, the electrodes which belong to them are connected so that those which follow one another on the screen belong respectively to each of the sub-families and this in the same order for the whole screen or in a variable order (nested networks).

According to another aspect of the invention, the production of the various alternating voltages required by the voltage generator is ensured using a transformer.

Preferably, the family of column electrodes is made of tin and indium oxide and the family of row electrodes is made of aluminum.

Advantageously for the production of a completely transparent display, the families of row and column electrodes are made of tin and indium oxide.

In the case of a completely transparent display, the other of the two families of electrodes is divided into at least two sub-families of parallel electrodes receiving respectively as many phase-shifted maintenance voltages.

Advantageously, the voltage variations relative to the maintenance voltage intended to modify the displayed image are placed in the time intervals between the peaks of the maintenance current flowing in the electrodes of the sub-family considered.

According to a preferred embodiment of the invention, the means allowing the addressing of the pixels comprise unipolar or bipolar addressing circuits of the push-pull type.

• - la figure 1a, déjà mentionnée, représente schématiquement la boucle d'hystérésis de la propriété électro-optique d'un afficheur de type connu;
• - la figure 1b, déjà mentionnée, est une vue en coupe perspec­tive d'un afficheur PC-EL de type connu;
• - la figure 2, déjà mentionnée, est un chronogramme relatif à une méthode d'adressage matriciel connue de l'afficheur de la figure 1;
• - la figure 3 est le schéma équivalent d'un exemple de circuit d'adressage ligne participant à l'adressage des pixels de l'afficheur à mémoire, objet de l'invention;
• - la figure 4 est le schéma de principe d'un générateur de tension couplé à un transformateur pour produire deux tensions de commande en opposition de phase;
• - la figure 5 est une illustration schématique d'un premier mode de réalisation de l'invention, faisant usage du généra­teur de la figure 4;
• - la figure 6 illustre le schéma équivalent d'un afficheur à mémoire selon l'invention;
• - la figure 7 est un chronogramme illustrant la commande des pixels, dans le cas où les tensions appliquées aux deux sous-familles d'électrodes lignes sont en opposition de phase;
• - la figure 8 est un chronogramme relatif à une variante de l'invention, où les tensions appliquées aux électrodes lignes sont en quadrature de phase; et
• - la figure 9 est un chronogramme illustrant une autre varian­te de l'invention, dans le cas où les tensions appliquées à trois sous-familles d'électrodes lignes sont déphasées de 120 degrés électriques les unes par rapport aux autres.

Other characteristics and advantages of the invention will appear on examining the detailed description below, and the appended drawings, in which:

• - Figure 1a, already mentioned, schematically shows the hysteresis loop of the electro-optical property of a display of known type;
• - Figure 1b, already mentioned, is a perspective sectional view of a PC-EL display of known type;
• - Figure 2, already mentioned, is a timing diagram relating to a matrix addressing method known from the display of Figure 1;
• - Figure 3 is the equivalent diagram of an example of a line addressing circuit participating in the addressing of the pixels of the memory display, object of the invention;
• - Figure 4 is the block diagram of a voltage generator coupled to a transformer to produce two control voltages in phase opposition;
• - Figure 5 is a schematic illustration of a first embodiment of the invention, making use of the generator of Figure 4;
• - Figure 6 illustrates the equivalent diagram of a memory display according to the invention;
• - Figure 7 is a timing diagram illustrating the control of the pixels, in the case where the voltages applied to the two sub-families of line electrodes are in phase opposition;
• - Figure 8 is a timing diagram relating to a variant of the invention, where the voltages applied to the line electrodes are in phase quadrature; and
• - Figure 9 is a timing diagram illustrating another variant of the invention, in the case where the voltages applied to three sub-families of line electrodes are phase shifted by 120 electrical degrees with respect to each other.

The appended drawings contain information of a certain nature in several respects. Furthermore, the geometry is involved in substance in the device according to the invention. Consequently, the appended drawings could not only serve to make the present description better understood, but also contribute to the definition of the invention, as much as necessary.

Referring to Figure 3, there is shown the equivalent diagram of an example of an addressing circuit participating in the addressing of the pixels of the memory display, object of the invention.

As an example, we will examine the case of a row addressing circuit 22 _ℓ but the column addressing circuit 22 _c has a similar behavior (apart from the sign of the voltages).

The addressing circuit 22 _{ℓ is} used to apply a potential U _ℓ to the line electrodes for which the pixel is not to be switched, and to apply to the line electrodes for which the pixel is desired to switch a potential U _ℓa less than U _ℓ .

The addressing circuit 22 _ℓ comprises two parallel loops B₁ and B₂ each consisting of a transistor S, a diode D of an input and an output. The input of loop B₁ is subject to potential U _ℓa and the input of loop B₂ is subject to potential U _ℓ . The output of the two loops is common and is connected to a line electrode 12. The transistors S₁ and S₂ have a switching role and are controlled at their base by a logic stage 40 bringing the data necessary for the selection of the line electrodes participating in the pixel switching.

The transistor S₁ is of the bipolar NPN type and the transistor S₂ is of the FET NMOS type. The loop transistors, B₁ and B₂, thus give circuit 22 _ℓ the so-called "Push-Pull" configuration. The circuit 22 _ℓ is unipolar insofar as U _ℓ -U _ℓa has a sign determined by the diodes D₁ and D₂ connected in parallel with the transistors S₁ and S₂. The circuit 22 can be bipolar by replacing the diodes D₁ and D₂ by transistors.

A first means of reducing the currents flowing in the display is to subdivide the family of line electrodes into two sub-families of parallel electrodes receiving two respective control voltages which are in phase opposition with respect to the other.

In Figure 4, there is shown schematically a voltage generator coupled to a transformer phase shifting the control voltages into two voltages in phase opposition to each other. The transformer 30 is a transformer whose primary winding 31 is coupled to an alternating voltage generator 20 delivering the maintenance voltage. The midpoint of the secondary winding 32 is grounded. At the ends of the secondary winding, there are thus two alternating voltages 33 and 34 in phase opposition to each other. Two voltages in phase opposition can be obtained by other means, in particular logic electronic means.

In FIG. 5, there is shown schematically a first embodiment of a memory display making use of the generator of FIG. 4. First, we see a column electrode 18 and four row electrodes 12 (individualized in 12- 1 to 12-4). Each electrode is supplied with voltage by its respective addressing circuit 22. The four line electrodes 12 are broken down into two sub-families of line electrodes: in one of the two sub-families, the electrodes 12-1 and 12-3 receive a potential V _e delivered by the voltage generator 20 through line circuits CI _ℓ1 and CI _ℓ3 ; in the other of the two sub-families, the electrodes 12-2 and 12-4 receive a potential -V _e , in phase opposition with respect to V _e , also delivered by the voltage generator 20 through the circuits CI _ℓ2 and CI _ℓ4 . The column electrode 18 is connected to the potential U _c or U _ca by the addressing circuit 22 _c . Finally, the four pixels defined respectively by the overlap areas of the four row electrodes and of the column electrode have respective capacities C₁ to C₄.

In Figure 6, there is shown the equivalent diagram of a memory display. This comprises, by way of illustration, four maintenance voltages V _e1 to V _e4 having between them an electrical phase shift of 90 °. A group of four line electrodes has been shown (individualized in 12-1 to 12-4) each comprising schematically a pixel represented individually by its respective capacity in C₁ to C₄ The group constitutes an elementary period of the spatial distribution of the electrodes and the pixels of the family considered, which is that of the lines in this particular representation.

In general, the elementary period of the memory display with ℓ polyphase maintenance voltages, where ℓ is an integer, comprises ℓ electrodes each connected to one of these voltages via the addressing circuits of the family.

₁ +

₂ + ... +

_ℓ est nulle, en adoptant la convention de signe dénotée par les flèches sur la figure 6 qui illustre le cas particulier de ℓ = 4. Il en résulte que le courant référencé i sur la figure 5 et sur la figure 6, traversant le circuit d'adressage colonnes 22_c (ou, plus généralement, le circuit de l'autre famille) est au plus voisin d'un des courants I. Le courant circulant dans l'électrode colonne résistive est également de l'ordre de grandeur d'un des cou­rants I, et lui est toujours inférieur. Il est donc très notablement réduit par rapport au cas où l'alimentation serait unique et monophasée, selon le procédé connu, car alors le courant i est égal au produit du nombre d'électrodes de la famille par la valeur du courant I.The phases of the maintenance voltages being regularly distributed over 360 ° electrical, the sum of the displacement currents

₁ +

₂ + ... +

_ℓ is zero, by adopting the sign convention denoted by the arrows in FIG. 6 which illustrates the particular case of ℓ = 4. It follows that the current referenced i in FIG. 5 and in FIG. 6, crossing the circuit d column addressing 22 _c (or, more generally, the circuit of the other family) is at most close to one of the currents I. The current flowing in the column electrode resistive is also of the order of magnitude of one of the currents I, and it is always less. It is therefore very significantly reduced compared to the case where the supply would be single and single-phase, according to the known method, because then the current i is equal to the product of the number of electrodes of the family by the value of the current I.

It can be calculated that the current flowing in the resistive electrode of a screen with polyphase supplies is respectively 1/2, 1 / √3 and 1 / √2 times the current I in the case of 2, 3 and 4 phases. As a result, the voltage drop induced by this current is negligible.

It is also understood that the effectiveness of the invention is maximum when the subfamilies are well nested, as indicated in FIG. 6 for the case of four phases.

In the general case of an electroluminescent screen with memory, the pixels in the lit state do not have a purely capacitive behavior. When, within a period as defined above, the ℓ pixels are in the same state (off or on), the current outside the loop is zero. On the other hand, in the case where the pixels are not all in the same state, the compensation effect is no longer total. However, it remains effective since the displacement current is canceled. If we integrate this compensation effect on the entire column electrode, we can see that the least favorable case in terms of residual current is that where the pixels defined by the overlap area of the first subfamily of row electrodes with a column electrode are in the off state and the pixels defined by the overlap area of the second subfamily of row electrodes with the column electrode are in the on state. In this case, the conduction current I _c is not at all compensated. However, even in this case, the reduction in the peak value of the current flowing from one end to the other of the column electrode and in the addressing circuit thereof is significant compared to the least favorable case. map of a memory display of the prior art which is that of the fully lit column.

Furthermore, the displacement current is largely compensated regardless of the distribution of the on and off pixels.

Current i, which reaches the column addressing circuit, is responsible for the voltage drop in the column electrode.

This current i is obtained by the difference of the total current flowing in one of the sub-families of cross-line electrodes with the column electrode and that flowing in the other or the other sub-families of cross-line electrodes with the column electrode. In the most unfavorable case in terms of residual current for the display device according to the invention described above, ia the value defined by the appended formula IV where L and d are the length and the width of the electrode considered, and where I _on and I _off are respectively the current densities in an on pixel and in an off pixel.

In a memory display of the prior art, for the least favorable case, that is to say that where a column electrode has all its pixels lit, i has the value given by the attached formula V.

FIG. 7 shows a timing diagram illustrating the control of the pixels, in the particular case of the invention at two maintenance voltages in phase opposition. The maintenance voltage V _e applied to the electrodes and the total maintenance current I _{t are shown} . As described with reference to FIG. 5, I _d is compensated in accordance with the invention, I _t is therefore no longer represented except by a current whose variation as a function of time is the same as that of I _c . The current gain compared to the display described with reference to FIG. 2 is even greater when the pixel in the lit state is in a less excited state. The lesser excitation corresponds to a lesser electronic injection into the electroluminescent layer. This is particularly the case for the display with inherent memory or that with PC-EL memory with different characteristics for the PC layer. This also corresponds to a lower maintenance voltage in the display. The conduction current is therefore less important relative to the displacement current.

One thus obtains, in the example described in FIG. 2, a surface density of current for i of the order of 20 milli-amperes per square centimeter, while for the display according to the invention and when one adopts the two-phase power supply, the density of the current i is of the order of 6 milli-amperes per square centimeter.

If we consider the case of a column electrode of length L = 10 centimeters and width d = 300 micrometers with a filling rate of 70% along the column, the filling rate being the ratio between the surface of all the pixels of the column and the total area of the column electrode, the peak current which a column addressing circuit must be able to flow goes from 4 milliamps to 1.2 milliamps thanks to the invention.

C dans la formule III annexée. Cette formule est valable si les deux sous-familles sont suffisamment imbriquées pour que l'on puisse considérer que la répartition de l'émission le long de la colonne est homogène. On a vu que k prend en géné­ral une valeur comprise entre 2 et 3, donc le gain sur la longueur maximum L_M que peut avoir l'écran d'affichage est un facteur 1,7 à 2. Dans l'exemple suivant, R=20 ohms par carré, C=10 nanofarads par centimètre carré, k=3 et ω=2πxl kHz, avec une tolérance de 1% sur la tension V_e, l'afficheur PC-EL de l'art antérieur a une longueur maximum L_M de 10 centimètres tandis que l'afficheur conforme à l'invention a un L_M d'une valeur de 17 centimètres.The first embodiment of a memory display described with reference to FIG. 5, returns, by compensating for the current of the displacement I _d and by the fact that the lit area is twice less, in the most unfavorable case in terms of residual current, with respect to the memory matrix display of the prior art, to be replaced kC by

C in the attached formula III. This formula is valid if the two sub-families are sufficiently nested so that one can consider that the distribution of the emission along the column is homogeneous. We have seen that k generally takes a value between 2 and 3, so the gain over the maximum length L _M that the display screen can have is a factor 1.7 to 2. In the following example, R = 20 ohms per square, C = 10 nanofarads per square centimeter, k = 3 and ω = 2πxl kHz, with a tolerance of 1% on the voltage V _e , the PC-EL display of the prior art has a maximum length L _M of 10 centimeters while the display according to the invention has an L _M of a value of 17 centimeters.

It will be noted that the invention has no direct effect on the current caused by the switching of a column electrode. It is therefore necessary to choose switching conditions such that the switching currents I _co do not on the one hand increase the peak values of the maintenance current I _c and on the other hand do not excessively disturb the peak maintenance voltage V _e in particular at the end of the column. Referring to FIG. 7, it is preferable to choose an additional switching potential column U _c -U _ca of trapezoidal shape. The plateau of this additional potential coincides with the top of the maintenance voltage V _e . Thanks to the invention, the displacement current associated with the maintenance voltage V _e is fully compensated. The displacement current is therefore zero except at the time of electronic injection into the electroluminescent layer. Referring to FIG. 7, the current peak I _c corresponds to the electronic maintenance injection into the electroluminescent layer. We see that there are two windows F₁ and F₂ where the maintenance current is zero. These two windows have a duration of the order of 300 microseconds under the conditions of the display previously described with reference to FIG. 5. An improvement of the invention will consist in placing the sides of the trapezoidal potential increase U _c -U _ca in these two windows. In addition, under the following typical conditions I _co <6 milli-amperes per square centimeter, C = 10 nanofarads per square centimeter and U _c -U _ca = 45 Volts, we see that a time of the order of 75 microseconds is sufficient to provide the column electrode with an additional potential U _c -U _AC without delivering a current of more than 6 milli-amperes per square centimeter. It is therefore easy to include the sides of the additional trapezoidal switching potential in the windows where the current maintenance is zero.

In the case where the addressing circuits are controlled by unipolar voltages, it will be possible, in the same maintenance cycle, to address a line supplied by a voltage V _e and a line supplied by a voltage -V _e , in phase opposition to each other. Referring to FIG. 5, a line is addressed during the positive half-period of V _e , that is to say during the interval between T₁ and T₂ and the other line is addressed during the other half -period of V _e , that is to say during the interval between 0 and T₁. Thus, with a frequency of 1 kHz for the maintenance voltage, a writing speed of 2000 lines per second is doubled compared to that of the prior art described with reference to FIG. 2.

The first means of reducing the currents flowing in the display in accordance with the invention by subdividing the family of line electrodes into two sub-families of parallel electrodes receiving two respective control voltages which are in phase opposition one by compared to the other thus allows, compared to a display of the prior art, a reduction of the peak current passing through the column addressing circuits by a factor of 3 to 4, also resulting in an increase in the maximum length of the column electrodes by a factor of 1.7 to 2 and a doubling of the writing speed of an image.

More generally, the means of reducing the currents flowing in the memory display in accordance with the invention is to subdivide the family of line electrodes into several sub-families of parallel electrodes receiving as many respective control voltages whose phases are regularly distributed over 2π radians. By way of illustration but in no way limitative, we describe below the case where four voltages are used in phase quadrature.

First, we proceed to a first division in two groups R₁ and R₂ on the family of n line electrodes. We apply to these two groups of n / 2 line electrodes each of the potentials U _ℓ1 and U _ℓ2 in phase quadrature. Then, each group R₁ and R₂ undergoes the subdivision described with reference to FIG. 5, the two groups R₁ and R₂ of n / 2 line electrodes each are thus divided into two subgroups of n / 4 line electrodes each, one sub-groups being maintained by a potential U _ℓ1 or U _ℓ2 and the other by a potential -U _ℓ1 or -U _ℓ2 Preferably, the two sub-groups of each group R₁ and R₂ are nested or even interdigitated. In this way, the maintenance displacement currents are compensated for.

The most unfavorable case for the reduction of the currents flowing in the display is the case where the pixels of a sub-group of line electrodes of the group R₁ and of the group R₂ are all lit and where the pixels of the other sub-groups are all off. In this case, the compensation for the conduction currents in the resistive column electrodes cannot be taken advantage of. However, there is no overlap between the two conduction current peaks relative to R₁ and relative to R₂.

In part a of FIG. 8, there is shown a timing diagram illustrating the control of the pixels in the case where the voltages applied to the line electrodes are in phase quadrature with respect to each other. Four maintenance voltages V _e1 , V _e2 , V _e3 , V _e4 are shown which are in phase quadrature with respect to each other. The total maintenance current I _t associated with these voltages is also shown, in the most unfavorable case where the pixels of the sub-families supplied by V _e3 and V _e4 are on, the others being off. According to the invention, the total maintenance current is therefore no longer represented except by a current varying in proportion to its component I _c .

Referring to part a of FIG. 8, we see that, in the most unfavorable case, the maximum peak value of the total current I _c is equal to that of one of the peaks constituting it. However, each peak corresponds to the emission of n / 4 pixels from the column electrode only. Thanks to the invention, a factor 2 is therefore gained over the peak value of the current obtained in the display described with reference to FIG. 5. Under the experimental conditions described with reference to FIG. 5, the invention allows a gain of a factor of 7 on the current supplied by the column addressing circuits relative to the display of the prior art described with reference to FIGS. 1 and 2.

C, le gain résultant sur la longueur maximale admissible L_M est d'un facteur 2,4 à 2,8. Dans l'exemple décrit précédemment, on obtient une longueur L_M de 24 centimè­tres pour une tolérance de 1% sur la tension.If the groups R₁ and R₂ are themselves nested as shown diagrammatically in FIG. 6, it can be assumed that the emission of each of these groups is homogeneous along the column. Thanks to the invention, in the attached formula III, kC is replaced by

C, the resulting gain over the maximum admissible length L _M is by a factor of 2.4 to 2.8. In the example described above, a length L _M of 24 centimeters is obtained for a tolerance of 1% on the tension.

As in the display described with reference to FIG. 7, care must be taken to ensure that the column switching currents I _co do not increase the peak values of the maintenance current. Thus, under the following typical conditions: I _co <3 milli-amperes per square centimeter, C = 10 nanofarads per square centimeter and U _ca = 45 Volts, we see that a time of the order of 150 microseconds is sufficient to provide on the column electrode an additional column potential U _c -U _ac without delivering a current of more than 3 milli-amperes per square centimeter.

Referring to part a of FIG. 8, it can be seen that there are four windows FI, FII, FIII, FIV with a duration of the order of 150 microseconds between the four peaks of conduction current. These windows thus make it possible to switch the column electrode in phase with the maximum of any one of the four maintenance voltages.

In part b of FIG. 8, there is shown a timing diagram illustrating the switching of a column electrode when the voltages applied to the line electrodes are in phase quadrature with respect to each other. There is shown two additional switching potential column U _c1 -U _ca1 and U _c2 -U _ca2 of trapezoidal shape. These two potential overcharges correspond in this example to the ignition of the pixels addressed by the line electrodes subjected to V _e2 and V _e4 . The pixels addressed by the line electrodes subjected to V _e1 and V _e3 are extinguished here. The dotted line placed between the two excess switching potentials U _c1 -U _ca1 and U _c2 -U _ca2 represents the additional switching potential corresponding to the ignition of the pixels addressed by the line electrodes subjected to V _e3 .

Thanks to the invention, it is possible to address, with unipolar addressing circuits, four lines per maintenance cycle. This increases the writing speed of an image up to 4000 lines per second.

The particular means of reducing the currents flowing in the display in accordance with the invention by subdividing the family of line electrodes into four sub-families of parallel electrodes receiving four respective control voltages which are in phase quadrature with respect to each other to the others thus allows, compared to the display of the prior art described with reference to FIGS. 1 and 2, a reduction of peak current passing through the column addressing circuits by a factor of 7, thus causing an increase in length. maximum of the column electrodes by a factor 2.4 to 2.8 and a quadrupling of the writing speed of an image.

In the particular case where a three-phase alternating voltage generator is used, the corresponding means of reducing the currents flowing in the display is to subdivide the family of line electrodes into three sub-families of parallel electrodes receiving three voltages of ordered which are 120 degrees electrical out of phase with each other.

Referring to Figure 9, there are shown three maintenance voltages V _e1 , V _e2 and V _e3 phase shifted by 120 electrical degrees relative to each other. The total maintenance current I _t associated with these voltages is, by reasoning similar to that described with reference to FIGS. 5 and 7, equal to the conduction current I _c , since the displacement current I _d of maintenance is fully compensated . The total maintenance current I _t is therefore represented by the sum of the conduction currents I _c1 , I _c2 and I _c3 associated with the maintenance voltages. These conduction currents are assigned a multiplying coefficient between 0 and 1 representing the ignition rate of the column electrode pixels belonging to the corresponding subfamily.

The most unfavorable case for the reduction of the voltage drop, from one end to the other of a column electrode is that for which the pixels of one of the three subfamilies are all on and all the others off. . Compared to the prior art, this third means makes it possible to eliminate the maintenance displacement current and to reduce the peak values of conduction current by a factor of 3 since each subfamily occupies an area equal to one third of the area total of the display. Compared to the example of the display described with reference to FIGS. 1 and 2, the peak current flowing in the column electrode and in the corresponding addressing circuit drops from 20 milliamps per square centimeter to 4 milliamps per square centimeter, a gain of a factor of 5.

It is also necessary to choose switching conditions suitable for the maintenance voltages so that the switching currents do not risk increasing the peak value of the maintenance current. Each conduction current peak I _c can only take one polarity, only its amplitude can vary depending on the ignition rate of the pixels of the electrode column considered. We therefore seek to make the switching current of the column electrode coincide with a peak of maintenance current of opposite polarity. This prevents the peak currents from being added. This advantageous procedure is applicable when the number of phases of the maintenance supply is, as is the case in the present example, odd.

Referring to FIG. 9, the switching current I _co of the pixel maintained by the maintenance voltage V _e1 is placed in temporal coincidence with the peaks of maintenance conduction current I _c2 associated with the maintenance voltage V _e2 . Advantageously, the additional switching potential U _c1 -U _ca1 is of trapezoidal shape. In accordance with the typical conditions described with reference to FIG. 7, there are maintenance switching windows F with a duration of 150 microseconds. However, windows with a duration of 110 microseconds are sufficient to switch a column electrode from 0 to 45 volts without exceeding a switching current of 4 milliamps per square centimeter.

It is also possible to switch three pixels and therefore three lines per maintenance cycle. Consequently, the writing speed of an image is tripled with respect to the display described with reference to FIGS. 1 and 2.

The invention can be generalized to a set M of maintenance voltages out of phase with each other, in opposition two by two or not, each voltage being applied to a subset R _i of neither line electrodes.

In the present description of the invention, the maintenance voltage is of simple sinusoidal shape. However, the invention is applicable to any type of symmetrical bipolar voltage: triangular, rectangular, trapezoidal or more complex. Constraints external to the display object of the invention can impose the use of asymmetric bipolar maintenance voltages. In this case, the invention no longer allows perfect compensation for the displacement current, but we still obtain a reduction in this.

In order to facilitate understanding of the present description, we have limited ourselves to simple maintenance and pixel switching voltages. The invention applies of course to more complex maintenance voltages making it possible to increase the tolerances on the voltages of switching on and off of the pixels or else to shorten the time of switching on of the pixels.

C × 1/35. En revanche, le faible taux de remplissage des pixels conduit à une augmentation de la résistance des électro­des colonnes, donc à un accroissement de la résistance surfa­cique apparente R. Toutefois, un dessin d'électrode approprié permet de limiter cette augmentation de R à un facteur 2 seulement, soit à une valeur typique de 50 ohms. Dans ces conditions, on obtient alors un gain d'un facteur 9 à 10,5 sur L_M par rapport à l'art antérieur, soit un L_M de 1 mètre pour une tolérance de 1% sur la tension d'entretien.

The invention can be combined with other power reduction techniques circulating in the PC-EL display as described in the French Patent Application ^No. 8611808 of August 18, 1986. This technique involves using pixels at low rates filling for a PC-EL display. We can consider the realization of a PC-EL screen whose filling rate is 1/35. Under these conditions, the current delivered by the column addressing circuits is 6/35 milli-amperes per square centimeter, that is to say 0.17 milli-amperes per square centimeter. Therefore, addressing a column 10 centimeters long and 300 micrometers wide requires peak currents of only 50 micro-amps. To estimate the maximum length of the column electrodes, replace in the attached formula III kC with

C × 1/35. On the other hand, the low pixel filling rate leads to an increase in the resistance of the column electrodes, therefore to an increase in the apparent surface resistance R. However, an appropriate electrode design makes it possible to limit this increase in R to a factor 2 only, ie at a typical value of 50 ohms. Under these conditions, a gain of a factor 9 to 10.5 is obtained over L _M compared to the prior art, ie an L _M of 1 meter for a tolerance of 1% on the maintenance voltage.

Claims (13)

1. Memory effect electroluminescent display comprising at least one layer having an electro-optical property with memory effect framed by a first (12) and a second (18) family of electrodes orthogonal to each other, a display point or pixel being defined by the overlap area of a particular electrode of a family (12) and of a particular electrode of the other family (18), this display further comprising a generator capable of generating an alternating maintenance voltage for the electrodes and means for selectively applying voltage variations relative to the maintenance voltage to electrodes of the two families in order to allow the addressing of one or more particular pixels, this display being characterized in that the generator is capable of generating several phase-shifted voltages and that at least one (12) of the families of electrodes is subdivided into at least two sub-families of parallel electrodes each receiving a e of these maintenance voltages out of phase with each other. 2. Display according to claim 1, characterized in that the layer having an electro-optical property with memory effect comprises a photoconductive layer (14) and an electroluminescent layer (16) superimposed. 3. Display according to claim 1, characterized in that the material of the layer having an electro-optical property with memory effect is for example zinc sulfide activated by manganese, or any other material emitting light under the effect of an electrical voltage. 4. Display according to any one of claims 1 to 3, characterized in that the maintenance voltages are two in number and that they are in phase opposition to each other. 5. Display according to any one of claims 1 to 4, characterized in that the maintenance voltages are four in number and that they are in phase quadrature with respect to each other. 6. Display according to any one of claims 1 to 5, characterized in that the maintenance voltages are three in number and that they are phase-shifted by 120 electrical degrees with respect to each other. 7. Display according to any one of claims 1 to 6, characterized in that the voltage generator is coupled to at least one voltage transformer in order to generate the phase-shifted voltages with respect to each other. 8. Display according to any one of claims 1 to 7, characterized in that one (12) of the two families of electrodes is made of aluminum and that the other family (18) of electrodes is made of oxide d tin and indium or any other conductive and transparent material. 9. Display according to any one of claims 1 to 7, characterized in that the two families of row (12) and column (18) electrodes are made of indium tin oxide or any other conductive material and transparent. 10. Display according to any one of claims 1 to 9, characterized in that the other (18) of the families of electrodes is also divided into at least two sub-families of parallel electrodes each receiving one of the voltages maintenance out of phase with each other. 11. Display according to any one of claims 1 to 10, characterized in that the voltage variations relative to the maintenance voltage intended to modify the displayed image are placed in the time intervals between the vertices of the current of maintenance circulating in the electrodes of the sub-family considered. 12. Display according to any one of claims 1 to 11, characterized in that the means allowing the addressing of the pixels comprise unipolar addressing circuits of the push-pull type. 13. Display according to any one of claims 1 to 11, characterized in that the means allowing the addressing of the pixels comprise bipolar addressing circuits of the push-pull type.

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