EP0318374A1 - Methods and devices for recording and/or transmitting high rates of binary signals by known means for the recording and/or transmission of video signals and for rereading the digital information - Google Patents

Abstract

A device according to the invention comprises a quartz oscillator (12) which oscillates at a frequency equal to that of a carrier wave for chrominance signals, for example at 4.43 MHz. It comprises a phase modulator (21) which receives this frequency and which also receives binary signals and a carrier wave all-or-nothing phase-modulated by the binary signals is collected at the modulator output terminals. …<??>One application is the recording and/or simultaneous transmission of a black and white video image and of the digital information measured during image capture. …<IMAGE>…

Description

The present invention relates to methods and devices for recording and / or for transmitting remotely and for replaying binary signals which appear at a rate of up to 1 Mbit / second, using known means for recording and / or transmission of video signals and methods and devices for replaying digital information.

The technical sector of the invention is that of recording and transmission of digital data encoded in binary.

There are many cases of industrial installations, in which binary signals pass at a high rate, in series on a common line (bus) or in parallel on several lines.

In many practical cases, these signals frequently appear at the same time as video signals supplied by a television camera or by an image analyzer.

An objective of the present invention is to provide means making it possible to record these binary signals produced at high rate or to transmit them using the same video recorders and / or the same means of transmission as those which are used to record and / or for transmitting the video signals by the PAL method or by the NTSC method.

In the case where the binary signals are transmitted at the same time as the video signals, another objective of the invention is to provide means making it possible to simultaneously record the luminance video signals and the binary signals, on the same medium. recording and / or transmitting them simultaneously through the same channel, so that the time relationship between video images and digital values measured simultaneously can be preserved.

A non-limiting example of a practical use case of the invention is that of a central unit which is connected by a single-line bus or by a bus composed of several lines parallel to several stations, each comprising a sensor which sends digital information on the bus in the form of binary signals at very high rate, of the order of 1 Mbit / sec.

The central unit can be, for example, a central control unit for a manufacturing process, for example a distillation tower, or a rolling mill train, or a nuclear reactor, etc., which is connected to different temperature, pressure, level sensors etc. or to servomotors fitted with a local microprocessor. It is advantageous to be able to record all the binary signals which circulated on the bus during a determined period in order to be able to analyze these signals in the event of an incident or to be able to verify the operation of the installation or to keep a complete recording of a period real tests in order to then analyze in more detail the evolution of the various parameters of the installation throughout this test period.

The present invention provides means which allow 2.5.10⁹ bits to be recorded for one hour of operation with a bit rate of the order of 0.7 Mbit / sec.

The industrial installation can also include a television camera which delivers images of one of the elements of the installation. For example, a locomotor robot may include a camera which provides images of the space in front of a robot and various actuators which are connected to a central unit by a common line (bus), on which they receive binary signal trains which control the motors of these actuators. In such a case, the present invention provides means which make it possible to record simultaneously on the same medium the black and white video signals supplied by the camera and the binary signals passing through the bus, which then makes it possible to reconstruct and d '' study the state of each actuator in correlation with the position of the robot in space, which is given by the television image.

It will be recalled that the PAL television method comprises a luminance signal and a chrominance signal which is carried by a subcarrier wave generally having a frequency of 4.43 MHz, which is phase modulated and which has a passband having a width of about 1 MHz. This bandwidth of 1 MHz allows this subcarrier wave to be used to convey and / or record binary signals whose transmission rate can reach 1 Mbit / sec.

The magnetic tapes used in PAL standard industrial video recorders, for example in "U-MATIC" brand video recorders sold by SONY, contain cassettes allowing one hour of recording, ie 2.5 Gbit, at the rate of 0.7 Mbit. /dry.

A method according to the invention consists in associating with a VCR with the PAL or NTSC standard, an electronic device which makes it possible to phase modulate a subcarrier wave having a frequency of 4.43 MHz, by means of the binary signals to be recorded instead to modulate it in phase by a chrominance signal then to record this modulated wave on said video recorder in PAL or NTSC standard, as we would record the chrominance signal.

A device according to the invention, in which six bytes per line are recorded while keeping approximately 600 lines per image, makes it possible to record approximately 700,000 bits / second.

The objectives of the invention are achieved by a method for recording and / or for transmitting a high bit rate of binary signals using known means for recording and / or transmission of video signals, which method comprises the following operations:
- a carrier wave is generated having a frequency equal to that of a carrier wave of analog chrominance video signals;
- said carrier wave is modulated in phase at 0 ° or 180 ° by said binary signals by means of a phase modulator;
- the modulated wave is mixed with video synchronization pulses and with phase reference bursts and the signals obtained can be recorded on a video recorder in PAL or NTSC standard and / or transmitted remotely.

A method according to the invention for reading digital information coming from a video recorder, from an antenna or from a video cable, in the form of a video carrier wave modulated in phase and mixed with synchronization pulses and with phase reference bursts include the following operations:
- isolating said carrier wave modulated in phase by means of a bandpass filter;
- Generates pulses enveloping said reference bursts by means of a pulse separator circuit;
- sending said phase-modulated carrier wave and said pulses envelopes phase reference bursts, on two inputs of a circuit which continuously transmits a reference wave in phase with said phase reference bursts and which allows said wave to pass modulated in phase;
- sending said reference wave on an input of a phase demodulator circuit and said phase modulated wave on another input of said phase demodulator circuit;
- And we collect at the output of said phase demodulator circuit, pulses which reproduce the binary signals representing said digital information.

Advantageously, a method according to the invention is used for recording and / or for transmitting, by known means of recording and / or transmission of video signals, both a high bit rate of binary signals representing digital information and images black and white video taken at the same time as the digital measurements.

In this case, a method according to the invention comprises the following operations:
the video signals are filtered by means of a plug filter which stops the carrier wave modulated by the chrominance signals having a frequency of 4.43 MHz and which lets the luminance signals and the synchronization pulses pass;
- a carrier wave is generated having a frequency of 4.43 MHz;
- said carrier wave is modulated in phase at 0 ° or 180 ° by said binary signals by means of a phase modulator;
- and the luminance video signal, the synchronization pulses, said phase-modulated 4.43 MHz wave and the phase reference bursts are mixed, so that video signals are obtained which can be recorded on a video recorder and / or transmitted remotely via a video channel and which make it possible to obtain both black and white images and digital data.

Advantageously, certain numbers of lines are determined at the start and at the end of each video frame which do not support any digital information in order to avoid phase disturbances due to switching of the read heads of the video recorder, which could cause errors in the digital information transmitted and / or read after recording.

According to a characteristic of the invention, a reference edge is created at the start of each of the lines carrying digital information, which precedes the first binary signal by a definite duration and which is transmitted and / or recorded as a binary signal .

A device according to the invention, for recording and / or for transmitting digital information by known means on video comprises an oscillator stabilized by a quartz which emits a wave having a frequency equal to that of the carrier wave of the chrominance signals and a phase modulator which receives said carrier wave on one of its inputs, which receives said binary signals on its control terminal and which delivers, on its output, said non-phase-shifted carrier wave while said binary signal is at zero level and phase-shifted at 180 °, while said binary signal is at level 1, a video synchronization pulse generator and a mixer which receives said video synchronization pulses and said phase modulated carrier wave and which mixes them.

A device according to the invention for reading digital information leaving a video recorder, an antenna or a video cable in the form of a carrier wave modulated in phase by binary signals and mixed with synchronization pulses and to phase reference bursts, comprises a bandpass filter, tuned to the frequency of said carrier wave which allows the latter and said phase reference bursts to pass; a synchro extractor associated with a synchro separator, which transmits on an output envelope pulses of said reference bursts; a reference generator which has two inputs, an input connected to the output of said filter and an input connected to said output of said sync splitter and which has two outputs, a first output which delivers a reference wave in phase with said reference bursts phase and a second output which delivers said phase modulated wave and a phase demodulator, the modulated wave input of which is connected to said second output and the output of which delivers pulses which constitute said binary signals.

The invention results in the ability to record in analog form a very large amount of digital information on VCR tapes, using commercially available tapes and VCRs.

The invention also makes it possible to remotely transmit a large flow of digital information, of the order of 700 Kbits / sec, in analog form using the existing video transmission means.

A particular advantage of the method and the devices according to the invention lies in the fact that they make it possible to simultaneously record or transmit video signals representing a black and white image and digital information measured during the taking of video images, this which allows to keep the temporal relation between the images and the measurements, which is often very useful to interpret the measurements.

The modulation and demodulation devices according to the invention make it possible to place digital information on a video carrier wave using known phase modulators, for example ring frequency mixers which are usually used to obtain a beat frequency or as modulators of one frequency by another frequency.

• La figure 1 est un schéma général sous forme de bloc diagramme des circuits et composants essentiels d'un dispositif selon l'invention destiné à placer des informations numériques sur une onde porteuse vidéo, afin de permettre l'enregistrement et/ou la transmission des valeurs numériques par des moyens vidéo connus.
• La figure 2 est un schéma d'un mélangeur de fréquences ou modulateur de phase en anneau.
• La figure 3 est un chronogramme des impulsions apparaissant en divers points des circuits de la figure 1 pendant les lignes qui sont utilisées pour supporter des informations numériques.
• La figure 4 est un schéma général sous forme de bloc diagramme des circuits et composants essentiels d'un dispositif selon l'invention destiné à lire les informations numériques supportées par une onde porteuse vidéo sortant d'un magnétoscope, d'une antenne vidéo ou d'un câble vidéo.
• La figure 5 est un chronogramme des impulsions apparaissant en divers points des circuits de la figure 4 pendant les lignes qui sont utlisées pour supporter des informations numériques.
• La figure 6 est une vue d'ensemble d'une installation selon l'invention pour enregistrer des valeurs numériques et pour les traiter ultérieurement.

The following description refers to the appended drawings which represent, without any limiting nature, exemplary embodiments of devices according to the invention.

• FIG. 1 is a general diagram in the form of a block diagram of the essential circuits and components of a device according to the invention intended to place digital information on a video carrier wave, in order to allow the recording and / or the transmission of the values digital by known video means.
• Figure 2 is a diagram of a frequency mixer or ring phase modulator.
• Figure 3 is a timing diagram of the pulses appearing at various points in the circuits of Figure 1 during the lines that are used to support digital information.
• Figure 4 is a general block diagram diagram of the essential circuits and components of a device according to the invention intended to read the digital information supported by a video carrier wave coming from a video recorder, a video antenna or a video cable.
• Figure 5 is a timing diagram of the pulses appearing at various points in the circuits of Figure 4 during the lines that are used to support digital information.
• FIG. 6 is an overall view of an installation according to the invention for recording digital values and for processing them subsequently.

FIG. 1 is a block diagram of the components and modulation circuits which make it possible to obtain a carrier wave having a frequency which corresponds to that of the carrier wave of the chrominance video signals, mixed with video synchronization pulses, called frame synchro or image and line sync and to phase-modulate this carrier wave by binary signals representing digital values, which phase-modulated wave can be recorded on a video recorder in PAL or NTSC standard or can be transmitted remotely on any link existing video (channel or cable).

FIG. 1 represents a first block 1 which optionally receives on an input terminal 1a, video signals coming from a video camera or from a video image synthesizer.

These video signals include synchronization pulses (image sync and line sync), a luminance video signal which makes it possible to obtain black and white images and, possibly a chrominance video signal which is supported by a carrier wave, which has generally a frequency of 4.43 MHz and which is phase modulated.

The video signals are sent to a sync extractor 3 which controls a two-stage switch 4a, 4b. The sync extractor 3 detects the presence or absence of a video signal on terminal 1a and emits a logic signal which actuates the switch 4a, 4b.

Block 1 comprises a generator 5 which transmits on a first output terminal 5a a video signal of uniform luminance and on a second output terminal 5b of synchronization pulses video.

The first stage 4a of the switch has two input terminals, one connected to terminal 1a and the other connected to terminal 5a.

The output of the first stage 4a is connected to a filter 6 which is a plug circuit tuned to the frequency 4.43 MHz. This circuit eliminates the chrominance signal contained in the video signal received on terminal 1a. It only lets through the luminance video signal and the synchronization pulses.

Block 1 includes a regenerator and separator for synchronization pulses 7.

The second stage 4 b of the switch has two inputs which are connected one to terminal 5b and the other to the output of the sync extractor 3.

The function of the synchro extractor 3 is to isolate the synchronization pulses and transform them into logic signals according to the T.T.L.

CCIR standard synchros have, for example, an amplitude of 300 mv and extractor 3 delivers logic signals at the 0-5 volt level compatible with T.T.L circuits.

The regenerator and synchro separator circuit 7 has four outputs marked 7₁, 7₂, 7₃ and 7₄ respectively.

The output 7₁ delivers pulses which correspond to the line synchros.

The output 7₂ delivers pulses corresponding to the frame synchros.

The output 7₃ delivers a logic signal at level 0, in the case of a frame of even rank and at level 1 in the case of a frame of odd rank.

The output 7₄ delivers a signal called the reference burst envelope, which is located at a determined instant after each line sync and which has a determined duration.

It is recalled briefly that the video signals are composed of two half-images or frames called even, comprising 312 lines and odd comprising 313 lines for a standard with 625 lines. The lines of the two frames are interlaced. Each frame begins with a so-called frame sync pulse and each line begins with a line sync. Each line lasts 64 µ and there are 25 frames / second.

The video images are generated in the form of a luminance signal which is represented by the amplitude of the video signal and of a chrominance signal which, in the PAL and NTSC standards which are of interest to the invention, modulates in phase a sub -carrier generally having a frequency of 4.43 MHz.

At the start of each line, immediately after each line sync, the chrominance signal includes some half-wave alternations of the carrier wave, intended to serve as a zero phase reference. These alternations are called reference bursts or "burst" signal.

The methods according to the invention use a carrier wave having a frequency of 4.43 MHz, to support digital information in binary form, which modulate this wave in phase by all or nothing, the zero binary level corresponding to a zero phase shift and the binary level 1 corresponding to a 180 ° phase shift.

At the beginning of each frame, the carrier wave risks being disturbed and it is necessary to avoid using the disturbed zones which would risk bringing errors on the digital information. It is therefore necessary to choose in each frame, the lines which can be used to support the digital information while eliminating the risks of errors.

Another difficulty lies in the arrangement of the digital information on the lines, in order to be able to re-read this information without error in the reading module.

Digital information cannot be placed on all lines of even and odd fields.

In fact, when the video signals are recorded on a video tape, the tape is played along oblique lines using several magnetic heads which are connected alternately.

The switching of the heads leads to disturbances and instability of the phase which can last up to 15 or 25 lines depending on the quality of the video recorder. This instability is due to the time necessary to reset itself to the zero reference phase given by the reference burst. It is also due to the quality of the video recorder, in terms of the servo-control of the speed of rotation of the read heads and the speed of movement of the magnetic tape.

The switching of the read heads takes place approximately 1 to 6 lines before each frame sync.

In addition, it is very important to place the digital information in well-defined locations on each line in order to be able to retrieve it accurately on the reading module.

According to the present invention, there are placed in series on each video line only 5 or 6 bytes, more than 5 control bits at the end of the line.

The problem to be solved is to determine, in a precise manner, the beginning of the digital information on each line.

One could consider placing this start at a determined distance from the preceding line sync, but this solution is not satisfactory.

Indeed, the line and frame synchros can be altered by disturbances.

According to the invention, the digital information is arranged on each line with respect to a particular signal called the reference edge, which is generated by the modulation circuits and which follows the digital information, that is to say which is recorded or transmitted at the same time as these, that it immediately precedes on each line, so that it is recognized by the read and demodulation circuits.

According to the invention, a reference front is created on each line which serves as a precise origin for the digital information and which is a phase change from 0 ° to 180 °. This phase change has a fixed duration and the digital information begins immediately after.

This reference edge is located at a determined distance from each line sync, for example at 8 alternation of the 4.43 MHz signal.

After having explained the problem of positioning digital data on certain lines, we return to the circuits of FIG. 1, which represents the means for obtaining this precise positioning.

FIG. 1 represents a block 8 which contains several counters associated with memories intended to generate signals which are used to control the recording of the digital values on the subcarrier wave at 4.43 MHz.

Block 8 contains a first pulse counter 9, the clock input of which is connected to the output 7₁ of the regenerator 7. The counter 9 is a 9-stage counter capable of counting up to 2⁹ = 512, which receives and counts the line synchros. The nine stages of the counter are connected on nine stages Ao to A8 of a memory 10 having a capacity of 1 Kilobits (1024 no address).

This counter 9 and memory 10 assembly is intended to select the video lines that will be used to support the binary signals.

The reset terminal RESET of the counter 9 is connected to the output 7₂ and receives the frame synchros.

Counter 9 can count up to 512. It is reset to zero by each frame sync after having alternately counted 312, then 313, then 312 etc ...

The counter 9 serves as an address counter for the memory 10. The last stage A9 of the memory 10 is connected to the output 7₃ and therefore alternately receives a binary signal 0 for the even frames and a binary signal 1 for the odd frames.

We want to avoid using the first and last lines of each frame to support digital information. For example, we want to avoid using the first sixteen lines 0 to 15 of each even and odd frame, the last seven lines 306 to 312 of each even frame and the last seven lines 307 to 313 of each odd frame.

We program the memory to achieve this goal, that is to say that we write a 1 in the memory boxes corresponding to the addresses 0 to 15 and 306 to 312, as well as to the addresses 512 to 527 and 819 to 821 and a zero in all the other boxes of the memory which correspond to the lines that we want to use.

The output S1 of the memory is connected to the most significant input terminal of two other memories, which are described below.

Block 8 contains a second counter 11, identical to counter 9, which is associated with a second memory 11a, identical to memory 10, of which it serves as an address counter.

The clock input of the counter 11 is connected to an electronic clock 12, stabilized by a quartz, the frequency of which is 4.43 MHz. The counter reset terminal 11 is connected to the output terminal 7₁ and therefore receives the line synchros.

The counter 11 and memory 11a assembly is intended to generate the bit shift signals in the parallel / serial shift registers to attack the phase modulation. It also has the function of delivering the reference fronts which are added at the start of each serial information to properly locate this start.

The most significant bit A9 of memory 11a is connected to the output S1 of memory 10, which is at level zero or 1. If the output S1 is at level 0, the information can exit from the second memory 12. If, on the contrary, the output S1 of the memory 10 is at level 1, the memory 12 is inhibited and it does not emit any output.

The period of the wave at 4.43 MHz lasts 0.225 µs. A video line lasts 64 µs, from which 4 µs must be subtracted for line sync. There remain therefore 60 μs during which 226 wave alternations at 4.43 MHz take place.

The counter 11 can count up to 512, but it is reset to zero for each line sync when it has reached 226.

The memory 11a has three outputs marked T1, T2 and T3.

The T1 output defines the position of the reference edge on each line, the T2 output emits a rectangular pulse called the envelope of the reference edge which frames the reference edge and which serves to switch the reference edge to the phase modulator and then the binary signals representing digital values.

The output T3 emits pulses in the form of a slot whose duration is equal to four half-waves of 4.43 MHz, or 900 µs, which serve as clock pulses controlling the shift registers.

The output T3 is connected to the clock input of a third pulse counter 13, identical to the counters 9 and 11. The reset terminal of the counter 13 is connected to the terminal 7₁ and receives the line synchros. The counter 13 is associated with a third memory 14 and acts as an address counter of it.

The most significant input A6 of this memory is connected to the output S1 of the first memory 10. The memory 14 has three channels V1, V2 and V3.

The counter 13 and memory 14 assembly is intended to deliver switching pulses from the shift registers and to generate request pulses for presentation of a byte at the input of the shift registers.

The counter 13 counts the pulses emitted by the output T3 of the second memory. As there are six bytes of digital information on each line plus four control bits, making a total of 52 bits, the counter 13 counts from 0 to 52, then it is reset to zero by the following line sync.

The output V1 emits a pulse at the start of each byte and at the start of the control byte. The output V2 sends request pulses for loading a byte in the shift registers.

The output V3 emits a request pulse to load the control byte into the shift registers.

FIG. 1 represents a block 15 which includes the circuits and components which make it possible to modulate in phase, in all or nothing, a wave having a frequency of 4.43 MHz, by digital information in binary code.

Block 15 includes an electronic clock 12 which is an oscillator stabilized by a quartz having a natural frequency of 4.43 MHz.

Oscillator 12 has an output at logic level T.T.L. which is connected, as we have seen, to the input of the counter 11. This output is also connected to a filter 16 with narrow passband which allows only the fundamental sinusoidal frequency to 4.43 MHz to pass.

The output of the filter 16 is connected in parallel on two phase shifters 17 and 18 which phase shift the oscillating voltage by + 45 ° and - 45 ° respectively, in order to obtain two sinusoidal voltages phase shifted by 90 °.

The filter output is connected to each phase shifter via a 19₁ or 19₂ potentiometer, which allows the amplitude of the carrier wave to be adjusted to 4.43 MHz.

It is easier to realize two phase shifts at ± 45 ° than a single phase shift at 90 °, because the phase stability is better. However, the two phase shifters 17 and 18 could be replaced by a single 90 ° phase shifter, placed on one of the two channels.

This 90 ° phase shifter is due to the need to be compatible with the PAL standard, in which the reference bursts are phase shifted from one line to the next by + 90 ° to allow phase drifts to be eliminated.

Block 15 comprises two identical circuits 20 and 21 which are essential circuits, in which the phase of the carrier wave having a frequency of 4.43 MHz is modulated by the binary signals which constitute the digital information.

FIG. 2 is a diagrammatic representation on a larger scale of a nonlimiting embodiment of one of the circuits 20 or 21, it being specified that these circuits can be formed by any known phase modulator.

Each circuit 20 or 21 is a circuit known as a frequency mixer or a ring modulator or demodulator, or a double-balanced mixer (DBM), which can be used to mix two frequencies called local oscillation ( LO) and radio frequency (RF) to obtain a beat frequency called intermediate frequency (IF). These circuits are sold for example by the firm Scientific Components Corp. in the SRA series. They comprise a primary winding 22, having terminals 1 and 2 between which a first voltage is applied, for example the local frequency (L.O.). This primary winding 1 is coupled by induction with two first secondary half-windings 23₁ and 23₂, having a midpoint connected to a terminal 3. It comprises two second output half-windings 24₁ and 24₂ having a midpoint which is connected to a terminal 4.

The two half-windings 24₁ and 24₂ are coupled by induction with an output winding 25 having two terminals 7 and 8, between which a second so-called radio frequency (RF) voltage is applied. It comprises a diode bridge 26 whose two ends of a diagonal are connected to the external ends of the first two secondary half-windings 23₁, 23₂ and whose two ends of the other diagonal are connected to the two outer ends of two second secondary half-windings 24₁, 24₂.

The intermediate voltage or beat voltage is recovered between terminals 3 and 4.

This circuit is reversible. These circuits can be used to detect a phase difference between two voltages of the same frequency applied respectively between terminals 1 and 2 and terminals 7 and 8 and, in this case, a direct current proportional to the phase difference. This application is also reversible. The present invention uses this second property of ring mixers.

If one applies a sinusoidal voltage between two extreme terminals 1 and 2 for example and pulses in crenellations between terminals 3 and 4, one obtains between terminals 7 and 8 a sinusoidal voltage of the same frequency as the applied voltage between terminals 1 and 2 which will not be phase-shifted when the square wave voltage is at level zero and which will exhibit a determined phase shift for example 180 ° when the square wave voltage is at level 1.

Conversely, if a sinusoidal alternating voltage is applied to terminals 1 and 2 and a voltage of the same frequency which is alternately 180 ° phase-shifted and not phase-shifted at terminals 7 and 8, a voltage is obtained between slots 3 and 4 , i.e. impulses.

Circuits 20 and 21 can therefore be used to phase-modulate a sinusoidal voltage applied between terminals 1 and 2 or 7 and 8, by a series of pulses representing binary numbers applied in series between terminals 3 and 4 and c ' is this application which is used in block 15 of figure 1.

Identical mixer circuits can also be used to demodulate a phase-modulated voltage and it is this second application which is used in the demodulator circuits which will be described below.

Returning to FIGS. 1 and 2, the voltage at 4.43 MHz leaving the phase shifter 17 is applied between the input terminals 1 and 2 of the mixer circuit 20 and between the terminals 1 and 2 of the mixer circuit 21 the voltage at 4.43 MHz out of phase shifter 18.

FIG. 1 shows two voltage sources + V and -V for example + 200 mV and - 200 mV, which represent the level 1 and level 0 of the pulses conveying the digital information. These two sources are connected to the two inputs of a switch 27, which is controlled by the pulses representing the digital information arriving in series, on a line 28 coming from another block 29 which will be described later.

The common output of switch 27 is connected in parallel respectively to an input terminal of a first switch 30₁, the second input terminal of which is grounded and to an input terminal of a second switch 30₂, of which the second input terminal is grounded. These two switches 30₁ and 30₂ are controlled simultaneously by pulses arriving by a line 31, which comes from block 29 and which make it possible to introduce phase reference bursts into the signals. The two switches 30₁ and 30₂ are drawn in the position where the line is at zero potential and, in this case, it is the switch 30₂ which is used.

The outputs of the two switches 30₁ and 30₂ are connected respectively to terminals 3 and 4 of the ring mixer 20 and to terminals 3 and 4 of the ring mixer 21.

The output terminals 7 and 8 of the mixer 20 and of the mixer 21 are connected in parallel through resistors 32₁ and 32₂ on an output line 33 of the block 15.

FIG. 1 represents an output block 34 which contains an amplifier 35 serving as an analog summator of the phase-modulated voltage, which arrives via line 33 and the luminance video signal mixed with the frame and line synchronization pulses which exit from the block 1.

We therefore obtain at the output of block 34 a mixture of frame and line synchros, of a luminance video signal making it possible to obtain a black and white image and of a wave at 4.43 MHz, which is modulated in all or nothing phase by digital information.

This mix is analogous to common PAL or NTSC standard video signals. It can therefore be recorded on commercial video recorders provided for these standards. It can also be transmitted by air or cable by the usual means of transmitting video signals and recorded remotely by a video recorder while black and white images may appear on a video screen.

FIG. 1 represents a block 29 which includes logic circuits and shift registers.

The block 29 includes a pulse divider by two 36 which is a flip-flop whose input is connected to the output 7₁ of the synchro separator 7 and whose output 36₁ delivers pulses, the duration of which is equal to the duration of a line.

The output 36₁ is connected to an input of an AND gate 37, the second input of which is connected to terminal 7₄, which delivers the envelopes of reference bursts.

There is therefore obtained at the output 37₁ of the gate 37, which is connected to the line 31, a reference burst envelope every two lines, which pulse simultaneously controls the two switches 30₁ and 30₂. During this reference burst envelope pulse, the switch 30₁ is closed and it lets pass the wave emitted by the phase shifter 17 which is 90 ° phase shifted with respect to that which leaves the phase shifter 18 and which constitutes the phase reference bursts every other line.

During all the rest of the time, it is the ring phase-shifter 21 which is in service.

Block 29 comprises two shift registers 38 and 39, which have the function of putting the digital information received in parallel on a line in series in the form of bytes on eight lines 40 which are connected in parallel on the respective parallel inputs of the two shift registers. The serial output terminals 38₁ and 39₁ of the two registers are connected to the two inputs of a switch 41, which acts as a logic multiplexer.

The common terminal of the switch 41 is connected to an input terminal of a switch 42 whose second input terminal is connected to the output T1 of the memory 11a which determines the reference edge.

The common terminal of switch 42 is connected to line 28, which controls the switch.

The switch 42 is controlled by the pulses emitted by the output T2 of the memory 11a which emits a pulse which frames the reference edge emitted by the output T1, so that the switch 42 is in the position shown on the FIG. 1 throughout this pulse covering the reference front and letting the reference front pass to the modulator 21 which performs a phase change which is found in the signal leaving the phase shifter 21 and the mixer 35.

At the end of the envelope pulse of the reference edge emitted by the output T2, the switch 42 switches and the pulse trains exiting in series alternately from the outputs 38₁ and 39₁ from one then from the other of the two registers to shifts are sent through the switch 27 on the ring phase shifter 21 which transforms them into phase modulations of the carrier wave at 4.43 MHz.

Block 29 includes a second pulse divider by two 43, which is a flip-flop, an input of which is connected to the output V1 of memory 14, which emits a pulse at the start of each control byte or semi-byte.

The two outputs of opposite polarity Q and Q of the rocker thus emit pulses of opposite direction which alternate with each change of byte or semi-byte.

The output Q is connected to the terminal 39₂ for inhibiting the bit shift clock of the register 39 and it controls the switch 41. It is also connected to an input of an AND gate 44 whose second input is connected to a terminal 45 for loading the bytes into the registers.

The second exit Q of flip-flop 43 is connected to terminal 38₂ for inhibiting the bit shift clock of register 39 and to an input of a second AND gate 46, the second input of which is also connected to the terminal for loading bytes 45.

Finally, the output T3 of the memory 11a is connected to the clock inputs 38₃ and 39₃ of the two shift registers.

The operation is as follows.

The digital information arrives in parallel in the form of bytes on the eight lines 40. They must be serially connected on a line 28 to control the switch 27.

While a byte is loaded in one of the shift registers 38 or 39, the other register is discharged in series by the output 38₁ or 39₁ through the switch 41 which switches at the start of each byte, then through the switch 42 .

Each byte is presented at the parallel input of a register following a byte loading pulse which comes from an external buffer memory and which arrives at input 45 and alternately crosses gate 44 or gate 46, the openings of which are controlled alternately by the outputs Q and Q of scale 43.

The shift clock of the resitres which controls the succession of the pulses in series is constituted by the output T3 of the memory 11a. We have seen that the period of this clock is equal to four periods of the wave at 4.43 MHz.

It can be seen in FIG. 1 that the output V2 of the memory 14, which transmits the loading request pulses of a byte, is connected to a terminal 46 and the output V3, which transmits the loading request pulses of a control half-byte, is connected to a terminal 47. The terminals 46 and 47 are connected to an external unit, for example a buffer memory, to clock the transfer of the bytes and the control half-byte to the input 40 of the shift registers.

When no byte is present on the parallel input 40, the registers offset clocks 38 and 39 continue to set the rate and they take into account the serial input of the registers which is connected to the ground hence modulation in phase with zeros, i.e. no modulation of the carrier wave at 4.43 MHz.

• La ligne 1 représente les synchros lignes sortant sur la borne 7₁.
• La ligne 2 représente les impulsions à la sortie 36₁ de la bascule 36.
• La ligne 3 représente les enveloppes des salves de référence de phase ou "burst" sur la sortie 7₄ du séparateur 7.
• La ligne 4 représente les impulsions à la sortie T2 de la mémoire 11a qui constituent les enveloppes des fronts de référence.
• La ligne 5 représente un front montant à la sortie T1 de la mémoire 11a, qui constitue le front de référence pour chaque ligne.
• La ligne 6 représente les impulsions à la sortie T3 de la mémoire 11a qui servent d'impulsions d'horloge pour le compteur 13 et pour les registres à décalage 38 et 39.
• La ligne 7 représente les impulsions à la sortie V1 de la mémoire 14, qui actionnent la bascule 43 dont les sorties commandent le chargement des octets alternativement dans l'un ou l'autre des deux registres à décalage.
• La ligne 8 représente les impulsions à la sortie Q de la bascule 43.
• La ligne 9 représente les impulsions à la sortie Q de la bascule 43 qui alternent avec les précédentes.
• La ligne 10 représente les trains de huit impulsions sortant en série par la sortie 38₁ du registre à décalage 38.
• La ligne 11 représente les trains de huit impulsions sortant en série de la salve 39₁ du registre à décalage 39 et alternant avec les précédents.
• La ligne 12 représente la succession des trains de huit impulsions en série (octets) sortant de la borne commune du commutateur 41, qui constitue la somme des deux lignes précédentes.
• La ligne 13 représente les trains d'impulsions sortant de la borne commune du commutateur 42 sur la ligne 28 qui correspondent aux impulsions précédentes auxquelles on a ajouté le front de référence (ligne 5).
• La ligne 14 représente les impulsions sortant de la porte ET 37, c'est-à-dire une enveloppe de salve de référence de phase sur deux.
• La ligne 15 représente les impulsions sur la sortie V2 de la mémoire 14, c'est-à-dire les impulsions de demande de chargement de chaque octet dans les registres à décalage.
• La ligne 16 représente les impulsions à la sortie V3 de la mémoire 14, c'est-à-dire les impulsions de demande de chargement des demi-octets de contrôle dans les registres à décalage.

FIG. 3 is a diagram of the pulses present at various points in the circuits of FIG. 1. This diagram represents the time on the abscissa.

• Line 1 represents the synchro lines going out on terminal 7₁.
• Line 2 represents the pulses at the output 36₁ of the flip-flop 36.
• Line 3 represents the envelopes of the phase reference bursts or "burst" on the output 7₄ of the separator 7.
• Line 4 represents the pulses at the output T2 of the memory 11a which constitute the envelopes of the reference edges.
• Line 5 represents a rising edge at the output T1 of the memory 11a, which constitutes the reference edge for each line.
• Line 6 represents the pulses at the output T3 of the memory 11a which serve as clock pulses for the counter 13 and for the shift registers 38 and 39.
• Line 7 represents the pulses at the output V1 of the memory 14, which actuate the flip-flop 43 whose outputs control the loading of the bytes alternately in one or the other of the two shift registers.
• Line 8 represents the pulses at the Q output of flip-flop 43.
• Line 9 represents the pulses at the output Q of flip-flop 43 which alternate with the previous ones.
• Line 10 represents the trains of eight pulses exiting in series by the output 38₁ of the shift register 38.
• Line 11 represents the trains of eight pulses exiting in series from the burst 39₁ of the shift register 39 and alternating with the previous ones.
• Line 12 represents the succession of trains of eight pulses in series (bytes) leaving the common terminal of switch 41, which constitutes the sum of the two preceding lines.
• Line 13 represents the pulse trains leaving the common terminal of switch 42 on line 28 which correspond to the previous pulses to which the reference edge has been added (line 5).
• Line 14 represents the pulses leaving the AND gate 37, that is to say one out of two phase reference burst envelopes.
• Line 15 represents the pulses on the output V2 of the memory 14, that is to say the pulses of request to load each byte in the shift registers.
• Line 16 represents the pulses at the output V3 of the memory 14, that is to say the pulses requesting the loading of the control bytes in the shift registers.

The pulses emitted by the outputs V2 and V3 are sent to external buffer memories, in which the bytes of digital values and the control bytes are recorded and these pulses control the transfer of the successive bytes to the parallel input 40.

The operation of a device according to FIG. 1 is summarized below. It is used to place binary pulses representing digital values on a video subcarrier by modulating all or nothing the phase of this subcarrier, this which has the effect that the digital values are supported by an analog signal which can be transmitted remotely and / or recorded by well-known devices for transmitting or recording analog video signals.

Block 15 contains the essential circuits. The subcarrier wave is created by the oscillator 12.

In the preferred example described, this carrier wave has a frequency of 4.43 MHz, which corresponds to the usual frequency of the subcarrier of the chrominance signals, which has the advantage that we can then mix in the block 34 this carrier wave has luminance signals and synchronization pulses for simultaneously transporting and / or recording a black and white video image and digital data. It is specified that this preferential example is not limiting and one can modulate another video carrier wave with digital information, in the case where the frequency of the subcarrier of the chrominance signals would be different from 4.43 MHz. As this carrier wave has a very high frequency, of the order of MHz, it makes it possible to transport a large bit rate of digital information.

The digital information enters block 15 via line 28 and it is sent to the intermediate terminals 3 and 4 of a phase modulator 21. The carrier wave is connected to one of the inputs of the phase modulator 21 and it is collected from the output of said modulator a wave modulated in phase by all or nothing by the digital information, that is to say not phase shifted when the modulator receives a binary signal at level 0 and phase shifted by 180 ° when the modulator receives a binary signal at level 1. The duration of the binary pulses is a multiple of the period of the subcarrier wave, for example the cycle of the binary pulses which appears on line 6 of FIG. 3 is equal to four periods of the carrier wave.

The second ring mixer 20 represented in FIG. 1 is an accessory component which is used only to let pass for a few periods the subcarrier wave offset by 90 ° for serve as a phase reference in the PAL standard.

Block 1 in FIG. 1 represents an exemplary embodiment making it possible to use either an external video feed to extract the synchronization pulses therefrom and, at the same time, keep the luminance signals, or a video generator which creates synchronization pulses and a uniform luminance signal.

Block 8 corresponds to counters and memories which make it possible to generate the timing pulses of the modulation operations.

The counter 9 memory unit 10 determines the lines of each frame which support digital information by eliminating a few lines at the start and end of the frame, for which the subcarrier wave could be disturbed.

The counter 11 memory unit 11a receives the subcarrier wave emitted by the oscillator 12, which serves as a clock signal and it emits a rising edge T1 represented on line 2 of the diagram, which serves as the origin of the times. on each line for the precise positioning of the digital information on this line. It also emits on output T3 pulses whose duration is equal to four periods of the carrier wave which are used to convey the digital information.

The counter 13 memory unit 14, is controlled by the pulses T3 and is used to transmit on the outputs V1, V2, V3 the pulses represented respectively on lines 7, 15 and 16 of the diagram which control the start of the bytes of digital information presented in series.

Block 29 essentially contains two shift registers which make it possible to present the digital information arriving in parallel on eight lines in series and to present them at the desired times so that they are written on the lines and on the portions of lines selected by the block circuits 8.

FIG. 4 is a general diagram in the form of a block diagram of a preferred embodiment of the reading circuits according to the invention, that is to say circuits which make it possible to separate the carrier wave of digital information from the others video signals recorded or transmitted remotely at the output of a device according to FIG. 1 and which make it possible to extract from the wave modulated in phase the digital information it supports.

Video signals from a VCR or video link enter the device through terminal 50, located at the top left.

These signals are sent in parallel to a suppressor filter 51 which eliminates the signals having a frequency of 4.43 MHz.

The output of the filter 51 is connected to an amplifier 52, the output of which is connected to a television set or to a video monitor, which reproduces the black and white image possibly contained in the received signals.

The signals received are also sent to a composite sync extractor 53, then to a device for regenerating and separating the synchronization pulses 54, which has four outputs. The output 54₁ transmits the line synchros. The output 54 sortie transmits the frame synchros. The output 54₃ emits a logic signal at level 0 for even blood frames and at level 1 for odd rank frames. The output 54₄ delivers pulses envelope of bursts of reference of phase (burst). The circuits 53 and 54 are identical to the circuits 3 and 7 of FIG. 1 and the outputs 54₁ to 54₄ fulfill the same functions as the outputs 7₁ to 7₄.

The device according to FIG. 4 comprises a pulse counter assembly 55, associated with a memory 55a which fulfill the same functions as the assembly 9 and 10 in FIG. 1. The memory 55a comprises an output 51 which emits a signal at the level 1 during the lines of each frame which are not used to support the digital information and a signal at level 0 during the lines used.

The device according to FIG. 4 comprises a second assembly composed of a pulse counter 56 associated with a memory 56a which are analogous to the counter 11 attached to the memory 11a and which fulfill substantially the same functions.

The clock input of counter 56 receives pulses at a frequency of 4.43 MHz, which are brought up to standard TTL (0 - 5V) by a comparator amplifier 57 connected to the output 58₄ of a regenerator of l reference wave 58.

Memory 56a has two outputs.

The M2 output is programmed to deliver a clock signal for the next counter, which also serves as a clock signal for the shift registers.

The output M1 of the memory 56a is programmed to emit pulses intended to reset the clock signals emitted by the output M2, in phase with the reference edges which are mixed with the digital information.

The principle is as follows.

The counter 56 is reset to zero by each line sync and it counts the pulses at 4.43 MHz frequency. The reference edge is extracted from digital information and set to TTL level by a comparator 59, the output of which is connected to an input of a NAND gate 60. The output M1 of the memory is programmed to send a pulse (window) between two determined pulses of the 4.43 MHz wave, for example between the 14th and the 23rd pulse, values between which the reference edge lies.

The pulse emitted by the output M1 is inverted by an inverter 61 and sent to the second input of the AND gate 60, at the output of which a new pulse is obtained having a falling edge which coincides with the start of the window and a rising edge which coincides with the reference edge. This pulse is sent directly to an input of a second AND gate 62. It is also sent, through an inverter 63, to a delay circuit 64 of the RC type which delays the falling edge and the output of which is connected to the second input. of the AND gate 62, so that a narrow pulse which coincides with the reference edge is obtained at the output of the gate 62. The output of door 62 is connected to the charging terminal of the counter 56.

It can be seen in FIG. 4 that the output M1 of the memory 56a is looped back to a stage of the address counter 56 which is, for example the 6th stage corresponding to the binary number 32, which is located beyond the end of the window .

After having received the loading pulse sent by gate 62, counter 56 will therefore count addresses from 32, which coincides with the reference edge.

We know that the first bit of digital data starts for example after eight half-waves of the 4.43 MHz clock, counted from the reference edge and lasts four alternations. The output M2, which emits the sampling signals of the shift registers, is programmed for example to emit the first 10-wave signal after the reference edge and from there, it emits a number of bits whose duration is equal to four alternations of the signal at 4.43 MHz and the number of which corresponds to the number of digital information bytes per line plus half a control byte, for example, 52 bits for records comprising six bytes per line and half a byte control.

The device shown in FIG. 4 further comprises an assembly composed of a third binary counter 65 acting as an address counter for a memory 65a, the nature and function of which are the same as those of the associated counter 13 in memory 14.

The clock pulses of the counter 65 are the pulses emitted by the output M2 of the memory 56a.

The memory 65a has a first output M1 which delivers a pulse every eight clock pulses.

The output M1 is connected to an input of a bi-stable flip-flop 66, which fulfills the same function as the flip-flop 43 of FIG. 1 and that the two outputs alternately control the authorization and the inhibition of the shift clock of the two shift registers 67 and 68, which receive the digital information in series and which deliver it in parallel on eight output lines 69.

The output M2 of the memory 65a emits pulses for loading the digital information leaving the shift registers in the input interface of a computer intended to process this information.

The input terminal 50 is connected through an amplifier 70 to a filter 71 with narrow bandwidth, tuned to 4.43 MHz, so that it lets through only the carrier wave at 4.43 MHz, frequency modulated by digital information and phase reference bursts. the output of the filter 71 is connected to a limiting amplifier 72, the output of which is connected to an input 58₁ of a frequency regenerator 58, stabilized by a quartz at 4.43 MHz.

A second input 58₂ of the regenerator 58 is connected on terminal 54₄ of memory 54, which sends envelope pulses of phase reference bursts.

Circuit 58 has two outputs 58₃ and 58₄. The operation of circuit 58 is as follows. While it receives on input 58₂ an envelope pulse of a reference burst, input 58₁ receives said reference burst. At this time the circuit operates as an amplifier and emits on its output 58₃ a wave which is in phase with the phase reference wave. When the envelope pulse of the phase reference arriving at terminal 58₂ ceases, circuit 58 continues to operate as an oscillator and to transmit on output 58₃ a reference wave at 4.43 MHz, the phase of which changes from 90 ° to each line in the PAL standard.

The output 58₄ of circuit 58 emits no wave during the pulses received on terminal 58 la and it transmits the phase modulated signal received on input 58₁ during the rest of the time. Circuit 58 is a known circuit, for example an integrated circuit sold by RCA under the reference CA-3128Q.

The device according to FIG. 4 comprises a phase demodulator 70 which is preferably identical to the ring mixer shown in FIG. 2 and to the phase modulators 20 and 21 of FIG. 1.

The input terminals 1 and 2 of the demodulator 70 are connected between the earth and the terminal 58₃ and therefore receive an unmodulated reference voltage.

The output terminals 7 and 8 of the demodulator 70 are connected one to the earth and the other to the terminal 58₄ of the circuit 58 and they therefore receive a voltage of 4.43 MHz out of phase with the reference voltage at 0 ° or 180 ° by digital information.

Terminal 3 of the modulator is connected to earth and terminal 4 is connected to output terminal 70₁ on which DC voltage pulses appear at zero level when the phase shift is zero, and at level 1 when the phase shift is 180 °. The output terminal 70₁ is connected to a filter 71 intended to suppress the residual harmonics of the voltage at 4.43 MHz. The output of the filter 71 is connected to an operational amplifier 59 mounted as a comparator, which has the function of bringing the pulses to the TTL standard (0-5V).

The binary pulses emitted by the comparator 59 are sent in parallel to the serial inputs of the two shift registers 67 and 68. These pulses also include the reference edge which precedes on each line the digital information and the output of the comparator 59 is connected to an entry from the NAND gate 60, as explained above.

• La ligne 1 représente les impulsions de synchronisation lignes à la sortie 54₁.
• La ligne 2 représente, sur une ligne vidéo, les positions de l'enveloppe de la salve de référence, du front de référence, de six octets d'information numérique et d'un demi octet de contrôle.
• La ligne 3 représente par une flèche le front montant qui constitue le front de référence.
• La ligne 4 représente les impulsions très étroites émises par la porte NON ET 62.
• La ligne 5 représente les impulsions d'horloge des registres à décalage émises par la sortie M2 de la mémoire 56a.
• La ligne 6 représente les impulsions de début d'octet émises par la sortie N1 de la mémoire 65a.
• Les lignes 7 et 8 représentent les impulsions de polarité émises respectivement par les sorties Q et Q de la bascule 66.
• La ligne 9 représente l'apparition des octets ou du demi octet de contrôle sur les sorties en parallèle 69.
• La ligne 10 représente les impulsions émises par la sortie N2 de la mémoire 65a pour commander le transfert des octets dans un calculateur.
• La figure 6 représente une vue d'ensemble en perspective d'une installation selon l'invention pour enregistrer sur un magnétoscope des images vidéo en noir et blanc et des informations numériques mesurées pendant les prises de vues et pour relire ultérieurement ces informations numériques et les traiter sur un calculateur.

FIG. 5 is a timing diagram which represents time on the abscissa and which represents the pulses at various points of the circuits of FIG. 4, during the lines used to support digital information.

• Line 1 represents the line synchronization pulses at output 54₁.
• Line 2 represents, on a video line, the positions of the envelope of the reference burst, the reference edge, six bytes of digital information and half a control byte.
• Line 3 represents by an arrow the rising edge which constitutes the reference front.
• Line 4 represents the very narrow pulses emitted by the NAND gate 62.
• Line 5 represents the clock pulses of the shift registers emitted by the output M2 of the memory 56a.
• Line 6 represents the start of byte pulses emitted by the output N1 of the memory 65a.
• Lines 7 and 8 represent the polarity pulses emitted by outputs Q and Q of scale 66.
• Line 9 represents the appearance of the control bytes or half byte on the parallel outputs 69.
• Line 10 represents the pulses emitted by the output N2 of the memory 65a to control the transfer of the bytes in a computer.
• FIG. 6 represents an overall perspective view of an installation according to the invention for recording on a video recorder black and white video images and digital information measured during the shots and for re-reading this digital information and the process on a calculator.

FIG. 1 represents a commercial video recorder 72, which is PAL standard, for example a video recorder sold by the firm SONY, under the brand "U-MATIC" which uses tapes allowing one hour of recording and which constitutes in the present application a peripheral memory which can contain 2.5 Giga bytes of digital information. The tapes simultaneously record the synchronization pulses, the luminance video signals which make it possible to reproduce a black and white image and a wave having the frequency of 4.43 MHz, which usually corresponds to the chrominance signals, but which is modulated, in the present case, by digital information.

The video recorder 72 has a video input 72₁ and a video output 72₂.

The installation comprises a box 73 containing printed circuit boards carrying the components and the circuits represented in FIGS. 1 and 4.

The digital information comes from a bus that connects a local computer to various measuring devices. They arrive at the housing 73 generally in parallel by one or more lines 74. The reference 75 represents the output line of the video signals from a camera 75a in black and white or in color. The reference 76 represents a video monitor which receives the video signals and which displays a black and white video image which makes it possible to control the recording operations and possibly to select the sequences to be recorded and which also makes it possible to reproduce the images in black and blank recorded in the VCR.

The video input 72₁ of the video recorder is connected by a line 77₁ to the output of the box 73 to transmit to the video recorder the signals leaving the mixer 35 of FIG. 1.

The video output 72₂ of the video recorder is connected to the input terminal 50 of the circuits of FIG. 4.

FIG. 6 represents, in addition, a mini-computer 78 provided with a keyboard 79, which is connected by a ribbon cable 80 of lines in parallel to the output 69 of FIG. 4, so that it can receive the digital information stored in the mass peripheral memory made up by the video recorder and process these in deferred time.

FIG. 6 illustrates a possible application of the methods and devices according to the invention, which make it possible to use a commercial video recorder to store in real time a large number of digital information transmitted by numerous sensors and for further processing of this information.

An installation according to FIG. 6 makes it possible to record digital information and black and white video images at the same time and to keep in memory the time relationship between the images and the measurements. It also makes it possible to reproduce in black and white the stored images at the same time as the digital values are extracted from the memory.

The methods and devices according to the invention make it possible to use commercial video recorders 72 as peripheral mass memory of a mini-computer 78.

The device which is shown in FIGS. 1 and 4 makes it possible to simultaneously record and transport a black and white image and digital information which take the place of the chrominance signals.

Alternatively, if the bit rate of the digital information is lower, this information can be placed in the form of phase modulation on only certain lines and the chrominance signal is preserved on the majority of the lines in order to record or transmit to the both a color image and numeric values.

Claims (13)

1. Method for recording and / or transmitting a large bit rate of binary signals remotely using known means for recording and / or transmitting video signals, characterized by the following operations:
- a carrier wave is generated having a frequency equal to that of a carrier wave of analog video chrominance signals;
- said carrier wave is modulated in phase at 0 ° or 180 ° by said binary signals by means of a phase modulator (21);
- the modulated wave is mixed with video synchronization pulses and with phase reference bursts and the signals obtained can be recorded on a video recorder in PAL or NTSC standard and / or transmitted remotely. 2. Method for reading digital information coming from a video recorder, an antenna or an emptied cable, in the form of a video carrier wave modulated in phase and mixed with synchronization pulses and reference bursts phase by a method according to claim 1, characterized by the following operations:
- isolating said carrier wave modulated in phase by means of a bandpass filter (71);
- Generating pulses surrounding said reference bursts are generated by means of a pulse separator circuit (54);
- sending said phase-modulated carrier wave and said pulses envelopes phase reference bursts, on two inputs of a circuit which continuously transmits a reference wave in phase with said phase reference bursts and which allows said wave to pass modulated in phase.
- sending said reference wave on an input of a phase demodulator circuit and said phase modulated wave on another input of said phase demodulator circuit (70);
- And we collect at the output of said phase demodulator circuit, pulses which reproduce the binary signals representing said digital information. 3. Method according to claim 1 for recording and / or for transmitting both a high bit rate of binary signals representing digital information and black and white video images using known means of recording. and / or empty signal transmission, characterized by the following operations:
the video signals are filtered by means of a plug filter which stops the carrier wave modulated by the chrominance signals having a frequency of 4.43 MHz and which lets the luminance signals and the synchronization pulses pass;
- a carrier wave is generated having a frequency of 4.43 MHz;
- said carrier wave is modulated in phase at 0 ° or 180 ° by said binary signals by means of a phase modulator (21);
- and the luminance video signal, the synchronization pulses, said phase-modulated 4.43 MHz wave and the phase reference bursts are mixed, so that video signals are obtained which can be recorded on a video recorder and / or transmitted remotely via a video channel and which make it possible to obtain both black and white images and digital data. 4. Method according to any one of claims 1 and 3, characterized in that a certain number of lines are determined at the start and at the end of each video frame which do not support any digital information in order to avoid phase disturbances due to switching of the playback heads of the video recorders. 5. Method according to claim 4, characterized in that one creates at the start of each of the lines carrying digital information, a reference edge which precedes the first binary signal by a well-defined duration and which is transmitted and / or recorded as a binary signal. 6. Device for recording and / or for remotely transmitting a large bit rate of binary signals using known means for recording and / or transmission of video signals, characterized in that it comprises an oscillator (12) stabilized by a quartz which emits a wave having a frequency equal to that of the carrier wave of the chrominance signals and a phase modulator (21) which receives said carrier wave on one of its inputs, which receives said binary signals on its control terminal and which delivers, on its output, said non-phase shifted carrier wave while said binary signal is at zero level and 180 ° phase shifted, while said binary signal is at level 1, a video synchronization pulse generator and a mixer which receives said video synchronization pulses and said phase modulated carrier wave which mixes them. 7. Device for reading digital information coming from a video recorder, antenna or video cable, in the form of a carrier wave modulated in phase by binary signals and mixed with synchronization pulses and phase reference bursts, characterized in that it comprises a bandpass filter (71) tuned to the frequency of said carrier wave which allows the latter and said phase reference bursts to pass; a synchronous extractor (53) associated with a synchronous separator (54), which emits on an output (54a) envelope pulses of said reference bursts; a reference regenerator (58) which has two inputs, an input (58₁), connected to the output of said filter and an input (58₂) connected to said output (54₄) of said sync separator, and which has two outputs, a first output (58₃), which delivers a reference wave in phase with said phase reference bursts and a second output (58₄) which delivers said phase modulated wave and a phase demodulator (70) including the phase reference input is connected to said first output (58₃), whose modulated wave input is connected to said second output (58₄) and whose output delivers pulses which constitute said binary signals. 8. Device according to claim 6, characterized in that it comprises a regenerative circuit and synchronization pulse separator (7) which has a first output (7₁) which delivers the line synchronization pulses and a second output (7₂) which delivers the frame synchronization pulses and it comprises an assembly constituted by a first pulse counter (9) associated with a memory (10), for which it acts as an address counter and the clock input of said counter is connected to said first output (7₁), while the reset terminal of said counter is connected to said second output (T2) and said memory is programmed to transmit on an output (S1) a zero level signal during that the counter calls the addresses corresponding to a determined number of lines located at the beginning and at the end of each frame. 9. Device according to claim 8, characterized in that it comprises a second assembly constituted by a second memory (11a) and by its address counter (11) and the clock input of said address counter (11) is connected to the output of said oscillator (12), the reset terminal of said counter (11 ) is connected to said first output (7₁) of the synchro separator (7) and said memory has three outputs, an output T1 which emits a pulse which determines on each line a reference edge, an output (T2) which emits a pulse envelope of the reference front and an output (T3) which emits a clock signal, the period of which is equal to a multiple of the period of said carrier wave. 10. Device according to claim 9, characterized in that it comprises a third memory (14) associated with an address counter (13) whose clock input is connected to said third output (T3) of the second memory and of which the reset terminal is connected to the output (7₁) of said sync splitter and said memory has three outputs: a first output (V1), which emits byte start signals on each line, a second output (V2) which sends byte request pulses and a third output (V3) which sends request pulses of a control byte located at the end of each line. 11. Device according to any one of claims 6 and 8 to 10, characterized in that it comprises two shift registers (38, 39), whose clock inputs are connected to said output (T3) which are intended alternately receiving the binary signals arriving in parallel on several lines (40) and putting them in series to send them in series to the intermediate terminals of said phase modulator (21). 12. Device according to claim 7, characterized in that it comprises two shift registers (67, 68) which alternately receive the binary signals leaving in series from said phase demodulator (70) and which deliver them in parallel on several lines of exit (69). 13. New application of a PAL or NTSC standard VCR, characterized in that said VCR is used to record a wave having the frequency of a chrominance signal carrier wave modulated in phase by digital information and serves as a memory for peripheral mass of a mini-computer.

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