EP0360527A3 - Parallel computer system using a simd method - Google Patents

Parallel computer system using a simd method Download PDF

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Publication number
EP0360527A3
EP0360527A3 EP19890309445 EP89309445A EP0360527A3 EP 0360527 A3 EP0360527 A3 EP 0360527A3 EP 19890309445 EP19890309445 EP 19890309445 EP 89309445 A EP89309445 A EP 89309445A EP 0360527 A3 EP0360527 A3 EP 0360527A3
Authority
EP
European Patent Office
Prior art keywords
controller
data
processor elements
computer system
parallel computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19890309445
Other languages
German (de)
French (fr)
Other versions
EP0360527B1 (en
EP0360527A2 (en
Inventor
Tatsuya Shindo
Kaoru Kawamura
Masanobu Umeda
Toshiyuki Shibuya
Hideki Miwatari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63234546A external-priority patent/JP2518902B2/en
Priority claimed from JP63234545A external-priority patent/JPH0814816B2/en
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to EP94104303A priority Critical patent/EP0605401B1/en
Publication of EP0360527A2 publication Critical patent/EP0360527A2/en
Publication of EP0360527A3 publication Critical patent/EP0360527A3/en
Application granted granted Critical
Publication of EP0360527B1 publication Critical patent/EP0360527B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Abstract

A parallel computer system using a SIMD method, which in one aspect is constituted by a controller (10) and a plurality of processor elements (14), each of the processor elements has a storage unit to store data to be processed, the controller controls operation of the processor elements, and the parallel computer system performs processing of the data based on a calculation control signal transmitted from the controller (10). The parallel computer system further comprises: a data collection unit (13) connected between the processor elements and the controller (10) for receiving output data from the processor elements (14), performing a predetermined calculation, and outputting calculated data to the controller; and a calculation control unit (15) connected between the data collection unit (13) and the controller (10) for transmitting the calculation control signal from the controller to the data collection unit (13) to make it possible to perform the predetermined calculation in the data collection circuit.
In another aspect (Fig. 10), the parallel computer system comprises: a controller (10), a plurality of control groups (G1...G4), each of the control groups being constituted by a number of processor elements divided from a plurality of the processor elements (14), for use as an address control unit; a plurality of scheduling circuits (110), each of the scheduling circuits provided for one of the control groups (G1...G4) and operatively connected to the controller (10), and for receiving and managing an event signal designating an address signal for data to be processed and transmitted from an adjacent control group; and a plurality of real address generation circuits (120), each of the real address generation circuits provided for one of the control groups (G1...G4) and connected between the controller (10), the scheduling circuit (110), and the control group, for generating an address signal for data to be processed by the processor element (14) belonging to the control group based on a base address determined by the event signal to be managed by the scheduling circuit (110), and an address signal applied from the controller (10).
EP89309445A 1988-09-19 1989-09-18 Parallel computer system using a SIMD method Expired - Lifetime EP0360527B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP94104303A EP0605401B1 (en) 1988-09-19 1989-09-18 Parallel computer system using a SIMD method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP234545/88 1988-09-19
JP234546/88 1988-09-19
JP63234546A JP2518902B2 (en) 1988-09-19 1988-09-19 Event scheduling processing method for parallel computers
JP63234545A JPH0814816B2 (en) 1988-09-19 1988-09-19 Parallel computer

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP94104303A Division EP0605401B1 (en) 1988-09-19 1989-09-18 Parallel computer system using a SIMD method
EP94104303.6 Division-Into 1989-09-18

Publications (3)

Publication Number Publication Date
EP0360527A2 EP0360527A2 (en) 1990-03-28
EP0360527A3 true EP0360527A3 (en) 1991-01-16
EP0360527B1 EP0360527B1 (en) 1995-01-04

Family

ID=26531623

Family Applications (2)

Application Number Title Priority Date Filing Date
EP94104303A Expired - Lifetime EP0605401B1 (en) 1988-09-19 1989-09-18 Parallel computer system using a SIMD method
EP89309445A Expired - Lifetime EP0360527B1 (en) 1988-09-19 1989-09-18 Parallel computer system using a SIMD method

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP94104303A Expired - Lifetime EP0605401B1 (en) 1988-09-19 1989-09-18 Parallel computer system using a SIMD method

Country Status (3)

Country Link
US (2) US5230057A (en)
EP (2) EP0605401B1 (en)
DE (1) DE68920388T2 (en)

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US7155708B2 (en) * 2002-10-31 2006-12-26 Src Computers, Inc. Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
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Also Published As

Publication number Publication date
US5230057A (en) 1993-07-20
EP0605401B1 (en) 1998-04-22
EP0360527B1 (en) 1995-01-04
EP0605401A2 (en) 1994-07-06
DE68920388T2 (en) 1995-05-11
USRE36954E (en) 2000-11-14
EP0360527A2 (en) 1990-03-28
DE68920388D1 (en) 1995-02-16
EP0605401A3 (en) 1994-09-28

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