EP0455977A3 - - Google Patents

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Publication number
EP0455977A3
EP0455977A3 EP91104684A EP91104684A EP0455977A3 EP 0455977 A3 EP0455977 A3 EP 0455977A3 EP 91104684 A EP91104684 A EP 91104684A EP 91104684 A EP91104684 A EP 91104684A EP 0455977 A3 EP0455977 A3 EP 0455977A3
Authority
EP
European Patent Office
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91104684A
Other versions
EP0455977B1 (en
EP0455977A2 (en
Inventor
Kazuhiro Nakada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Publication of EP0455977A2 publication Critical patent/EP0455977A2/en
Publication of EP0455977A3 publication Critical patent/EP0455977A3/xx
Application granted granted Critical
Publication of EP0455977B1 publication Critical patent/EP0455977B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
EP91104684A 1990-03-30 1991-03-25 Semiconductor memory device having diagnostic unit operable on parallel data bits Expired - Lifetime EP0455977B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2084006A JP2953737B2 (ja) 1990-03-30 1990-03-30 複数ビット並列テスト回路を具備する半導体メモリ
JP84006/90 1990-03-30

Publications (3)

Publication Number Publication Date
EP0455977A2 EP0455977A2 (en) 1991-11-13
EP0455977A3 true EP0455977A3 (xx) 1995-02-08
EP0455977B1 EP0455977B1 (en) 1997-01-02

Family

ID=13818522

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91104684A Expired - Lifetime EP0455977B1 (en) 1990-03-30 1991-03-25 Semiconductor memory device having diagnostic unit operable on parallel data bits

Country Status (4)

Country Link
US (1) US5079747A (xx)
EP (1) EP0455977B1 (xx)
JP (1) JP2953737B2 (xx)
DE (1) DE69123875T2 (xx)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2549209B2 (ja) * 1991-01-23 1996-10-30 株式会社東芝 半導体記憶装置
KR950001293B1 (ko) * 1992-04-22 1995-02-15 삼성전자주식회사 반도체 메모리칩의 병렬테스트 회로
US5377144A (en) * 1993-07-27 1994-12-27 Texas Instruments Inc. Memory array reconfiguration for testing
KR0168896B1 (ko) * 1993-09-20 1999-02-01 세키자와 다다시 패리티에 의해 에러를 수정할 수 있는 반도체 메모리장치
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
JPH08203278A (ja) * 1995-01-25 1996-08-09 Sony Corp 半導体メモリ
JP2746222B2 (ja) * 1995-08-31 1998-05-06 日本電気株式会社 半導体記憶装置
JP4503142B2 (ja) * 2000-06-14 2010-07-14 株式会社ルネサステクノロジ 半導体記憶装置
JP2004234770A (ja) * 2003-01-31 2004-08-19 Renesas Technology Corp 半導体記憶装置とテスト方法
KR100639614B1 (ko) * 2004-10-15 2006-10-30 주식회사 하이닉스반도체 뱅크 내 셀을 테스트하기 위한 데이터 출력 컴프레스 회로및 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0026602A1 (en) * 1979-09-27 1981-04-08 Communications Satellite Corporation A method of writing into and reading from the memory of a buffer memory system and a buffer memory system using such a method
EP0385704A2 (en) * 1989-02-27 1990-09-05 Nec Corporation Semiconductor memory device having output data buffer unit shared between usual access mode and test mode of operation
EP0410464A2 (en) * 1989-07-27 1991-01-30 Nec Corporation Semiconductor memory device having diagnostic circuit for memory cells

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2523586B2 (ja) * 1987-02-27 1996-08-14 株式会社日立製作所 半導体記憶装置
US4967394A (en) * 1987-09-09 1990-10-30 Kabushiki Kaisha Toshiba Semiconductor memory device having a test cell array

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0026602A1 (en) * 1979-09-27 1981-04-08 Communications Satellite Corporation A method of writing into and reading from the memory of a buffer memory system and a buffer memory system using such a method
EP0385704A2 (en) * 1989-02-27 1990-09-05 Nec Corporation Semiconductor memory device having output data buffer unit shared between usual access mode and test mode of operation
EP0410464A2 (en) * 1989-07-27 1991-01-30 Nec Corporation Semiconductor memory device having diagnostic circuit for memory cells

Also Published As

Publication number Publication date
JP2953737B2 (ja) 1999-09-27
EP0455977B1 (en) 1997-01-02
JPH03283199A (ja) 1991-12-13
DE69123875D1 (de) 1997-02-13
US5079747A (en) 1992-01-07
EP0455977A2 (en) 1991-11-13
DE69123875T2 (de) 1997-06-26

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