EP0464778A1 - Franking machine comprising a specific printed circuit constituting interfaces - Google Patents

Abstract

The invention relates to a postal franking machine, printing stamps while computing the values of these stamps, and comprising: - a motor (27) and rollers carrying figures in relief for printing a stamp; - a microprocessor (16) for controlling the motor, and for computing the value of each stamp; - coders (21 to 24) for translating into the form of binary words the values of the figures of the stamp printed; and the states of manual control switches (SW'1 to SW'4); - interfaces constituted essentially by an application-specific integrated circuit (ASIC) (25) comprising means for receiving and executing a start control signal for the motor (27); or a stop control signal for the motor; or a single signal triggering a scan and transmission of the values translated by all the coders (21 to 24) and of the states of all the switches (SW'1 to SW'4). <IMAGE>

Description

The invention relates to a franking machine, printing stamps by counting the values of these stamps.

• - un moteur et des mollettes portant des chiffres en relief, pour imprimer un timbre;
• - un microprocesseur pour commander le moteur, et pour comptabiliser la valeur de chaque timbre imprimé;
• - des codeurs de position, reliés respectivement aux mollettes pour traduire sous forme de mots binaires les valeurs des chiffres des timbres imprimés;
• - plusieurs interrupteurs de commande manuelle;
• - une première interface commandée par des ordres du microprocesseur pour scruter et pour transmettre au microprocesseur les valeurs traduites par les codeurs, et les états des interrupteurs;
• - une seconde interface commandées par des ordres du microprocesseur pour commuter l'alimentation du moteur.

Conventionally, such a machine comprises:

• - an engine and knobs with raised figures, for printing a stamp;
• - a microprocessor to control the motor, and to record the value of each stamp printed;
• - position encoders, connected respectively to the knobs to translate into binary words the values of the numbers of the stamps printed;
• - several manual control switches;
• a first interface controlled by orders from the microprocessor for scanning and for transmitting to the microprocessor the values translated by the encoders, and the states of the switches;
• - a second interface controlled by orders from the microprocessor to switch the power supply to the motor.

It is known to distribute these sub-assemblies on two printed circuit boards. A so-called main card notably includes the microprocessor and a first part of the second interface. A so-called interface card comprises: the first interface, the position encoders, the switches, and a second part of the second interface. The two cards are connected by connectors with five contacts corresponding respectively to: a conductor for the reference potential, a conductor for the supply voltage of the electronic circuits, a specialized conductor for a motor control signal, and two conductors constituting a serial transmission bus, according to the 12C protocol for example. The microprocessor is the master of transactions between the two cards. One bus conductor transmits clock pulses clocking the transmission, while the other conductor transmits binary data, in either direction. This bus transmits the commands controlling the scanning and the transmission of the values translated by the encoders, and of the states of the switches; and transmits data in response to these orders.

The first interface has two general purpose integrated circuits available commercially: a serial input-output circuit, and a decoder. These circuits make it possible to scan a matrix of conductors in which the encoders and the switches establish variable connections between rows and columns. The lack of available outputs on these circuits leads to the use in addition of twelve diodes, to connect six outputs of the decoder to the twelve columns of the matrix without harming the independence of these columns.

The second interface, which switches the power supply to the motor, comprises: an address decoder and a locking register, located on the main card; and comprises: a power transistor and a preamplifier transistor, located on the interface card. The specialized driver for motor control routes a direct voltage, supplied by an output of the latching register and directly controlling the preamplifier transistor. An exemplary embodiment of an interface card of a machine according to the prior art will be described in more detail in the following.

The interface card of a machine according to the prior art has the advantage of comprising only integrated circuits for general use, commercially available. Their number is small (two) but it is desirable to reduce it to reduce the cost of manufacturing the machine (cost of the printed circuit, assembly, control). It is not possible to reduce the number of integrated circuits by using a single integrated circuit which is commercially available, since there is no general-purpose integrated circuit which can fulfill all the functions of the first interface and, a fortiori, fulfill part or all of the functions of the second interface. We must therefore consider the realization of an integrated circuit specific to this application (ASIC). It is possible to integrate into a single integrated circuit: the twelve diodes, the serial input-output circuit, and a decoder. The new machine would then have the same performance and the same drawbacks as the machine according to the prior art, except that the bulk and the cost would be reduced.

The machine according to the prior art has the following drawbacks. To scan the value translated by each encoder, it is necessary to send, from the microprocessor to the input-output circuit, a write order consisting essentially of two bytes; then send, from the microprocessor to the input-output circuit, a read order consisting essentially of a byte; and finally, to send, from the input-output circuit to the microprocessor, a byte of data. There is therefore transmission, in one direction or the other, of four bytes to examine the state of a single encoder. In addition, each order sent by the microprocessor is preceded by a signal characteristic of the start of a transaction, and it is followed by a signal characteristic of an end of transaction.

Scanning four encoders requires four scans triggered by four orders from the microprocessor.

The manual control switches constitute two groups, separated from the encoders, and which are the subject of a fifth and a sixth scan, and of the transmission of a fifth and a sixth byte of data. Finally, the scrutiny of all the encoders and switches is followed by putting all the columns of the matrix to rest, consisting in configuring the input-output circuit by a write order such that none of the columns of the matrix is only scanned by the decoder. In total, to scan four encoders and four switches, twenty six bytes are transmitted on the data conductor.

To eliminate the rebound effect of switch and encoder contacts, a scan is commanded every 10 milliseconds. In an exemplary embodiment where the minimum admissible period for the clock of the bus clocking the transmission, is 10 microseconds, the minimum duration necessary to scan four switches and four encoders is 2.5 milliseconds. The microprocessor therefore devotes a quarter of its operating time to carrying out this scan. On the other hand, a non-negligible current flows in the columns of the matrix corresponding to an encoder, during the scanning of the latter. Consequently, the duration of all the scans has a direct effect on the amount of energy taken from the power supply device of the electronic circuits of the machine. Incidentally, this scanning mode requires storing a relatively complex program in the microprocessor program memory.

The machine according to the prior art also has a drawback arising from the lack of outputs on the decoder. The use of diodes to connect the columns of the matrix to the outputs of the decoder, has the effect of reducing by 0.7 volt the noise immunity of the ports of the input-output circuit, when they are configured as inputs .

The fact of transmitting by two different processes the orders controlling the motor and the orders controlling the scanning leads to adding a specialized conductor to connect the two cards of the machine, which increases by one the number of contacts of the connectors connecting the two cards. In addition, the main card has a space requirement and a cost increased by the presence of the address decoder and the locking register forming part of the second interface.

Finally, the machine according to the prior art has a drawback arising from the lack of inputs on the input-output circuit. This lack of entries leads to limiting the number of rows in the matrix to five. As each coder constitutes a sub-matrix comprising five lines, all the lines of the matrix are occupied when a coder is scanned. Consequently, the switches are grouped into two groups, independent of the encoders. The states of the switches are transmitted in two bytes distinct from the four bytes transmitting the values translated by the four encoders. There is therefore a transmission of six data bytes which each contain a maximum of four useful bits and stuffing bits. This poor filling of the data bytes contributes to increasing the transactions between the interface card and the main card, by increasing the number of data bytes.

The object of the invention is to provide a franking machine whose input-output interface card comprises a single integrated circuit, specific to this application; and which does not have the disadvantages of the machine according to the prior art.

• - un moteur et des molettes portant des chiffres en relief, pour imprimer un timbre ;
• - un microprocesseur pour commander le moteur, et pour comptabiliser la valeur de chaque timbre imprimé;
• - des codeurs de position reliés respectivement aux molettes pour traduire sous forme de mots binaires les valeurs des chiffres du timbre imprimé;
• - des interrupteurs de commande manuelle;
• - une première interface, commandé par des ordres du microprocesseur, pour scruter et pour transmettre au microprocesseur les valeurs traduites par les codeurs, et les états des interrupteurs;
• - une seconde interface, commandée par des ordres du microprocesseur, pour commuter l'alimentation du moteur;

est caractérisée en ce que la première interface comporte un circuit logique intégré, spécifique de cette application, comportant des moyens pour scruter et pour transmettre au microprocesseur les valeurs traduites par tous les codeurs, et les états de tous les interrupteurs de ladite machine, suite à la réception d'un ordre unique envoyé par le microprocesseur.According to the invention, a machine for franking mail, printing stamps by recording the values of these stamps, comprising:

• - a motor and wheels with raised figures, for printing a stamp;
• - a microprocessor to control the motor, and to record the value of each stamp printed;
• - position encoders connected respectively to the dials to translate the values of the digits of the printed stamp into binary words;
• - manual control switches;
• a first interface, controlled by orders from the microprocessor, for scanning and for transmitting to the microprocessor the values translated by the encoders, and the states of the switches;
• - a second interface, controlled by orders from the microprocessor, for switching the power supply to the motor;

is characterized in that the first interface comprises an integrated logic circuit, specific to this application, comprising means for scanning and for transmitting to the microprocessor the values translated by all the encoders, and the states of all the switches of said machine, further to receipt of a single order sent by the microprocessor.

The fact that scanning and transmission are triggered by a single order for all the encoders and switches of the machine, greatly lightens the task of the microprocessor. This characteristic makes it possible to use the microprocessor with greater efficiency, to make it perform other tasks that it could not have completed, or less well, in a machine according to the prior art, for lack of time. available; or allows this microprocessor to be used at a slower rate to reduce the consumption of electronic circuits. In addition, the microprocessor program can be made lighter, which makes it possible to free up space in its program memory for other tasks, or else makes it possible to use a memory of smaller capacity.

• - un bus relié au microprocesseur ;
• - des moyens pour filtrer des signaux envoyés par le microprocesseur;
• - des moyens pour mettre en parallèle des données binaires reçues en série;
• - des moyens pour décoder une adresse;
• - des moyens pour détecter un signal de début de transaction et détecter un signal de fin de transaction envoyés par le microprocesseur; et en ce qu'elle comporte, en propre :
• - des moyens pour mémoriser l'état de la commutation de l'alimentation du moteur;
• - au moins une partie d'un amplificateur de commutation pour commuter l'alimentation du moteur.

According to another characteristic, the second in terface, controlling the engine, is integrated into the same specific integrated circuit as the first interface, and it comprises, in common with the first interface:

• - a bus connected to the microprocessor;
• - means for filtering signals sent by the microprocessor;
• - Means for paralleling binary data received in series;
• - means for decoding an address;
• means for detecting a transaction start signal and detecting a transaction end signal sent by the microprocessor; and in that it includes, in its own right:
• - Means for memorizing the state of the switching of the motor supply;
• - at least part of a switching amplifier for switching the power supply to the motor.

The machine thus characterized no longer comprises, on the main card, an address decoder and a locking register for the switching commands of the motor supply, thanks to the fact that these commands are routed by the same bus and the same specific integrated circuit that the scanning and transmission orders. There is no longer a specialized driver to transmit a motor control signal between the two cards of the machine, therefore these two cards can each have a connector with four contacts only. In addition, the creation of a specific integrated circuit is an opportunity to integrate at least part of the switching amplifier. This characteristic therefore makes it possible to reduce the size of the connector and the number of components beyond what a simple integration of the interfaces according to the prior art would allow in a specific integrated circuit.

According to another characteristic of the machine according to the invention, the second interface is connected to the first interface, inside said specific integrated circuit, for transmitting to the microprocessor, at the same time as bits representing the values translated by the coders, and represent the states of the switches, a bit indicating the state of the motor: running or stopped.

The machine thus characterized, allows the microprocessor to verify the correct execution of the switching commands of the motor supply, without the slightest additional component having to be added, thanks to an internal connection to the specific circuit and thanks to the use of means already present, in the specific integrated circuit, to transmit the values translated by the encoders and transmit the states of the switches.

• - une phase de repos, à la suite de chaque mise sous tension ou à la suite d'une commande de retour au repos émise par le séquenceur lui-même, ou par le microprocesseur;
• - une phase d'activation, si ledit circuit intégré spécifique reçoit un signal de début de transaction, cette phase permettant de détecter une adresse qui est propre au circuit intégré spécifique, et un bit indiquant soit un ordre de scrutation et de transmission des valeurs traduites par les codeurs et des états des interrupteurs; soit un ordre de commutation de l'alimentation du moteur;
• - une phase de scrutation et de transmission, consécutive à une phase d'activation, si ledit circuit intégré spécifique reçoit, à la suite de son adresse, un ordre de transmission des valeurs traduites par les codeurs et des états des interrupteurs; cette phase étant suivie d'un retour à la phase de repos;
• - une phase de commande du moteur, consécutive à une phase d'activation, si ledit circuit intégré spécifique reçoit, à la suite de son adresse, un ordre de commutation de l'alimentation du moteur : mise en marche ou mise à l'arrêt.

According to another characteristic of the machine according to the invention, the first and the second interface comprise in common, in said specific integrated circuit, a sequencer comprising means for memorizing four operating phases which are mutually exclusive:

• - a rest phase, following each power-up or following a return to rest command issued by the sequencer itself, or by the microprocessor;
• an activation phase, if said specific integrated circuit receives a transaction start signal, this phase making it possible to detect an address which is specific to the specific integrated circuit, and a bit indicating either a scan order and a transmission of the translated values by encoders and switch states; either a command to switch the motor supply;
• a scanning and transmission phase, following an activation phase, if said specific integrated circuit receives, following its address, an order for transmission of the values translated by the encoders and of the states of the switches; this phase being followed by a return to the rest phase;
• - a motor control phase, following an activation phase, if said specific integrated circuit receives, following its address, a command to switch the power supply to the motor: starting or stopping .

This sequencer gives the interface card a certain autonomy, by making it possible to carry out a long phase of scanning and transmission or to carry out a motor command, following a single order sent by the microprocessor.

According to another characteristic, the specific integrated circuit, for a franking machine comprising encoders and switches making variable connections between rows and columns of a matrix of conductors, has outputs in number at least equal to the number of columns of the matrix, and which are respectively connected to said columns.

The machine thus characterized does not require diodes mounted respectively in series with the conductors constituting the columns of the matrix, thanks to the fact that each column is connected to an output of the specific integrated circuit, independent of the others. Thus the cost and size of the interface card are significantly reduced. On the other hand, this characteristic increases by 0.7 volt the noise immunity of the inputs of the specific circuit which are connected to the conductors constituting the lines of the matrix.

According to another characteristic, the specific integrated circuit includes a number of inputs re linked to matrix lines, which is greater than the number of matrix lines to which the coders are connected; at least one matrix line being connected only to manual control switches, the encoders and switches being connected as a group, each group having a number of outputs at most equal to the number of lines of the matrix, the outputs of each group being connected respectively to the rows of the matrix.

This specific integrated circuit structure allows the scanning phase and the transmission phase to be carried out more optimally, by increasing the number of useful bits in each byte of data sent to the microprocessor.

• - la figure 1 représente le schéma synoptique d'un exemple de réalisation de la carte d'interfaces d'une machine selon l'art antérieur;
• - la figure 2 représente le schéma synoptique d'un exemple de réalisation de la carte d'interfaces de la machine selon l'invention;
• - la figure 3 représente le chronogramme de la transmission d'un ordre de mise en marche ou d'arrêt du moteur, dans cet exemple de réalisation de la machine selon l'invention;
• - la figure 4 représente le chronogramme de la transmission d'un ordre de scrutation et de transmission, puis de la transmission de données vers le microprocesseur, dans cet exemple de réalisation de la machine selon l'invention;
• - la figure 5 représente le schéma synoptique du circuit intégré spécifique que comporte cet exemple de réalistion de la machine selon l'invention.

The invention will be better understood, other details and other advantages will appear from the following description and the accompanying figures:

• - Figure 1 shows the block diagram of an exemplary embodiment of the interface card of a machine according to the prior art;
• - Figure 2 shows the block diagram of an exemplary embodiment of the machine interface card according to the invention;
• - Figure 3 shows the timing diagram of the transmission of an order to start or stop the engine, in this embodiment of the machine according to the invention;
• - Figure 4 shows the timing diagram of the transmission of a scan and transmission order, then of the data transmission to the microprocessor, in this embodiment of the machine according to the invention;
• - Figure 5 shows the block diagram of the specific integrated circuit that includes this embodiment of the machine according to the invention.

• - quatre codeurs de position, 1 à 4, chacun traduisant sous la forme d'un mot binaire, respectivement : le chiffre des milliers, le chiffre des centaines, le chiffre des dizaines, et le chiffre des unités, du timbre imprimé par la machine à l'instant considéré;
• - quatre interrupteurs, SW1 à SW4, de commande manuelle;
• - un décodeur 5, du type 74HC138 fabriqué par la Société RTC;
• - un circuit d'entrée-sortie, du type PCF8574 fabriqué par la Société RTC;
• - deux transistors, 7 et 8, montés en circuit Darlington, et une résistance R6, pour constituer un dispositif de commutation de l'alimentation d'un moteur 10;
• - un circuit 9 d'alimentation du moteur 10.

The interface card of a machine according to the prior art, the diagram of which is shown in FIG. 1, comprises:

• - four position encoders, 1 to 4, each translating in the form of a binary word, respectively: the thousands digit, the hundreds digit, the tens digit, and the units digit, from the stamp printed by the machine at the instant considered;
• - four switches, SW1 to SW4, for manual control;
• - a decoder 5, of the 74HC138 type manufactured by the company RTC;
• - an input-output circuit, of the PCF8574 type manufactured by the company RTC;
• - Two transistors, 7 and 8, mounted in Darlington circuit, and a resistor R6, to constitute a device for switching the supply of a motor 10;
• - a circuit 9 for supplying the motor 10.

The motor 10 is connected to the interface card by two terminals 11 and 12. A transformer, not shown, which is not mounted on the interface card, supplies the circuit 9 by two terminals 13 and 14. The rest of the interface card is supplied by a DC voltage supplied by the main card, which is not shown. The interface card is connected to the main card by a connector 30 with five contacts.

A contact noted CDM, specialized for the control of the motor, provides a binary signal which directly controls the transistors 7 and 8 through the resistor R6. A contact marked SDA transmits data in serial form, from the microprocessor to an input of circuit 6, and vice versa. A contact noted SCL transmits a clock signal from the microprocessor to circuit 6, to clock the data transmission in both directions. A contact marked VDD provides a supply voltage of + 5V. A contact rated VSS brings a reference potential.

The encoders 1 to 4 and the switches SW1 to SW4 make variable connections between five rows and twelve columns of a matrix of conductors, each encoder constituting a sub-matrix comprising five rows and two columns. Each encoder has five terminals connected respectively to the five rows of the matrix and has two terminals connected to two columns of the matrix. Each encoder has two movable contacts which establish a connection between the first of the two columns corresponding to the encoder, and one of the five lines; and a link between the second of the two columns and another line among the five lines.

Each switch SW1 to SW4 possibly establishes a connection between a row of the matrix and a column. The five lines of the matrix are connected to the VDD contact providing a voltage of + 5V, respectively by five resistors R1 to R5 each having a value of 2.7 kilo-ohms. The scanning of one of the coders consists in connecting the two columns corresponding to this coder, to a potential close to the reference potential and to determining the potential on the five lines of the matrix. Each coder codes a digit, from 0 to 9, by providing on the five lines of the matrix a binary word comprising two low levels and three high levels, when it is scanned.

Each switch SW1 to SW4 is scanned by connecting the corresponding column to a potential close to the reference potential. If the switch is closed, the line to which the column is connected is at the low level. Otherwise, this line is at the high level.

The serial input-output circuit 6 has eight ports, denoted PO to P7, which can be configured individually either as input or output, by a write order sent by the microprocessor. It also has three inputs: A0, A1, A2, used to define the address of circuit 6 as the microprocessor's slave. In this example, these three inputs are linked to the reference potential. The ports PO to P4 are connected to the five lines of the matrix, while the ports P5, P6, P7 are connected to three inputs: A, B, C of the decoder 5.

The decoder 5 has eight complementary outputs, denoted YO to Y7. Each of these outputs is constituted by a CMOS door. Only one of the eight outputs is low at all times. It is a function of the value of the binary word applied to the inputs A, B, C. The outputs YO to Y5 are used to scan the twelve columns of the matrix, while the outputs Y6 and Y7 are not connected. One of these two outputs Y6, Y7 is selected when the microprocessor commands an absence of scanning on all the encoders and all the switches, at the end of a scanning sequence.

Each of the outputs YO to Y5 simultaneously scans two columns of the matrix by means of two diodes making it possible to maintain the independence of these two columns whatever the state of the contacts possibly connecting these two columns to the rows of the matrix. Likewise, the switches SW1 to SW4 are scanned two by two. In total, the interface card has twelve diodes D1 to D12 to fulfill this function. It appears, that each of these diodes increases by 0.7V the potential corresponding to the low level of the lines of the matrix, by adding their voltage drop of 0.7 V to a voltage drop of the order of 0.4V existing between the drain and the source of the transistor constituting each of the outputs YO to Y5 of the decoder 5. When one of the ports PO to P4 is configured as an input, the potential on the line connected to this port is interpreted as a low level s' it is less than 1.5 V, therefore the noise immunity is equal to 0.4 V. A disturbance producing on this line of the matrix an increase of + 0.4 V at the time of the scanning on the ports of the circuit 6, therefore causes an erroneous reading.

It also appears that the diodes D1 to D12 increase the number of components of the interface card; as well as the presence of the two transistors 7 and 8. On the other hand, it appears that the separation of the motor control interface, into a part located on the interface card and a part located on the main card, requires a connection between the two cards, by the contact noted CDM, which increases the number of connector 11 contacts by 25%.

Communication between the microprocessor and the serial input-output circuit 6 is established according to a conventional protocol called 12C. A transaction begins when the microprocessor sends a transaction start signal, consisting of a descent to the low level on the data conductor, SDA, while the clock conductor, SCL, is stable at the high level. A transaction is completed when the microprocessor emits an end of transition signal, consisting of a rise to the high level of the data conductor, SDA, while the clock conductor, SCL, has a high stable level.

To scan an encoder, or a group of two switches, the microprocessor begins by configuring circuit 6, with a write operation. For example, to scan the encoder 4 translating the value of the digit of the units, the ports PO to P4 are configured as inputs while the ports P5, P6, P7 are configured as outputs providing a binary word 000 so that the decoder 5 provides a low level on its output YO and high levels on its outputs Y1 to Y7, the output YO exciting the two columns of the encoder 4. To carry out this configuration, the microprocessor emits: a start signal, then a byte composed of the seven bits of the specific address of circuit 6, and of a read or write command bit; followed by a data byte that controls the configuration of ports PO to P7. Before transmitting this data, the microprocessor checks that it receives an acknowledgment signal sent by the circuit 6, in the form of a low level, during the 9th clock period. Likewise, the microprocessor verifies that it receives an acknowledgment signal after having transmitted the data byte. Then it sends the end of transaction signal.

To read the logic levels on the five ports PO to P4, the microprocessor then orders a read. For this, it transmits a transaction start signal, followed by a byte made up of the seven bits of the address specific to circuit 6, followed by the read-write bit indicating a read. Then it verifies that it receives an acknowledgment of receipt sent by the circuit 6, and consisting of a low level during the ninth clock period. It then receives a byte indicating the logical levels read on the ports PO to P7, among which only the ports PO to P4 are of interest. The microprocessor then emits an acknowledgment of receipt, then an end of transaction signal.

To scan the value translated by the tens digit encoder, 3, a similar sequence is repeated, but ports P5 to P7 are configured as outputs with different levels so that the decoder 5 scans the encoder 3, instead of the encoder 4 An analogous sequence is restarted to examine the value translated by the encoder 2; then to examine the value translated by the encoder 1; then to examine the state of the switches SW3, and SW4; then to scan the state of switches SW1 and SW2. In total, the scanning of the matrix requires thirteen transactions, each transaction corresponding to twenty clock pulses, on the conductor SCL. As the minimum admissible period for this clock, in this exemplary embodiment, is 10 microseconds, the minimum duration necessary to scan all the encoders and switches is therefore 2.6 milliseconds.

To correctly neutralize the effect of contact bouncing, these contacts must be scanned approximately every 10 milliseconds. Under these conditions, the microprocessor spends a quarter of its time scanning the encoders and switches. In addition, the polling program includes numerous instructions, since it ensures the management of numerous write and read orders intended for the interface card. Finally, the assembly has the disadvantage of consuming a certain current during all the duration of the scanning, that is to say 2.6 milliseconds at least, every 10 milliseconds. In this exemplary embodiment, this current has an intensity of 3 milliamps during the scanning. The average power consumed is relatively high because it is directly proportional to the duration of the scan.

• - quatre codeurs de position, 21 à 24, analogues aux codeurs 1 à 4 décrits précédemment, constituant chacun une sous-matrice à cinq lignes et deux colonnes;
• - quatre interrupteurs, SW'1 à SW'4, analogues aux interrupteurs SW1 à SW4 décrits précédemment;
• - un circuit intégré spécifique de l'application, 25;
• - un transistor de puissance 28;
• - un circuit 26 d'alimentation, analogue au circuit d'alimentation 9 décrit précédemment, pour alimenter un moteur 27.

FIG. 2 represents the block diagram of an exemplary embodiment of the interface card of a franking machine, according to the invention. This card includes:

• - four position encoders, 21 to 24, analogous to the encoders 1 to 4 described above, each constituting a sub-matrix with five rows and two columns;
• - four switches, SW'1 to SW'4, similar to the switches SW1 to SW4 described above;
• - an application-specific integrated circuit, 25;
• - a power transistor 28;
• a supply circuit 26, similar to the supply circuit 9 described above, for supplying a motor 27.

The interface card is connected to the motor 27 by two terminals 17 and 18, and to a supply transformer, not shown, by two terminals 19 and 20 which are connected to two inputs of the supply circuit of the circuit 26. The terminal 17 is connected to the collector of transistor 28 while terminal 18 is connected to an output of the supply circuit 26. The interface card is also connected to a main card, carrying a microprocessor 16, by a connector 29.

The main card is represented briefly by its microprocessor 16 and by a connector 15 which fits into the connector 29. This card notably includes a supply circuit, not shown, supplying a voltage of + 5V. The connector 29 has only four contacts.

A contact marked SDA is connected to a conductor transmitting data in serial form, in both directions. A contact noted SCL is connected to a conductor transmitting a clock signal sent by the microprocessor 16 during the transactions. A contact marked VDD receives a continuous supply voltage of + 5V. A contact noted VSS is connected to a conductor bringing the reference potential.

The specific integrated circuit 25 comprises two inputs connected respectively to the two contacts SDA and SCL of the connector 29, to communicate with the microprocessor 16. It further comprises: six inputs denoted E2 to E7 which are respectively connected to six lines of a matrix of conductors; an output marked MOT which is connected to the base of transistor 28 by a resistor R13; and outputs: UNIO, UNI1, UN12, DIZO, DIZ1, DIZ2, CENTO, CENT1, CENT2, MIO, M11, M12, which are respectively connected to the twelve columns of the matrix. Each of the coders 21 to 24 has two terminals connected respectively to two columns of the matrix; and comprises five second terminals connected respectively to five lines of the matrix, the sixth line being independent of the encoders but being common to the four switches SW'1 to SW'4.

Each of these switches is connected to a separate column, and establishes a connection between this column and the sixth row of the matrix. The six lines of the matrix are connected to the supply voltage, respectively by six resistors R7 to R12 each having a value of 1.2 kilo-ohms. The diagram does not include any diodes since each column of the matrix is scanned by an independent output, UNIO, ..., M12, of the specific integrated circuit 25. This eliminates the drawbacks of cost, bulk, and reduction immunity to noise, which were due to diodes D1 to D12 of the interface card described above.

The outputs UNIO to M12 are respectively constituted by transistors of the MOS type with open drain, while the output MOT is made up of a complementary pair of transistors of the MOS type.

The specific integrated circuit 25 has essentially three functions, triggered respectively by three unique orders sent by the microprocessor 16 according to the protocol 12C: a single order for controlling the starting of the engine; a single command to order engine shutdown; and a single command for controlling a scan of all the encoders and all the switches.

FIG. 3 represents a timing diagram of the transaction between the microprocessor 16 and the circuit 25, constituting an order to control the motor, which replaces the connection by the conductor noted CDM in the interface card according to the prior art, described above. The transaction begins with a start signal, consisting of a passage at the low level of the SDA conductor, while the SCL conductor is stable at the high level. The microprocessor 16 then sends an address of seven bits, specific to the integrated circuit 25, then a read-write bit, denoted R / W, during in the eighth clock period. In this case, the R / W bit is a write bit, consisting of a low level. Then the circuit 25 responds with an acknowledgment of receipt, denoted ACK, constituted by a low level on the conductor SDA during the ninth period of the clock sent on the conductor SCL.

When the microprocessor 16 has detected this acknowledgment of receipt, it sends an eight-bit control word which has the hexadecimal value 6A or EA to command a starting of the motor; or which has a hexadecimal value other than 6A and EA to stop the engine. When it has received this command word, the circuit 25 sends an acknowledgment, denoted ACK, constituted by a low level on the conductor SDA for the duration of the ninth clock period, counted from the first bit of the word ordered. Finally, the microprocessor 16 sends an end of transaction signal, constituted by a high level transition on the conductor SDA while the conductor SCL has a stable high level. The circuit 25 imposes a voltage close to + 5V or 0V on its MOT output, depending on whether the order is to start or stop the supply of the motor 27.

FIG. 4 represents a timing diagram of the transaction between the circuit 25 and the microprocessor 16, constituting the order of scanning and transmission, then the actual transmission of the values translated by the encoders 21 to 24, and of the state of the switches SW '1 to SW'4. The microprocessor 16 sends a single order which consists first of all of a transaction start signal, then of the address specific to the integrated circuit 25, then of an R / W read-write bit. In this case, it is a read bit consisting of a high level on the driver SDA for the duration of the eighth clock period on the driver SCL. The response of circuit 25 is: an acknowledgment, ACK, constituted by a low level on the conductor SDA during the ninth period of the clock; then a first data byte consisting of bits B7, B6, B5, B4, B3, B2, M, and a stuffing bit. These bits B7 to B2 represent respectively: the states of the inputs E7 to E2 when the encoder 21 and the switch SW'1 are scanned by setting the outputs MIO, M11 and M12 to the low level. Bit M represents the switching state of the motor supply.

The microprocessor 16 responds briefly by sending an acknowledgment, ACK ', consisting of a low bit on the conductor SDA during the ninth clock period on the conductor SCL, counted from the first data bit. When the circuit 25 has received this acknowledgment ACK ', it sends a second data byte representing the state of the inputs E7 to E2 when the encoder 22 and the switch SW'2 are scanned by setting the outputs CENTO to low. , CENT1, CENT2; and representing the state of the switching of the motor supply.

The microprocessor 16 responds briefly by sending an acknowledgment ACK '. After receiving this acknowledgment ACK ', the circuit 25 sends a third data byte representing the state of the inputs E7 to E2 when the encoder 23 and the switch SW'3 are scanned by setting the outputs DIZO to low , DIZ1, DIZ2; and representing the state of the switching of the motor supply.

The microprocessor 16 responds with an acknowledgment of receipt ACK '. After receiving this acknowledgment ACK ', the circuit 25 sends a fourth data byte representing the state of the inputs E7 to E2 when the encoder 24 and the switch SW'4 are scanned by setting the outputs to low. UNIO, UNI1, UN12; and representing the state of the switching of the motor supply. The microprocessor 16 responds by sending an acknowledgment of receipt ACK '. Then, as there is no more data to transmit, it sends an end of transaction signal. The transaction has five bytes instead of twenty six.

The number of inputs E2, ..., E7 connected to the lines of the matrix has been increased compared to the number of ports PO, ..., P4 configured as inputs, in the interface card according to the prior art. The number of rows in the matrix has been increased from five to six. Thanks to this means, the encoders and switches are scanned by group, each group comprising an encoder and a switch, in this example. This minimizes the number of data bytes to be transmitted to the microprocessor, since each data byte contains six useful bits, instead of five. In this example, four bytes are enough to transmit the data resulting from the scan. The transaction therefore comprises five bytes, instead of seven if the switches constituted two separate groups of coders, as was the case in the prior art.

If the clock period on the SCL conductor is 10 microseconds, the scan lasts less than 0.5 milliseconds, which is about 5 times less than in the example machine according to the prior art, described above.

On the other hand, the scanning of the state of an encoder and of a switch does not last during the duration of transmission of a byte, but in fact only lasts during the duration of a clock period preceding this transmission, that is to say lasts only 10 microseconds. In this example, the encoders therefore consume current only for 4 times 10 microseconds, ie 0.04 milliseconds instead of 2.6 milliseconds in the example of machine according to the prior art. The energy consumption in the interface card is therefore significantly reduced.

This reduction in consumption easily makes it possible to increase the intensity of the current passing through each contact, with the aim of improving the reliability of the contacts when an oxide layer or a dust layer is formed. This is why resistors R7 to R12 have a value of 1.2 kilo-ohms instead of 2.7 kilo-ohms. This reduction in resistance makes it possible to approximately double the intensity of the current passing through each contact, while nevertheless benefiting from a significant reduction in the energy consumption in the interface card.

The scanning time is reduced by a factor of five: 0.5 milliseconds instead of 2.6 milliseconds, which frees up computing time for the microprocessor. The program controlling the microprocessor is very light since a single command is sufficient to scan all the encoders and switches. Consequently, the program requires less memory capacity, which frees up space for other applications, or makes it possible to reduce the size of this memory.

• - un oscillateur 62, constitué d'une série d'inverseurs logiques rebouclées pour osciller avec une période d'environ 0,1 microseconde;
• - deux filtres numériques classiques, 61 et 63, ayant chacun une entrée reliée respectivement au conducteur SDA et au conducteur SCL, pour éliminer les parasites superposés aux signaux transmis sur ces conducteurs;
• - un registre à décalage 60 dans lequel sept bits peuvent être inscrits ou lus, en série ou en parallèle;
• - un décodeur 65 pour décoder l'adresse propres au circuit intégré spécifique 25;
• - un décodeur 66 pour décoder les mots de commande propre à la mise en marche du moteur;
• - un circuit 67 pour détecter le signal de début de transaction et le signal de fin de transaction;
• - un compteur par neuf, 68;
• - un séquenceur 69, constitué essentiellement de quatre bascules et de portes logiques non représentées, pour mémoriser quatre phases de fonctionnement qui s'excluent mutuellement;
• - un dispositif d'initialisation 80, qui fonctionne à la mise sous tension du circuit 25;
• - une bascule 81 pour mémoriser l'état de la commutation de l'alimentation du moteur;
• - un préamplificateur 82 ayant une sortie constituant la sortie MOT du circuit 25;
• - un compteur par cinq, 71;
• - un décodeur 70, ayant cinq sorties dont l'une est sélectionnée au moyen d'un mot de trois bits;
• - douze interfaces de sortie, 40 à 51, constituées chacune d'un transistor de type MOS à drain ouvert, constituant respectivement les sorties UNI0,...,MI2 du circuit 25;
• - des portes logiques ET, 31 à 37, 59, 64 et 72.

FIG. 5 represents the block diagram of an exemplary embodiment of a specific integrated circuit 25 carrying out the functions described above. It can be produced using CMOS technology. This example includes:

• - An oscillator 62, consisting of a series of logic inverters looped back to oscillate with a period of approximately 0.1 microseconds;
• - two conventional digital filters, 61 and 63, each having an input connected respectively to the SDA conductor and to the SCL conductor, to eliminate the parasites superimposed on the signals transmitted on these conductors;
• - a shift register 60 in which seven bits can be written or read, in series or in parallel;
• a decoder 65 for decoding the address specific to the specific integrated circuit 25;
• - a decoder 66 for decoding the control words specific to starting the engine;
• a circuit 67 for detecting the start of transaction signal and the end of transaction signal;
• - one counter per nine, 68;
• - A sequencer 69, consisting essentially of four flip-flops and logic gates, not shown, for storing four operating phases which are mutually exclusive;
• - an initialization device 80, which operates when the circuit 25 is energized;
• - A flip-flop 81 for memorizing the state of the switching of the motor supply;
• - A preamplifier 82 having an output constituting the MOT output of circuit 25;
• - a counter by five, 71;
• - a decoder 70, having five outputs, one of which is selected by means of a three-bit word;
• - twelve output interfaces, 40 to 51, each consisting of an open drain MOS type transistor, respectively constituting the outputs UNI0, ..., MI2 of circuit 25;
• - AND logic gates, 31 to 37, 59, 64 and 72.

The clock signal supplied by the conductor SCL constitutes a clock signal denoted H1, after filtering by the filter 63. It is applied to: a clock input of register 60; a clock input of the detector 67; and a clock input of the counter 68. The oscillator 62 supplies a clock signal H2 to the two filters 61 and 63, and to a clock input of the sequencer 69. The data signal supplied by the conductor SDA is filtered by the filter 61 then is supplied, on the one hand, to a data input of the detector 67 and, on the other hand, to a first input of the AND gate 64.

An output of the detector 67 is connected to an input of the sequencer 69 to provide it with a logic signal for the duration of a transaction. An output of the sequencer 69 is connected to a second input of the AND gate 64, and an output of the latter is connected to a serial input of the circuit 60. The register 60 is loaded in series, by validating the AND gate 64, to load an address received or load a motor control word, at the rate set by the clock H1. The register 60 has seven stages having seven parallel outputs connected respectively to seven inputs of the decoder 65 and to seven inputs of the decoder 66.

The output of the first stage of the register 60 is connected to an input of the sequencer 69. This output provides the R / W bit for read-write command, or the acknowledgment bit ACK ', during certain periods of the clock. H1.

Register 60 has seven parallel inputs which are respectively connected to the outputs of AND gates 31 to 37. A first input of each AND gate 31 to 36 constitutes respectively one of the inputs E7 to E2 of circuit 25. A first input of AND gate 37 is connected to the output of flip-flop 81 memorizing the state of the switching of the motor supply, by a link marked EM, internal to the specific integrated circuit 25. A second input from each of the gates 31 to 37 is connected to an output of the sequencer 69 to control the loading of seven bits in parallel in the register 60.

The decoder 65 and the decoder 66 each have an output connected respectively to an input of the sequencer 69. When the decoder 65 recognizes the address specific to the integrated circuit 25, it provides a signal at input of the sequencer 69. The register 60 has an output series connected to a first input of the AND gate 59. A second input of this door is connected to an output of the sequencer 69, which controls a serial transmission to the microprocessor, and an output of this door 59 is connected to the SDA conductor.

The counter 68 has: a clock input connected to the output of the filter 63; a validation input connected to an output of the sequencer 69; a first output connected to an input of the sequencer 69 to supply it with a pulse for the duration of each eighth period of the clock H, which corresponds to the reception of an R / W bit; a second output connected to an input of the sequencer 69 and to a first input of the gate ET72.

The counter 68 is a counter by nine which counts the pulses of the clock signal H1. Its second output provides another clock signal denoted H3 consisting of a pulse for each ninth pulse of the clock signal H1. Each pulse of the clock signal H3 therefore corresponds to the time interval reserved for the emission of an acknowledgment signal ACK by the circuit 25 or the reception of a reception signal ACK 'sent by the microprocessor 16 .

A second input of the AND gate 72 is connected to an output of the sequencer 69. The output of the gate 72 is connected to a clock input of the counter 71.

The counter 71 is a counter by five which counts five periods of the clock H3 to scan four groups successively, each group consisting of an encoder and a switch; and which has a fifth period of the clock H3 to return to an absence of scanning. The counter 71 has three outputs connected respectively to three inputs of the decoder 70. The latter has five outputs of which only one is selected at a time, according to the value of the binary word applied to the three inputs. These outputs are denoted SO, ..., S4 and are selected in this order when the counter 71 is incremented. The output SO is connected in parallel to the inputs of the output interfaces 49, 50, 51 which correspond respectively to three outputs MIO, M11, M12, of the circuit 25. Similarly the outputs S1, S2, S3 each control a group of three interfaces Release. The output S4 is connected to a sequencer input 69. It provides a logic signal, noted END, indicating to it the end of the scanning of the four groups of coders and switches, in order to bring the sequencer 69 back to a rest phase.

The initialization device 80 has an output connected to an initialization input of the sequencer 69 and to an initialization input of the flip-flop 81, to put the sequencer 69 in a rest phase, and to cut the power supply to the motor 27 when the franking machine is switched on.

The flip-flop 81 has a data input connected to an output of the sequencer 69, for storing an on or off order. The output of the flip-flop 81 is connected to an input of the preamplifier 82. The output of the flip-flop 81 is also connected, inside the integrated circuit 25, to a first input of the AND gate 37. The second input of the door AND 37, as well as the second inputs of AND gates 31 to 36 are connected to an output of sequencer 69 which commands the parallel loading of a word of seven bits of data in register 60, for their transmission in the form of series . Thus the state of the switching of the power supply, and therefore the state of the motor, will be transmitted to the microprocessor 16 in the same byte which will transmit the state of the inputs E7 to E2.

The sequencer 69 is in a rest phase following an initialization by the device 80, at power-up; or following a scan end signal supplied by the output S4 of the decoder 70; or after the execution of an engine start or stop order; or following the detection of an end of transaction signal, by the detector 67.

The sequencer 69 goes into an activation phase as soon as a start of transaction signal is detected by the detector 67. It then commands the AND gate 64 to load into the register 60 the bits transmitted by the microprocessor 16. It validates the counter 68. At the end of the seventh clock pulse H3, the signal supplied by the output of the address decoder 65 is stored by the sequencer 69. If this signal does not indicate that the address specific to circuit 25 has been detected, the sequencer 69 blocks the emission of an acknowledgment of receipt ACK, then it enters the rest phase at the end of the ninth clock pulse H3. Otherwise, it sends an acknowledgment of receipt ACK on the driver SDA by imposing a low level, during the ninth period of the clock H3. Then it goes into the scanning and transmission phase, or else into the control phase of the motor, according to the value of the R / W bit, which is supplied to it by the output of the first stage of the register 60 during the eighth period of the clock H3.

If the R / W bit is low, it indicates a command to switch the motor supply. The sequencer 69 then enters a motor control phase. The motor control word is loaded into circuit 60 and is then decoded by circuit 66 which supplies a logic signal to sequencer 69. If the control word has the hexadecimal value 6A or EA, the decoder 66 provides a high level which corresponds when the engine is started. If the control word has another value, the decoder 66 provides a low level which corresponds to a shutdown. The output of the sequencer 69 which is connected to a control input of the flip-flop 81 writes the value of this logic signal there. If it is a start command, the preamplifier 82 supplies the output MOT with a current to saturate the power transistor 28.

After decoding the word controlling the motor, the sequencer 69 sends an acknowledgment of receipt ACK to the microprocessor, by imposing a low level on the conductor SDA, by means of the AND gate 59; then returns to a rest phase. The engine remains running if it has been started or remains stopped if it has just been stopped.

If the R / W bit is high, it indicates an order to scan all the values translated by the encoders and all the states of the switches, and to transmit them. The sequencer 69 then enters a scanning and transmission phase. For each group consisting of an encoder and a switch, the decoder 70 selects a group of three output interfaces, for example 40, 41, 42, to bring three columns of the matrix to a potential close to the reference potential. The sequencer 69 validates the gates 31 to 37, 72, and 59, to load seven bits of data in parallel into the register 60 then transmit them in series on the conductor SDA, with an eighth bit constituting a stuffing.

The microprocessor 16 sends an acknowledgment ACK ', consisting of a high level, during the clock period following the eight transmission periods of a data byte. This acknowledgment is loaded into the first stage of register 60 under the control of each ninth pulse of the clock H1. The output of the first stage provides this acknowledgment ACK 'to the sequencer 69.

This sequence is repeated for the second, third, and fourth groups of encoders and switches.

At the end of the scan, the end signal supplied by the decoder 70 causes the sequencer 69 to return to the rest phase. If the circuit 25 does not receive an acknowledgment of receipt ACK 'for the first, or the second, or the third byte of data, the sequencer 69 returns to a quiescent phase and waits for a new order starting with a start signal.

The transmission of the state of the motor from circuit 25 to the microprocessor makes it possible to achieve a very reliable control of the motor, since a transmission error, affecting the motor control word, is detected quickly, during the next scan, thanks to the bit M which is retransmitted to the microprocessor. On the other hand, it should be noted that the number of values (6A or EA) of the control word triggering the starting of the engine is much lower than the number of values (two hundred and fifty six) causing the engine to stop. A transmission disturbance is therefore much more likely to cause the engine to stop, rather than starting unexpectedly.

The scope of the invention is not limited to the embodiment described above, those skilled in the art can adapt it in particular to scan another number of coders and switches; and can optionally group them differently. It can also be adapted to the case where the microprocessor is connected to the interfaces by a bus with parallel transmission, instead of a bus with serial transmission.

Claims (6)

1. Mail franking machine, printing stamps by recording the values of these stamps, comprising: - a motor (27) and knobs carrying figures in relief, for printing a stamp; - a microprocessor (16) for controlling the motor, and for recording the value of each stamp printed; - position encoders (21 to 24), respectively connected to the dials to translate the values of the digits of the printed stamp into binary words; - and manual control switches (SW'1 to SW'4); a first interface, controlled by orders from the microprocessor, for scanning and for transmitting to the microprocessor the values translated by the encoders, and the states of the switches; - a second interface, controlled by orders from the microprocessor, for switching the power supply to the motor;
characterized in that the first interface comprises an integrated logic circuit (25), specific to this applica tion, comprising means (31 to 72) for examining and transmitting, to the microprocessor (16), the values translated by all the encoders (21 to 24), and the states of all the switches (SW'1 to SW'4 ) of said machine, following the reception of a single order sent by the microprocessor (16). 2. Machine according to claim 1, characterized in that the second interface is integrated in the same specific integrated circuit (25) as the first interface; and includes, in common with the first interface: - a bus (SDA, SCL) connected to the microprocessor (16); - means (61 to 63) for filtering signals sent by the microprocessor (16); - means (60) for putting a parallel of the binary data received in series; - means (65) for decoding an address; - means (67) for detecting a start of transaction signal and an end of transaction signal sent by the microprocessor;
and in what it comprises, in its own right - Means (81) for memorizing the state of the switching of the motor supply; - at least one part (82) of a switching amplifier for switching the power supply to the motor (27). 3. Machine according to claim 2, characterized in that the specific integrated circuit (25) comprises an internal link (EM) connecting the second interface to the first interface to transmit to the microprocessor, at the same time as bits (B2, .. ., B7) representing the values translated by the encoders (21 to 24) and representing the states of the switches (SW'1 to SW'4), a bit (M) indicating the state of the motor (27): running or stopped. 4. Machine according to claim 2, characterized in that the first and the second interface further comprise, in common, in said specific circuit (25), a sequencer (69) comprising means for memorizing four operating phases, which s '' mutually exclude: - a rest phase, following each power-up or following a command to return to rest, issued by the sequencer itself, or by the microprocessor; - an activation phase, if said specific integrated circuit (25) receives a transaction start signal; this phase making it possible to detect an address which is specific to the specific integrated circuit, and a bit indicating either an order of scanning and of transmission of the values translated by the encoders and of the states of the switches; either a command to switch the motor supply; - a scanning and transmission phase, following an activation phase, if said specific integrated circuit (25) receives, following its address, a bit indicating an order of scanning and transmission of the values translated by the encoders and switch states; this phase being followed by a return to the rest phase; a motor control phase (27), consecutive to an activation phase, if said specific integrated circuit (25) receives, following its address, a bit indicating a command to switch the power supply to the motor, on or off. 5. Machine according to claim 1, comprising coders (21 to 24) and switches (SW1 to SW4) making variable connections between rows and columns of a matrix of conductors, characterized in that said specific integrated circuit ( 25) has outputs (UNI1, UN12, ...) in number at least equal to the number of columns of the matrix, and which are respectively connected to said columns. 6. Machine according to claim 5, characterized in that said specific integrated circuit (25) has a number of inputs connected to matrix lines, which is greater than the number of matrix lines to which the encoders are connected (21 to 24 ); at least one matrix line being connected only to manual control switches (SW'1 to SW'4), the encoders (21 to 24) and the switches (SW'1, ..., SW'4 ) being connected in groups (21-SW'1, 22-SW'2, ...), each group having a number of outputs at most equal to the number of rows of the matrix, the outputs of each group being connected respectively to matrix lines.

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