EP0485021A1 - Elastic buffer - Google Patents
Elastic buffer Download PDFInfo
- Publication number
- EP0485021A1 EP0485021A1 EP91202821A EP91202821A EP0485021A1 EP 0485021 A1 EP0485021 A1 EP 0485021A1 EP 91202821 A EP91202821 A EP 91202821A EP 91202821 A EP91202821 A EP 91202821A EP 0485021 A1 EP0485021 A1 EP 0485021A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- information
- buffer
- address
- pointers
- addressing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
Definitions
- the invention relates to a buffer for temporary storage of digital information in memory locations having n cyclically successive addresses, which information is transmitted between two digital systems coupled to each other through the buffer, which systems comprise each a clock generator, there being provided addressing units associated to each of the systems comprising each an address counter, which addressing units are used for addressing while the information is being written in the memory locations of the buffer on a first time base determined by the clock generator of one system and for addressing while the information is being read out on a second time base determined by the clock generator of the other system, which second time base substantially corresponds to the first time base which is substantially equivalent to the first time base.
- the invention further relates to a data communication system comprising two or more digital systems which mutually exchange information through a buffer connected to the systems.
- Such a buffer is known from French Patent Application FR 2 583 238 and is used, for example, in digital telephone exchanges or for communication between digital systems, such as microprocessors, modems etc.
- prior-art buffer is that the transmission efficiency expressed in terms of amounts of effectively transmitted information is too low when the buffer is used in a communication system.
- the buffer according to the invention is characterized in that the buffer comprises two rows of cyclically numbered memory locations and the buffer includes a control circuit coupled to the addressing units, which control circuit is arranged in such a manner that during the addressing operation either system writes information in a memory location in one row and reads information from the corresponding memory location in the other row, whereas the other system reads the information from the memory location in one row and writes the information in the corresponding memory location in the other row.
- each of the two systems reads and writes substantially simultaneously during the addressing operation of the thus arranged dual buffer, the transmission efficiency is further improved. Communication between the digital systems may then be effected in the full duplex mode.
- this buffer comprises an address distance monitoring means connected to the addressing units for creating a difference between the address counts (pointers) of the address counters when equality between the address counts (pointers) of the address counters is detected, which address distance monitoring means is arranged in such a way that the distance between the pointers of the address counters is made equal to n:2.
- a pointer difference of n:2 maximizes the mutual distance between the pointers controlled by the relevant clock generators, so that the chance of the pointers addressing the same memory location at any one moment is minimized. This minimizes the number of necessary retransmissions in which the same information is to be retransmitted for obtaining a reliable information transmission and optimizes the transmission efficiency.
- the control protocols with which a retransmission of bit, byte or frame-structured information is provided with the aid of check bits and control bits are thus resorted to for shorter time intervals. The gain of time leads to a further improvement of the amount of effectively transmitted information.
- the pointers of the address counters in such a way that one of the pointers is brought back to a fixed initial position in the buffer after the address distance monitoring means has detected equality, a simplified retransmission is effected in the cases where the byte synchronisation is lost during information transmission between the digital systems.
- the drawing Figure shows a communication system 1 comprising two digital systems 2 and 3 coupled through a buffer 4.
- the systems 2 and 3 are connected to the respective lines 5 and 6 and connected to the storage area 7 of the buffer 4.
- Data communication between the systems 2 and 3 is effected in that, for example, information originating from system 2 is written in the storage area 7 and after being read out is made available to a system 3 over line 6.
- system 3 transmits the data to system 2.
- the writing and reading of information in the memory area 7 may even be performed simultaneously by the two systems 2 and 3.
- the communication between the two systems 2 and 3 is effected in synchronism, which is to say, communication is effected under the control of a clock signal.
- This clock signal is generated by clock generators 8 and 9 included in each of the systems 2 and 3.
- the clock generators 8 and 9 produce the time base signals in response to which synchronous data communication takes place. This communication does not take place, however, in the manner in which either time base dominates the other.
- Each of the systems 2 and 3 retains its autonomous time base derived from the relevant output signal of the clock generator 8 or 9 to address the storage area 7.
- the storage area 7 comprises, for example, one or two rows of memory locations a1 to an and b1 to bn respectively.
- the buffer 4 comprises a single row of memory locations a1 to an.
- the drawing Figure diagrammatically shows the case where n 8.
- Addressing units 10 and 11 shown in the buffer 4 comprise address counters 12 and 13 in which address values are stored in the form of pointers for addressing the memory locations.
- the systems 2 and 3 provide information in the form of check and control signals influencing the pointers of the address counters 12 and 13 in the buffer 4.
- a clock signal is generated by each of the clock generators 8 and 9 and added to the information to be transmitted, from which the pointers can be derived.
- This clock signal may be transmitted by the systems 2 and 3 over a separate line in tandem with the information data portion to be transmitted, but, alternatively, it is possible that the clock information is included in the coding of the data to be transmitted.
- the clock information can be recovered by regenerating the transmitted data.
- the actual data transmission will be effected bit-by-bit, generally under the control of a suitable protocol.
- the information transmitted bit-by-bit over line 5 is written in a memory location, for example, a7, for which case the value of 7 will be stored in the address counter 12.
- the buffer 4 is a cyclic memory and structured as a ring memory.
- the pointers of the address counters 12 and 13 are adjusted to 0 and n/2, respectively.
- the storage area 7 of the buffer 4 comprises two aforedescribed rows a and b having cyclically numbered memory locations a1 to an and b1 to bn.
- one row for example row a
- information of, for example, system 2 is written in, for example, memory location a7, while information is read out from the corresponding location b7.
- memory location 3 will be addressed by addressing unit 11 comprising address counter 13, while information is read out from memory location a3 and a few instants later information originating from system 3 is written in memory location b3.
- the control logic necessary for this purpose is accommodated in a control circuit 15 connected to the two addressing units 10 and 11.
- control circuit 15 which includes the logic necessary for controlling the second row of memory locations present is deemed to be known to the expert.
- pointers of the address counters 12 and 13 are changed in such a way that one of them is reset to a fixed initial position, for example, 1 in the present case once they have been differentiated after collision, it will be possible to restore the byte synchronisation in a simpler manner if the byte synchronisation in the data control protocol has been lost, because the restoration of lost byte synchronisation necessitates bringing back the relevant read and write pointers to fixed initial positions.
Abstract
Description
- The invention relates to a buffer for temporary storage of digital information in memory locations having n cyclically successive addresses, which information is transmitted between two digital systems coupled to each other through the buffer, which systems comprise each a clock generator, there being provided addressing units associated to each of the systems comprising each an address counter, which addressing units are used for addressing while the information is being written in the memory locations of the buffer on a first time base determined by the clock generator of one system and for addressing while the information is being read out on a second time base determined by the clock generator of the other system, which second time base substantially corresponds to the first time base which is substantially equivalent to the first time base.
- The invention further relates to a data communication system comprising two or more digital systems which mutually exchange information through a buffer connected to the systems.
- Such a buffer is known from French
Patent Application FR 2 583 238 and is used, for example, in digital telephone exchanges or for communication between digital systems, such as microprocessors, modems etc. - The disadvantage of prior-art buffer is that the transmission efficiency expressed in terms of amounts of effectively transmitted information is too low when the buffer is used in a communication system.
- It is an object of the invention to optimize the transmission efficiency when the buffer is used in a communication system.
- For this purpose, the buffer according to the invention is characterized in that the buffer comprises two rows of cyclically numbered memory locations and the buffer includes a control circuit coupled to the addressing units, which control circuit is arranged in such a manner that during the addressing operation either system writes information in a memory location in one row and reads information from the corresponding memory location in the other row, whereas the other system reads the information from the memory location in one row and writes the information in the corresponding memory location in the other row.
- If each of the two systems reads and writes substantially simultaneously during the addressing operation of the thus arranged dual buffer, the transmission efficiency is further improved. Communication between the digital systems may then be effected in the full duplex mode.
- Data communication between systems comprising each their own clock generator poses specific requirements to the control logic in suchlike systems, however, because there is usually frequency or phase inequality between the clock signal of the transmitting system and that of the receiving system. In certain circumstances the frequencies may deviate to such an extent that the address counts (pointers) on the basis of which the addressing is performed when information is written or read out, become equal, which would cause information at a specific memory location to be written and read out simultaneously. In that case the transmitted information is mutilated, which is usually designated bit slip. If this situation is detected by the address distance monitoring means, the address counts also designated pointers are set apart, that is to say, rendered different relative to each other, which necessitates a renewed transmission of information transmitted previously.
- In an embodiment for the buffer this buffer comprises an address distance monitoring means connected to the addressing units for creating a difference between the address counts (pointers) of the address counters when equality between the address counts (pointers) of the address counters is detected, which address distance monitoring means is arranged in such a way that the distance between the pointers of the address counters is made equal to n:2.
- A pointer difference of n:2 maximizes the mutual distance between the pointers controlled by the relevant clock generators, so that the chance of the pointers addressing the same memory location at any one moment is minimized. This minimizes the number of necessary retransmissions in which the same information is to be retransmitted for obtaining a reliable information transmission and optimizes the transmission efficiency. In this manner the control protocols with which a retransmission of bit, byte or frame-structured information is provided with the aid of check bits and control bits are thus resorted to for shorter time intervals. The gain of time leads to a further improvement of the amount of effectively transmitted information.
- By influencing, according to a further embodiment of the buffer, the pointers of the address counters in such a way that one of the pointers is brought back to a fixed initial position in the buffer after the address distance monitoring means has detected equality, a simplified retransmission is effected in the cases where the byte synchronisation is lost during information transmission between the digital systems.
- The invention will also be further explained with reference to the annexed drawing. In the drawing the Figure shows a preferred embodiment of a communication system and a buffer according to the invention.
- The drawing Figure shows a communication system 1 comprising two
digital systems systems respective lines storage area 7 of the buffer 4. Data communication between thesystems system 2 is written in thestorage area 7 and after being read out is made available to asystem 3 overline 6. Self-evidently, the reverse is also possible, in whichcase system 3 transmits the data tosystem 2. In a specific embodiment to be described hereinafter, the writing and reading of information in thememory area 7 may even be performed simultaneously by the twosystems - The communication between the two
systems clock generators systems clock generators systems clock generator storage area 7. - The
storage area 7 comprises, for example, one or two rows of memory locations a1 to an and b1 to bn respectively. First the case will be described where the buffer 4 comprises a single row of memory locations a1 to an. The drawing Figure diagrammatically shows the case where n=8. - Addressing
units address counters lines systems address counters clock generators systems - In the latter case the clock information can be recovered by regenerating the transmitted data.
- Assuming that
system 2 wishes to transmit data tosystem 3, the actual data transmission will be effected bit-by-bit, generally under the control of a suitable protocol. The information transmitted bit-by-bit overline 5 is written in a memory location, for example, a7, for which case the value of 7 will be stored in theaddress counter 12. The buffer 4 is a cyclic memory and structured as a ring memory. Once the information has been written in memory location a7, theaddress counter 12 is incremented in response to the clock signal received fromsystem 2, after which memory location a8 is filled with information conveyed overline 5. This process will be continued while, for example, memory location a3 can be read out simultaneously. In that case the address counter 13 stores the value of 3. When the information at memory location a3 is read out, the information is made available toline 6 and is thus received bysystem 3. In this fashion the information previously written in memory location a3 by thesystem 2 is received insystem 3 after some time. On the other hand, ifsystem 3 wishes to transmit information tosystem 2, the operation of the system is similar, with the addressing of the relevant memory location of the transmittingsystem 3 being effected by means of the pointers stored in theaddress counter 13 and the addressing of the memory location ofsystem 2 is effected by means of the pointers ofaddress counter 12. As long as reading and writing operations are performed with the aid of pointers at places which do not overlap, the information transmission will be unaffected. However, in the case of frequency oscillations, for example, occurring as a result of temperature variations or the like, there will be differences between the read and write speeds and the mutual speeds with which the pointers are changed will no longer be substantially equal. In that case it may happen that information is written in a memory location and that from the same location information should be read out. This situation is monitored by means of an address distance monitoring means 14 connected to the addressingunits address counters - If the memory location at which the collision between the writing and reading of information is designated pc, and the number of memory locations of
memory area 7 is designated n, the difference between the pointers of theaddress counters address counters memory location 6, and n=8, the new pointer becomes equal to 2, so that the pointers end up a maximum distance apart. The chance that in such a case phase deviations between the clock signals of theclock generators - When collision is detected in practice, the pointers of the
address counters - In a second embodiment the
storage area 7 of the buffer 4 comprises two aforedescribed rows a and b having cyclically numbered memory locations a1 to an and b1 to bn. In one row, for example row a, information of, for example,system 2 is written in, for example, memory location a7, while information is read out from the corresponding location b7. In thatcase memory location 3 will be addressed by addressingunit 11 comprisingaddress counter 13, while information is read out from memory location a3 and a few instants later information originating fromsystem 3 is written in memory location b3. In this fashion the transmission capacity of thebuffer 3 is doubled. The control logic necessary for this purpose is accommodated in acontrol circuit 15 connected to the two addressingunits control circuit 15 which includes the logic necessary for controlling the second row of memory locations present is deemed to be known to the expert. - If the pointers of the address counters 12 and 13 are changed in such a way that one of them is reset to a fixed initial position, for example, 1 in the present case once they have been differentiated after collision, it will be possible to restore the byte synchronisation in a simpler manner if the byte synchronisation in the data control protocol has been lost, because the restoration of lost byte synchronisation necessitates bringing back the relevant read and write pointers to fixed initial positions.
-
- data communication system
- 1
- digital systems
- 2, 3
- buffer
- 4
- lines
- 5, 6
- storage area
- 7
- clock generators
- 8, 9
- addressing units
- 10, 11
- address counters
- 12, 13
- address distance monitoring means
- 14
- control circuit
- 15
Claims (4)
- Buffer for temporary storage of digital information in memory locations having n cyclically successive addresses, which information is transmitted between two digital systems coupled to each other through the buffer, which systems comprise each a clock generator, there being provided addressing units associated to each of the systems, comprising each an address counter, which addressing units are used for addressing while the information is being written in the memory locations of the buffer on a first time base determined by the clock generator of one system and for addressing while the information is being read out on a second time base determined by the clock generator of the other system, which second time base substantially corresponds to the first time base, characterized in that the buffer comprises two rows of cyclically numbered memory locations and the buffer includes a control circuit coupled to the addressing units, which control circuit is arranged in such a manner that during the addressing operation either system writes information in a memory location in one row and reads information from the corresponding memory location in the other row, whereas the other system reads the information from the memory location in one row and writes the information in the corresponding memory location in the other row.
- Buffer as claimed in Claim 1, characterized in that it comprises an address distance monitoring means connected to the addressing units for creating a difference between the address counts (pointers) of the address counters when equality between the address counts (pointers) of the address counters is detected, which address distance monitoring means is arranged in such a way that the distance between the pointers of the address counters is made equal to n:2.
- Buffer as claimed in Claim 2, characterized in that the pointers of the address counters are influenced in such a way that one of the pointers is set at to a fixed initial position in the buffer after the address distance monitoring means has detected equality.
- Data communication system comprising two or more digital systems mutually exchanging information through a buffer as claimed in one of the Claims 1 to 3 connected to the systems.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL9002426A NL9002426A (en) | 1990-11-08 | 1990-11-08 | ELASTIC BUFFER MEMORY. |
NL9002426 | 1990-11-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0485021A1 true EP0485021A1 (en) | 1992-05-13 |
EP0485021B1 EP0485021B1 (en) | 2001-01-10 |
Family
ID=19857936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91202821A Expired - Lifetime EP0485021B1 (en) | 1990-11-08 | 1991-10-31 | Elastic buffer |
Country Status (5)
Country | Link |
---|---|
US (1) | US5293409A (en) |
EP (1) | EP0485021B1 (en) |
JP (1) | JPH04267431A (en) |
DE (1) | DE69132506D1 (en) |
NL (1) | NL9002426A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996021897A1 (en) * | 1995-01-11 | 1996-07-18 | Telefonaktiebolaget Lm Ericsson (Publ) | A data transmission system |
EP0868081A1 (en) * | 1995-12-25 | 1998-09-30 | Nec Corporation | Clock phase synchronizing circuit |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0525221B1 (en) * | 1991-07-20 | 1995-12-27 | International Business Machines Corporation | Quasi-synchronous information transfer and phase alignment means for enabling same |
US5418910A (en) * | 1992-05-05 | 1995-05-23 | Tandy Corporation | Dual buffer cache system for transferring audio compact disk subchannel information to a computer |
CA2106271C (en) * | 1993-01-11 | 2004-11-30 | Joseph H. Steinmetz | Single and multistage stage fifo designs for data transfer synchronizers |
KR0177733B1 (en) * | 1994-08-26 | 1999-05-15 | 정장호 | Clock sync. circuit of data transmitter |
JP2000031948A (en) * | 1998-07-13 | 2000-01-28 | Fujitsu Ltd | Clock transfer device |
US6594325B1 (en) | 1999-09-08 | 2003-07-15 | Cypress Semiconductor Corp. | Circuitry, architecture and method(s) for synchronizing data |
US6553503B1 (en) * | 1999-09-08 | 2003-04-22 | Cypress Semiconductor Corp. | Circuitry, architecture and method(s) for synchronizing data |
US6597707B1 (en) | 1999-09-08 | 2003-07-22 | Cypress Semiconductor Corp. | Circuitry, architecture and methods for synchronizing data |
US6738917B2 (en) * | 2001-01-03 | 2004-05-18 | Alliance Semiconductor Corporation | Low latency synchronization of asynchronous data |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2048734A1 (en) * | 1970-10-03 | 1972-04-06 | Sel | Control method and circuit arrangement for telecommunications, in particular telephone switching networks |
US3867579A (en) * | 1973-12-21 | 1975-02-18 | Bell Telephone Labor Inc | Synchronization apparatus for a time division switching system |
EP0041429A1 (en) * | 1980-05-19 | 1981-12-09 | ETAT FRANCAIS repr. par le Secrétaire d'Etat aux Postes & Télécommunications (Centre National d'Etudes des Télécommunications) | Process and device for the synchronization of digital signals |
FR2583238A1 (en) * | 1985-06-11 | 1986-12-12 | Applic Electro Tech Avance | Plesiochronous digital transmission device with expanded buffer memory |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3569632A (en) * | 1967-08-15 | 1971-03-09 | Ultronic Systems Corp | Synchronous digital multiplex communication system including switchover |
DE3416610A1 (en) * | 1984-05-05 | 1985-11-07 | Philips Patentverwaltung Gmbh, 2000 Hamburg | BUFFER MEMORY FOR AN INPUT LINE OF A DIGITAL SWITCHING CENTER |
-
1990
- 1990-11-08 NL NL9002426A patent/NL9002426A/en not_active Application Discontinuation
-
1991
- 1991-10-31 DE DE69132506T patent/DE69132506D1/en not_active Expired - Lifetime
- 1991-10-31 EP EP91202821A patent/EP0485021B1/en not_active Expired - Lifetime
- 1991-11-07 JP JP3291340A patent/JPH04267431A/en active Pending
- 1991-11-07 US US07/789,224 patent/US5293409A/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2048734A1 (en) * | 1970-10-03 | 1972-04-06 | Sel | Control method and circuit arrangement for telecommunications, in particular telephone switching networks |
US3867579A (en) * | 1973-12-21 | 1975-02-18 | Bell Telephone Labor Inc | Synchronization apparatus for a time division switching system |
EP0041429A1 (en) * | 1980-05-19 | 1981-12-09 | ETAT FRANCAIS repr. par le Secrétaire d'Etat aux Postes & Télécommunications (Centre National d'Etudes des Télécommunications) | Process and device for the synchronization of digital signals |
FR2583238A1 (en) * | 1985-06-11 | 1986-12-12 | Applic Electro Tech Avance | Plesiochronous digital transmission device with expanded buffer memory |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996021897A1 (en) * | 1995-01-11 | 1996-07-18 | Telefonaktiebolaget Lm Ericsson (Publ) | A data transmission system |
US6009107A (en) * | 1995-01-11 | 1999-12-28 | Telefonaktiebolaget Lm Ericsson | Data transmission system |
EP0868081A1 (en) * | 1995-12-25 | 1998-09-30 | Nec Corporation | Clock phase synchronizing circuit |
US5856851A (en) * | 1995-12-25 | 1999-01-05 | Nec Corporation | Clock phase synchronizing circuit |
Also Published As
Publication number | Publication date |
---|---|
US5293409A (en) | 1994-03-08 |
JPH04267431A (en) | 1992-09-24 |
DE69132506D1 (en) | 2001-02-15 |
EP0485021B1 (en) | 2001-01-10 |
NL9002426A (en) | 1992-06-01 |
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