EP0609392A1 - Soi cmos device having body extension for providing sidewall channel stop and body tie - Google Patents
Soi cmos device having body extension for providing sidewall channel stop and body tieInfo
- Publication number
- EP0609392A1 EP0609392A1 EP92924126A EP92924126A EP0609392A1 EP 0609392 A1 EP0609392 A1 EP 0609392A1 EP 92924126 A EP92924126 A EP 92924126A EP 92924126 A EP92924126 A EP 92924126A EP 0609392 A1 EP0609392 A1 EP 0609392A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- region
- mesa
- source
- extension
- surface portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 34
- 210000000746 body region Anatomy 0.000 claims description 40
- 230000005669 field effect Effects 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000004020 conductor Substances 0.000 claims description 6
- 230000001939 inductive effect Effects 0.000 claims 5
- 238000000034 method Methods 0.000 claims 5
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 239000011810 insulating material Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 230000005865 ionizing radiation Effects 0.000 abstract description 10
- 239000000463 material Substances 0.000 abstract description 6
- 239000010409 thin film Substances 0.000 abstract description 6
- 229910052594 sapphire Inorganic materials 0.000 abstract description 4
- 239000010980 sapphire Substances 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract description 3
- 108091006146 Channels Proteins 0.000 abstract 6
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 239000007943 implant Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
- H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates in general to semiconductor devices and is particularly directed to an SOS/SOI architecture, the
- the present invention further provides an asymmetric sidewall channel stop structure in opposite end portions of the 10 source region, thereby preventing ionizing radiation-induced inversion of the sidewalls of the P-type body/channel region.
- a conventional N-channel SOI/SOS thin film MOS transistor structure is typically comprised of a semiconductor (silicon) mesa layer 11, which is disposed atop a substrate-supported dielectric (silicon dioxide) layer 12 and the sidewall perimeter of which is bounded by air or an oxide dielectric layer, shown at 13.
- 25 semiconductor mesa structure contains a P-type body/channel region 14 disposed between and immediately contiguous with respective N+ source and drain regions 16 and 18. Overlying the (P-type) channel/body region 14 and extending onto the surrounding support substrate, either co-planar with the top of the mesa as shown in Figure 2 in the
- the mesa is bounded by an oxide dielectric layer 13, or stepped down to the surface of dielectric layer 12 in the case where the mesa is bounded by air isolation, is a doped polysilicon gate layer 21, insulated from the semiconductor material of the mesa by thin dielectric layer (e.g. oxide) 22.
- a doped polysilicon gate layer 21 insulated from the semiconductor material of the mesa by thin dielectric layer (e.g. oxide) 22.
- the surface of P-doped material (here the P-typ channel/body region 14) is susceptible to inversion in the presenc of ionizing radiation, there is the danger of a leakage path o 'parasitic' channel being induced along the body/channel sidewall 23, 24 between the source and drain regions 16, 18.
- th inability of some manufacturing processes to accurately control th channel doping along the edges of the device (beneath the polysilico gate overlay 21)
- the lack of control of electrostatic charg build-up along surface portions 25, 27 of dielectric layer 13 that is immediately adjacent to P-type silicon body 14 may cause the device to suffer extraordinary current leakage in its OFF state.
- Another problem associated with this type of architecture is the fact that the body/channel region 14 of the transistor, being situated atop a dielectric layer, is not readily accessible to be terminated to either a Vdd node or, in the case of an N-channel device, a Vss node, so that the potential of the body/channel region effectively r floats', which can severely degrade the performance of the transistor (e.g. subject the saturation region of the device to the 'kink' effect and additionally by permitting parasitic NPN devices to be turned on) .
- the above drawbacks of conventional SOI/SOS thin film MOS mesa architectures are effectively obviated by extending the body/channel region beyond the source and drain regions and also increasing the impurity concentration at a selected portion (e.g. an end portion) of the extended body region, so as to provide both a body tie access location which enables the body/channel region to be terminated to a prescribed bias voltage (e.g. Vss) , and a channel stop region that is effective to functionally interrupt a current leakage path or 'parasitic 7 N- channel that may be induced along sidewall surface of the P-type material of the body/channel region.
- a prescribed bias voltage e.g. Vss
- the problem of the inducement of a parasitic sidewall channel within an SOI/SOS field effect transistor architecture is successfully addressed by extending the body/channel region beyond endwall 5 terminations of source and drain regions that are contiguous with the body/channel region, so as to form a pair of body/channel extension regions at opposite ends of the device.
- the thin film, field effect transistor being an SOI/SOS mesa structure, includes a semiconductor mesa having a body/channel region of a first conductivity type (e.g.
- an underlying dielectric layer e.g. silicon dioxide, sapphire
- a second conductivity type e.g. N-type for an N-channel device
- a drain region of the second conductivity type (N-type) is formed in the mesa on a third surface portion of the substrate, spaced apart from the second surface portion by the first surface portion therebetween, and being immediately contiguous with the first surface
- a dielectrically insulated (polysilicon) gate layer overlies the body/channel region of the mesa.
- 25 drain regions serves to increase the effective channel length to a value greater than the case where the (P-type) body/channel region terminates 'flush' with the (N+) source and drain regions.
- the channe stops of the extension regions are configured to provide additiona functionality, specifically to provide body tie contact regions, s that the body/channel region may be terminated at a prescribed bia voltage (e.g. Vss, which will substantially reduce parasitic curren leakage during the transistor 7 s OFF state).
- the problem of ionizing radiation-induced inversion of the sidewalls of the P-type body/channel region is addressed by means of an asymmetric sidewall channel stop structure formed in opposite end portions of one of the source and drain regions.
- first and second end portions of one (e.g. the N+ source region) of (N+) source and drain mesa regions which are contiguous with the (P) body/channel mesa region and extend to sidewall edges of the selected one of the source and drain mesa regions, are heavily overdoped with impurities (e.g. P+) of the same conductivity type as the body/channel region, thereby forming a demiurgic channel stop structure having first and second mesa sidewall channel stops immediately adjacent to the ends of the (P) body/channel region and which extend throughout the thickness of the selected source or drain region.
- impurities e.g. P+
- the heavy (P+) overdoping ensures that the parasitic sidewall threshold is higher than any possible negative threshold shift that might occur as a result of the incidence of ionizing radiation. Even in the case of a very thick dielectrically filled trench isolation structure where the potential charge generation volume is relatively large, the sidewall remains adequately enhancement mode. Since the P+ channel stops are disposed in the same N+ region, they are physically and electronically separated from the N+ drain/source region on the opposite side of the body/channel region over which the polysilicon gate is formed. Thus, both P+/N+ junctions formed between the high impurity concentration (P+) channel stops and the (N+) material in which they are introduced are into the source region and are always at the same potential, so that the value of reverse bias breakdown voltage is not of concern.
- Figures 1 and 2 are respective diagrammatic top and side views of a conventional N-channel SOI/SOS thin film MOS transistor structure
- Figures 3 and 4 are respective diagrammatic top and side views of an MOS transistor structure having body/channel extension regions in accordance with a first embodiment of the present invention
- Figures 5 and 6 are respective diagrammatic top and side views of an MOS transistor structure having body/channel extension regions in accordance with a second embodiment of the present invention
- Figures 7 and 8 are respective diagrammatic top and side views of an MOS transistor structure having body/channel extension regions in accordance with a third embodiment of the present invention
- Figures 9 and 10 are respective diagrammatic isometric and side views of an asymmetric sidewall channel stop structure in accordance with a fourth embodiment of the present invention.
- FIGS 11 - 16 show conventional MOS channel stop architectures.
- FIGS 3 and 4 respective top and side view of a first embodiment of the present invention show how th conventional thin mesa transistor structure of Figures 1 and 2 i modified such that the body/channel region 14 extends beyond it interfaces with each of the source and drain regions, as shown b body/channel extension regions or segments 31, 32.
- Regions 31, 3 have a prescribed length x and a width y within the dimensions of th gate layer 21 and serve to increase the effective channel length o body/channel region 14 to a value greater than the case where th body/channel region terminates 'flush 7 with source and drain region 16, 18 (as shown in Figure 1) .
- Figures 5 and 6 diagra matically show respective top and sid view of a second embodiment of the invention, in which respective high impurity concentration 'tab 7 regions 41, 42 are introduced to overlap end portions 43, 44 of (P-type) body/channel extension regions 31, 32 so that the impurity concentration of these end portions of the extension regions is increased relative to the impurity concentration of that portion 17 of the body/channel region 14 disposed between the source and drain regions, thereby forming a pair of P+- channel stops.
- This relatively high impurity concentration of the channel stop tab regions 41, 42 insures that the parasitic sidewall threshold is higher than any possible negative threshold shift which might be induced by ionizing radiation.
- These more heavily doped (P+) tab regions 41, 42 of the extension regions 31, 32 are spaced apart from the endwall edges of source and drain regions 16, 18 by respective portions 51, 52 of the extension regions 31, 32 of the same doping concentration as the body/channel region 14 itself, so that the more heavily doped (P+) channel stop tab regions 41, 42 do not form (very low breakdown voltage) P+/N+ junctions with the source and drain regions 16, 18.
- the source and drain regions may be formed by an N+ implant using an implant mask the geometry of which overlaps polysilicon gate layer 21, as shown at 55 in Figure 6.
- the channel stops of the extension regions are configured to provide additional functionality, specifically to provide body tie contact regions, so that the body/channel region may be terminated at a prescribed bias voltage (e.g. Vss, which will substantially reduce parasitic sidewall originating current leakage during the transistor 7 s OFF state) .
- a prescribed bias voltage e.g. Vss, which will substantially reduce parasitic sidewall originating current leakage during the transistor 7 s OFF state
- heavily doped 'bodytab' portions 61, 63 of P-type body/channel extension regions 31, 32 protrude to the side of or transverse to the lengthwise direction of the body/channel region 14 and its polysilicon gate overlay 21, so that the pair of heavily doped (P+) bodytabs 61, 63 project outwardly from beneath and to the side of the gate layer 21, thereby forming a symmetrical, bidirectional transistor geometry and facilitating the electrical connection of a bias voltage rail to the body/channel region from either end of the device.
- heavily doped bodytab regions 61, 63 are spaced apart from the end sidewalls of N+ source and drain regions 16, 18 by extension portions 51, 52, so that the more heavily doped (P+) channel stop tab regions 61, 62 do not form (low reverse breakdown voltage) P+/N+ junctions with the source and drain regions 16, 18.
- the problem of ionizing radiation-induced inversion of the sidewalls of the P-type body/channel region is addressed by means of an asymmetric sidewall channel stop structure formed in opposite end portions of one of the source and drain regions.
- first and second end portions 71, 72 of one of N+ source and drain mesa regions are heavily overdoped with impurities of the same conductivity type as the body/channel region.
- these P+ end portions 71 and 72 are located such that they are contiguous with the (P) body/channel mesa region 14 and extend to sidewall edges 75, 76 of the source mesa region 16, thereby forming a demiurgic channel stop structure havin first and second mesa sidewall channel stops 81, 82 immediatel adjacent to ends 83, 84 of the (P) body/channel region 14 and whic extend throughout the thickness of the selected region (source regio 16) .
- the P+ implant photomask used to define the geometry of channel stop regions 81, 82 is sized and located such that it partiall overlaps (e.g. terminates along the centerline 90 of) polysilicon gate 21 and also extends beyond the side edge of the gate onto the source region, so as create a partially self-aligned P+ channel stop structure that is contiguous with the P-type body/channel region. Terminating the P+ channel stop implant masking photoresist pattern over polysilicon gate layer 21 guarantees that the P+ implant will not fall off the gate onto either the source or drain region side under statistically controlled misalignment conditions.
- Channel stop regions 71, 72 are doped with a P-type impurity during both a lightly doped P source/drain region implant and P+ surface source/drain implant operations, such that the composite doping profile of these regions is sufficient to inhibit sidewall inversion well into the megarad total dose range.
- the magnitude of P+ implant energy is predetermined to be sufficient to cause a pair of P source and drain regions of an associated complementary P-channel device to bottom out against insulator support layer 12. As a consequence, the P+ implant is similarly effective across the entire sidewall interface surface in the formation of the channel stops 81, 82.
- this heavy (P+) overdoping ensures that the sidewalls 83, 84 of the mesa adjacent to the location where gate electrode 21 exits the mesa are P-doped to the magnitude necessary to prevent sidewall inversion.
- the heavy overdoping also ensures that the parasitic sidewall threshold is higher in magnitude than any possible threshold shift that might occur as a result of the incidence of ionizing radiation. Even in the case of a very thick dielectrically filled trench isolation structure where the potential charge generation volume is relatively large, the sidewall remains adequately enhancement mode. Since P+ channel stops 81, 82 are disposed in the same N+ source region 16, they are physically and electronically separated from the N+ drain region 18 on the opposite side of body/channel region 14 over which polysilicon gate 21 is formed.
- Conductive material such as a layer of low resistance silicide 95 is formed atop each of gate layer and source and drain regions, as shown in Figure 9.
- Silicide layer 95 conductively bridges channel stop regions 81, 82 and source region 16, so that the body region 14 is inherently shunted to source region 16.
- P+/N+ junctions 91, 92 formed between the high impurity concentration P+ channel stops 81, 82 and the N+ material of source region 16 in which they are introduced are at the same potential, so that the reverse bias voltage characteristics of the diode are of no consequence.
- This bridging silicide layer 95 also eliminates the need for additional contacts and metalization, such as those shown in the structure of Figure 14, which employs N+ diffusions spaced inwardly away from the mesa edge. In fact, for small transistors, a single, minimum sized source contact to silicide layer 95 will serve to maintain the necessary bias on both sidewall channel stops 81, 82, while also providing bias to the body/channel region 14 and the source region 16. It will also be appreciated that conventional configuration employing full or partial guardrings ( Figure 15) and circular gat structures ( Figure 16) require significantly larger chip area t implement than do the asymmetric device of Figures 9 and 10, and mak high density memories and other digital circuits more difficult t design and manufacture.
- guardring structures at least on additional lithographic and ion implantation step is required prio to- the deposition of the gate electrode.
- i asymmetric device of the present invention no additional fabricatio operations, photomasking, or ion implantation steps are required.
Abstract
Une structure mesa d'un transistor MOS à couches minces silicium sur isolant/silicium sur saphire possède une zone substrat/canal (14) qui s'étend au-delà des zones de la source et du drain (16, 18) et la concentration d'impuretés est plus grande dans une partie sélectionnée (par exemple une partie terminale) du prolongement du substrat (31, 32), de façon qu'elle puisse servir à la fois d'emplacement d'accès de raccordement du substrat, ledit emplacement permettant le raccordement de la zone substrat/canal (14) à une tension de polarisation prescrite (par exemple Vss), et de zone d'arrêt de canal (41, 42), ladite zone pouvant, de façon fonctionnelle, interrompre un passage de courant de fuite ou un canal de type N parasite qui peut être induit le long de la surface de la paroi latérale du matériau de type P de la zone substrat/canal (14). Dans un autre mode de réalisation, l'inversion, induite par rayonnement ionisant, des parois latérales (83, 84) de la zone substrat/canal de type P (14) est empêchée par une structure d'arrêt de canal de parois latérales asymétrique (71, 72) formée dans les parties terminales opposées de la zone de la source (16).A mesa structure of a silicon-on-insulator/silicon-on-sapphire thin-film MOS transistor has a substrate/channel region (14) that extends beyond the source and drain regions (16, 18) and the concentration of impurities is greater in a selected part (for example an end part) of the extension of the substrate (31, 32), so that it can serve both as a location of access for connection of the substrate, said location allowing the connection of the substrate/channel zone (14) to a prescribed bias voltage (for example Vss), and of the channel stop zone (41, 42), said zone being able, in a functional manner, to interrupt a passage of leakage current or a parasitic n-type channel which may be induced along the surface of the side wall of the p-type material of the substrate/channel region (14). In another embodiment, ionizing radiation-induced inversion of the sidewalls (83, 84) of the P-type substrate/channel zone (14) is prevented by an asymmetric sidewall channel stopper structure (71, 72) formed in opposite end portions of the source region (16).
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/780,251 USH1435H (en) | 1991-10-21 | 1991-10-21 | SOI CMOS device having body extension for providing sidewall channel stop and bodytie |
PCT/US1992/009096 WO1993008603A1 (en) | 1991-10-21 | 1992-10-21 | Soi cmos device having body extension for providing sidewall channel stop and body tie |
US780251 | 2001-02-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0609392A1 true EP0609392A1 (en) | 1994-08-10 |
Family
ID=25119055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP92924126A Withdrawn EP0609392A1 (en) | 1991-10-21 | 1992-10-21 | Soi cmos device having body extension for providing sidewall channel stop and body tie |
Country Status (4)
Country | Link |
---|---|
US (1) | USH1435H (en) |
EP (1) | EP0609392A1 (en) |
JP (1) | JP2002516649A (en) |
WO (1) | WO1993008603A1 (en) |
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Also Published As
Publication number | Publication date |
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JP2002516649A (en) | 2002-06-04 |
USH1435H (en) | 1995-05-02 |
WO1993008603A1 (en) | 1993-04-29 |
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