EP0739089A2 - Spread spectrum clock generator - Google Patents
Spread spectrum clock generator Download PDFInfo
- Publication number
- EP0739089A2 EP0739089A2 EP96302821A EP96302821A EP0739089A2 EP 0739089 A2 EP0739089 A2 EP 0739089A2 EP 96302821 A EP96302821 A EP 96302821A EP 96302821 A EP96302821 A EP 96302821A EP 0739089 A2 EP0739089 A2 EP 0739089A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- clock
- counter
- signal
- spread spectrum
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/0966—Modifications of modulator for regulating the mean frequency using a phase locked loop modulating the reference clock
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B29/00—Generation of noise currents and voltages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/0916—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop
- H03C3/0925—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop applying frequency modulation at the divider in the feedback loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/0941—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation at more than one point in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2215/00—Reducing interference at the transmission system level
- H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2215/00—Reducing interference at the transmission system level
- H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
- H04B2215/067—Reduction of clock or synthesizer reference frequency harmonics by modulation dispersion
Definitions
- the present invention relates to the field of digital circuits, and, more particularly, to a clock circuit having reduced measurable electromagnetic interference (EMI) emissions.
- EMI electromagnetic interference
- a clock signal permits the precise timing of events in the microprocessor, for example.
- Typical microprocessors may be supervised or synchronized by a free-running oscillator, such as driven by a crystal, an LC-tuned circuit, or an external clock source. Clocking rates up to and beyond 40 MHz are common in personal computers.
- the parameters of a clock signal are typically specified for a microprocessor and may include minimum and maximum allowable clock frequencies, tolerances on the high and low voltage levels, maximum rise and fall times on the waveform edges, pulse-width tolerance if the waveform is not a square wave, and the timing relationship between clock phases if two-clock phase signals are needed. (See Electronics Engineers' Handbook, by Fink et al., p. 8-111, 1989.)
- EMI electromagnetic interference
- the spectral components of the EMI emissions typically have peak amplitudes at harmonics of the fundamental frequency of the clock circuit.
- regulatory agencies such as the FCC in the United States, have established testing procedures and maximum allowable emissions for such products.
- the Commission Electrotechnique International Commission International Special Des Perturbations Radiocies (C.I.S.P.R.)
- C.I.S.P.R. Commission Electrotechnique International
- the measured 6 dB bandwidth is a relatively wide 120 kHz.
- digital spread spectrum modulation circuits are preferably used. These circuits are synchronized by resetting a counter which controls the circuit.
- Spread spectrum clock implementations employing a voltage controlled oscillator but not digital control are disclosed in US-A-4,507,796 to Stumfall.
- Digital control circuits of some similarity, not for spread spectrum clock control are disclosed in US-A-3,764,933 to Fletcher et al, US-A-3,962,653 to Basset, US-A-4,943,786 to Cordwell et al, and US-A-5,028,887 to Gilmore.
- Digital FM communication circuits of some similarity are disclosed in US-A-5,272,454 to Ikai et al, US-A-5,301,367 to Heinonen, and US-A-5,329,253 to Ichihara.
- EP-A-0655829 discloses a digital implementation, not shown in the drawings, that has data digitally stored which is applied to an adder and accumulated.
- the output of the accumulator is one input to a phase detector of a phase locked loop, the other input being a divided feedback from the output of the voltage controlled oscillator of the phase locked loop.
- the output of that oscillator is divided and used as the spread spectrum clock signal.
- No disclosed embodiment of the present invention employs an adder or accumulator.
- a clock circuit including an oscillator for generating a reference frequency signal, and spread spectrum clock generating means for generating a spread spectrum clock output signal having a fundamental or centre frequency and reduced amplitude EMI spectral components at harmonics of the fundamental frequency.
- the spread spectrum clock generating means preferably includes clock pulse generating means for generating a series of clock pulses, and spread spectrum modulating means for modulating the clock pulse generating means to broaden and flatten amplitudes of EMI spectral components which would otherwise be produced by the clock pulse generating means. A starting point in such modulation is precisely controllable to facilitate synchronization.
- the clock pulse generating means if unmodulated, would typically produce generally rectangular or trapezoidal electrical pulses which, in turn, would generate corresponding impulse-shaped EMI spectral components at harmonics of the fundamental frequency.
- the spread spectrum modulating means reduces the peak amplitude of the EMI spectral components that would otherwise be produced. Accordingly, expensive shielding or other EMI suppression techniques may be reduced or eliminated in an electronic device including the spread spectrum clock generating circuit of the present invention.
- the spread spectrum clock generating circuit may find wide application in a number of electronic devices, particularly those including a microprocessor or microcontroller, such as a personal computer.
- the spread spectrum modulating means preferably includes frequency modulating means for frequency modulating the clock pulse generating means.
- the frequency modulating means in turn, preferably includes profile modulating means for frequency modulating the clock pulse generating means with a periodic waveform having a predetermined period and a predetermined frequency deviation profile as a function of the predetermined period.
- profile modulating means for frequency modulating the clock pulse generating means with a periodic waveform having a predetermined period and a predetermined frequency deviation profile as a function of the predetermined period.
- the clock pulse generating means preferably includes a phase locked loop as is commonly used in a conventional clock generating circuit.
- the frequency modulation means may be implemented by a programmable modulating generator which can produce a predetermined profile for the frequency deviation.
- the frequency modulating means is preferably capable of modulating the clock pulse generating means with a periodic waveform having a period of less than about 500 microseconds, that is, the frequency of modulation is desirably greater than about 2 kHz.
- an electronic device such as the schematically illustrated personal computer 10, may benefit by having reduced measurable EMI spectral component emissions provided by a spread spectrum clock generator 14 (SSCG) according to the invention.
- a reference frequency generator 15 such as a piezoelectric crystal driven at its resonant frequency by a suitable driver or oscillator circuit, provides a reference frequency for the SSCG 14.
- the illustrated personal computer 10 also includes a display 12 and a keyboard 13.
- a number of electronic devices incorporating microprocessors or other digital circuits requiring a clock signal for synchronization may also desirably incorporate the SSCG 14.
- computer printers may also desirably include the SSCG 14.
- the SSCG 14 generates the spread spectrum output clock signal by frequency modulating a typical clock signal including a series of trapezoidal or generally rectangularly-shaped electrical clock pulses.
- the modulation reduces the spectral amplitude of the EMI components at each harmonic of the clock when compared to the spectrum of the same clocking signal without modulation.
- Fig.2 is a schematic representation of this effect where the spectral amplitude versus frequency at a harmonic (NF) is indicated by the plot labelled M.
- the spectrum at the same harmonic of a standard clock signal is given as an impulse function labelled I.
- the spectrum of the SSCG output clock signal at the same harmonic ideally assumes a trapezoidal shape as illustrated by the plot labelled T.
- the spectral "width" of the spread spectrum output clock signal at a harmonic is greater than the width of the standard non-modulated clock signal, the maximum amplitude for the harmonic is reduced.
- the amplitude of the spread spectrum modulated harmonic will not be uniform, but will exhibit some peaking near the centre frequency and at the edges as illustrated by the plot M.
- the SSCG 14 includes profile modulation means for frequency modulating the clock pulse generating means with a periodic waveform having a predetermined period and a predetermined frequency deviation profile as a function of the predetermined period.
- the modulation profiles described herein produce relatively optimized flat spectral amplitudes at each harmonic.
- the preferred profiles are more complicated than a simple sine wave in order to thereby reduce the measurable spectral peaks of the EMI components.
- the present invention converts narrow band harmonics into broadband signals that significantly reduce the measured emissions for the FCC and other regulatory bodies worldwide. These emission reductions may permit corresponding cost reductions of about $20 or more per product, as compared to the cost of conventional measures to suppress or shield EMI emissions.
- Fig. 3 illustrates a typical profile of the frequency deviation versus time as may be used within the SSCG 14.
- the maximum deviation illustrated is 100 kHz.
- This maximum frequency deviation is desirably programmable via a serial link with an upper limit of the maximum deviation being preferably about 250 kHz for typical current applications. However, depending on the application, the maximum deviation may be much greater that 250 kHz as would be readily understood by those skilled in the art.
- a standard, non-modulated clock signal may be obtained by programming the maximum deviation to 0.
- the frequency of the signal modulating profile shown in Fig. 3 is 30 kHz. Significant peak amplitude reduction may also be achieved where the frequency is above 2 kHz, that is, where the period of the modulating waveform or profile is less than about 500 microseconds. This frequency is also desirably programmable via a serial link or may be fixed dependent on the application.
- the modulating profile illustrated is a linear combination of a standard triangular wave and its cubic. The values of the profile are given in TABLE 1 of EP-A-0655829.
- Fig. 4 several preferred ranges of profiles of frequency deviation are illustrated.
- the profiles are expressed as a percentage of frequency deviation versus a percentage of the period (%Period) of the periodic waveform.
- the outermost range or envelope is illustrated by the dotted lines labelled F 1 , F 2 in the second quadrant II, that is, between 0% and 25% of the period.
- Straightforward symmetry defines the boundaries in the other indicated quadrants as described. Accordingly, those of skill in the art may readily implement and scale the ranges for a desired application.
- the dotted lines may be defined mathematically by predetermined upper and lower bounds for the second quadrant II.
- the upper bound F 1 is defined by 100% -1+ - % period 25 2 +4 % period 25 +.973
- the lower bound F 2 is defined by 50% % period 25 10 .
- a more preferred profile range is indicated by the dashed lines indicated in Fig. 4.
- this profile is defined by an upper bound F 3 and a lower bound F 4 .
- the upper bound F 3 is defined in quadrant II by 100% % period 25
- the lower bound is defined in quadrant II by 100% % period 25 3 .
- the solid line P 1 of Fig. 4 illustrates the linear combination of a triangular waveform and its cubic. More particularly, this profile is defined quadrant II by F 5 which is equal to 100%[0.45(%Period/25) 3 + 0.55(%Period/25)].
- the solid line is defined in the other quadrants as follows:
- Fig. 5 illustrates yet another embodiment of a profile for the frequency deviation modulation which may be scaled to fit within the outermost profile defined by F 1 and F 2 as would be readily appreciated by those of skill in the art.
- a circuit embodiment for the SSCG 14 is described.
- the block diagrams are similar to several conventional phase locked loop (PLL) frequency synthesizer chips; however, a modulation section is added which includes a programmable modulation generator in several embodiments, or an analog modulation generator in other embodiments.
- the modulation is fed into a voltage controlled oscillator (VCO) or oscillator tank circuit to give the desired modulation index.
- VCO voltage controlled oscillator
- the SSCG 14 may desirably be programmable via an I 2 C serial bus or select lines to allow variation of the centre frequency, maximum frequency deviation and modulation frequency.
- a single +5V supply, minimal external circuitry and a crystal will produce a TTL and CMOS compatible output with controlled rise and fall times.
- all inputs are standard TTL compatible.
- Y1 22 is a piezoelectric crystal used with an oscillator circuit 24 to generate a stable clock pulse train or unmodulated clock signal.
- a first programmable counter 26 divides the unmodulated clock signal by an integer number (M).
- a voltage controlled oscillator 28 (VCO 1) generates an output clock signal that is proportional to the input voltage from a phase detector 30 through a filter 32.
- a second programmable counter 34 divides the signal from VCO 28 by an integer number (N).
- Counters 26 and 34 are the two inputs to phase detector 30.
- Phase detector 30 and filter 32 generate an analog signal that is proportional to the errors in phase between the first and second programmable counters 26, 34 respectively. Accordingly, the output for phase detector 30 and filter 32 each represents the oscillator 24 frequency times N/M, when N and M are constant, as they are in the embodiment of Fig. 6.
- VCO 28 is operated as in a standard phase locked loop circuit.
- the spread spectrum modulation is introduced in this embodiment by a ROM 36 having stored therein modulation variation values that are fed into a digital to analog convertor (DAC) 38.
- DAC digital to analog convertor
- An up/down counter 40 is used to index the value of ROM 36, while a third programmable counter 42 sets the modulation frequency.
- a second voltage controlled oscillator (VCO 2) 44 receives an input of the constant output from filter 32 plus the input from DAC 38, which varies the frequency of VCO 44 according to the changes in input from DAC 38.
- VCO 44 is connected through buffer 46 as the spread spectrum clock output.
- the modulation can be brought to a known condition by setting up/down counter 40.
- the input to VCO 44 represents that for the start of a cycle and VCO 44 promptly adjusts to provide a corresponding frequency.
- Element 50 is a reference frequency clock, which may be identical to the combination of elements 22 and 24 in the Fig. 6 embodiment.
- Clock 50 serves as a clock input to count-down counter 52.
- a second input on line 54 to counter 52 is a reset input.
- Counter 52 receives number data from ROM table memory 56, which data is counted down once with each clock signal from clock 50 until counter 52 reaches zero and produces a signal on output line 58. That signal on line 58 is an input signal to up/down counter 60 and phase detector 62.
- Each count change of counter 60 produces a different output, which changes the address to ROM table 56 and thereby applies the count data at that address to counter 52, to again begin a count down to zero by counter 52.
- counter 60 when counter 60 is reset by a signal on line 54, it produces a signal on line 64 suitable as a reset signal of another spread spectrum clock circuit, which may be identical to that of Fig. 7.
- Phase detector 62 and the remaining elements of Fig. 7 are a standard phased locked loop.
- the second input to phase detector 62 is the output of voltage controlled oscillator 66 on line 68 divided by an integral number by a counter 70.
- Phase detector 62 produces a signal proportional to the time difference between leading edges of the signal on line 58 and the signal from counter 70. This output is smoothed by filter 72, as is conventional.
- reference clock 50 steps down counter 52, which has been loaded by ROM table 56.
- the number from table 56 defines a delay before counter 52 reaches zero and issues a signal on line 58. That signal is one input to phase detector 62, while a divided feedback from the output 68 of the phased locked loop is the other.
- the signal from counter 52 on line 58 also steps up/down counter 60.
- the next status of counter 60 defines an output which selects the next location in ROM table 56, thereby entering a different number in counter 52.
- ROM table 56 can directly correspond to the desired change.
- a very simplified and illustrative content might be 17 followed by 14, followed by 10, followed by 6, followed by 3, followed by 0. These are addressed as counter 60 increases from 0 (which addresses the 17) to 5 (which addresses the 0), after which counter 60 would decrement on the next count, so that the next count is 4 (which addresses the 3).
- phase locked loop 62, 72, 66, and 70 may be optimized in various ways. If the inputs on line 58 may be relatively frequent with respect to the frequency band which filter 72 passes, than the output does not closely follow individual changes. In that event the number contents in ROM table 56 might differ somewhat in order to achieve the desired output through filter 72, although the gross change in numbers in ROM table 56 would continue to correspond to the desired spread spectrum pattern. In such event the specific numbers in ROM table 56 will be best determined empirically.
- the clock timing may vary provided certain functions are synchronized to that varying pattern.
- a laser beam is swept across a photoconductor as it is pulsed or not pulsed at the clock times.
- Those clock times may be in a spread spectrum without significant degradation of the printing if each sweep is synchronized to the same point in the spread spectrum.
- a similar problem exists for video displays created by electron beam sweep or similar sweeping.
- the reset input on line 54 provides such synchronization.
- a start-of-sweep signal is conventionally available from a laser printhead (conventionally termed HSync).
- HSync This HSync signal is applied to the line 54. That signal resets counter 60 and counter 52 to zero. This immediately brings the frequency of pulses on line 58 to that defined by the counter 60 being zero and then being stepped as described.
- Phase detector 62 immediately begins to change the frequency of VCO 66 if the other input to phase detector 62 represents a different phase.
- the resetting of counter 60 produces a signal on line 64, which can reset a second spread spectrum clock circuit so that the two spread spectrum clock circuits are synchronized with themselves and with the input on the line 54.
- Fig. 8 is an alternative embodiment which eliminates the counter 70.
- Other elements are numbered the same as the corresponding elements in Fig. 7, as the other difference is in the content of ROM table 56. Since the reference clock is one of the two inputs to phase detector 62, the content of ROM table 56 must be adjusted accordingly. In practice, the exact content of ROM table 56 will be best determined empirically.
- SSCG spread spectrum clock generating circuits
- a standard phase locked loop frequency synthesizer may also be located in the same DIP to provide standard clock signals, if desired.
- the SSCG may also be included internally with a microprocessor or any other digital or analog circuit.
Abstract
Description
- The present invention relates to the field of digital circuits, and, more particularly, to a clock circuit having reduced measurable electromagnetic interference (EMI) emissions.
- Many electronic devices employ microprocessors or other digital circuits which require one or more clock signals for synchronization. A clock signal permits the precise timing of events in the microprocessor, for example. Typical microprocessors may be supervised or synchronized by a free-running oscillator, such as driven by a crystal, an LC-tuned circuit, or an external clock source. Clocking rates up to and beyond 40 MHz are common in personal computers. The parameters of a clock signal are typically specified for a microprocessor and may include minimum and maximum allowable clock frequencies, tolerances on the high and low voltage levels, maximum rise and fall times on the waveform edges, pulse-width tolerance if the waveform is not a square wave, and the timing relationship between clock phases if two-clock phase signals are needed. (See Electronics Engineers' Handbook, by Fink et al., p. 8-111, 1989.)
- Unfortunately, high performance, microprocessor-based devices using leading edge, high speed circuits are particularly susceptible to generating and radiating electromagnetic interference (EMI). The spectral components of the EMI emissions typically have peak amplitudes at harmonics of the fundamental frequency of the clock circuit. Accordingly, many regulatory agencies, such as the FCC in the United States, have established testing procedures and maximum allowable emissions for such products. For example, the Commission Electrotechnique International (Comite International Special Des Perturbations Radioelectriques (C.I.S.P.R.)) has guidelines establishing measurement equipment and techniques for determining compliance with regulations. More particularly, for the frequency band of interest to clock circuits, the measured 6 dB bandwidth is a relatively wide 120 kHz.
- In order to comply with such government limits on EMI emissions, costly suppression measures or extensive shielding may be required. Other approaches for reducing EMI include careful routing of signal traces on printed circuit boards to minimize loops and other potentially radiating structures. Unfortunately, such an approach often leads to more expensive multilayer circuit boards with internal ground planes. In addition, greater engineering effort must go into reducing EMI emissions. The difficulties caused by EMI emissions are made worse at higher processor and clock speeds.
- In certain applications it is necessary to precisely synchronise the period of one clock with that of another. Accordingly, precise control of the modulation of a clock signal can be significant. In the present invention digital spread spectrum modulation circuits are preferably used. These circuits are synchronized by resetting a counter which controls the circuit. Spread spectrum clock implementations employing a voltage controlled oscillator but not digital control are disclosed in US-A-4,507,796 to Stumfall. Digital control circuits of some similarity, not for spread spectrum clock control, are disclosed in US-A-3,764,933 to Fletcher et al, US-A-3,962,653 to Basset, US-A-4,943,786 to Cordwell et al, and US-A-5,028,887 to Gilmore. Digital FM communication circuits of some similarity are disclosed in US-A-5,272,454 to Ikai et al, US-A-5,301,367 to Heinonen, and US-A-5,329,253 to Ichihara.
- EP-A-0655829, also in the name of the present applicant, discloses a digital implementation, not shown in the drawings, that has data digitally stored which is applied to an adder and accumulated. The output of the accumulator is one input to a phase detector of a phase locked loop, the other input being a divided feedback from the output of the voltage controlled oscillator of the phase locked loop. The output of that oscillator is divided and used as the spread spectrum clock signal. No disclosed embodiment of the present invention employs an adder or accumulator.
- In view of the foregoing background, it is therefore an object of the present invention to provide a clock circuit and associated method for generating a clock signal, such as for driving a microprocessor or other digital circuit at relatively high frequencies, while reducing the spectral amplitude of EMI components as measured over a relatively large bandwidth.
- This and other objects, features, and advantages of the present invention are provided by a clock circuit including an oscillator for generating a reference frequency signal, and spread spectrum clock generating means for generating a spread spectrum clock output signal having a fundamental or centre frequency and reduced amplitude EMI spectral components at harmonics of the fundamental frequency. More particularly, the spread spectrum clock generating means preferably includes clock pulse generating means for generating a series of clock pulses, and spread spectrum modulating means for modulating the clock pulse generating means to broaden and flatten amplitudes of EMI spectral components which would otherwise be produced by the clock pulse generating means. A starting point in such modulation is precisely controllable to facilitate synchronization.
- The clock pulse generating means, if unmodulated, would typically produce generally rectangular or trapezoidal electrical pulses which, in turn, would generate corresponding impulse-shaped EMI spectral components at harmonics of the fundamental frequency. The spread spectrum modulating means reduces the peak amplitude of the EMI spectral components that would otherwise be produced. Accordingly, expensive shielding or other EMI suppression techniques may be reduced or eliminated in an electronic device including the spread spectrum clock generating circuit of the present invention. As would be readily understood by those skilled in the art, the spread spectrum clock generating circuit may find wide application in a number of electronic devices, particularly those including a microprocessor or microcontroller, such as a personal computer.
- The spread spectrum modulating means preferably includes frequency modulating means for frequency modulating the clock pulse generating means. The frequency modulating means, in turn, preferably includes profile modulating means for frequency modulating the clock pulse generating means with a periodic waveform having a predetermined period and a predetermined frequency deviation profile as a function of the predetermined period. Several preferred or effective ranges for such modulating periodic waveforms are described later herein. In general, the preferred waveforms are more complicated than a simple sine wave in order to thereby reduce the spectral peak of EMI components by broadening and flattening their shape.
- The clock pulse generating means preferably includes a phase locked loop as is commonly used in a conventional clock generating circuit. The frequency modulation means may be implemented by a programmable modulating generator which can produce a predetermined profile for the frequency deviation. In addition, the frequency modulating means is preferably capable of modulating the clock pulse generating means with a periodic waveform having a period of less than about 500 microseconds, that is, the frequency of modulation is desirably greater than about 2 kHz.
- Certain embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
- Fig. 1 is a schematic block diagram of a personal computer including a spread spectrum clock generating circuit in accordance with an embodiment of the present invention;
- Fig. 2 is a graph illustrating a reduction of peak spectral amplitude of a harmonic of a clock fundamental frequency produced by a spread spectrum clock generating circuit in accordance with an embodiment of the present invention;
- Fig. 3 is a graph illustrating an embodiment of a desired modulation profile for producing a spread spectrum modulated clock signal in accordance with the present invention;
- Fig. 4 is a graph illustrating several modulation profile ranges for producing a spread spectrum modulated clock output signal in accordance with the present invention;
- Fig. 5 is a graph illustrating yet another embodiment of a desired modulation profile for producing a spread spectrum modulated clock output signal in accordance with the present invention;
- Fig. 6 is a schematic block diagram illustrating a circuit embodiment for producing a precisely controlled spread spectrum modulated clock output signal in accordance with the present invention;
- Fig. 7 is a schematic block diagram illustrating another embodiment for producing a precisely controlled spread spectrum modulated clock output signal in accordance with the present invention; and
- Fig. 8 is a variation of the circuit of Fig. 7 eliminating one counter.
- Like numbers refer to like elements throughout.
- Referring first to Figs. 1 through 5, an electronic device incorporating a spread spectrum clock generating circuit and its basic operation are first explained.
- As shown in Fig. 1, an electronic device, such as the schematically illustrated
personal computer 10, may benefit by having reduced measurable EMI spectral component emissions provided by a spread spectrum clock generator 14 (SSCG) according to the invention. Areference frequency generator 15, such as a piezoelectric crystal driven at its resonant frequency by a suitable driver or oscillator circuit, provides a reference frequency for theSSCG 14. The illustratedpersonal computer 10 also includes adisplay 12 and akeyboard 13. - As would be readily understood by those of skill in the art, a number of electronic devices incorporating microprocessors or other digital circuits requiring a clock signal for synchronization may also desirably incorporate the
SSCG 14. For example, computer printers may also desirably include theSSCG 14. - The SSCG 14 generates the spread spectrum output clock signal by frequency modulating a typical clock signal including a series of trapezoidal or generally rectangularly-shaped electrical clock pulses. The modulation reduces the spectral amplitude of the EMI components at each harmonic of the clock when compared to the spectrum of the same clocking signal without modulation. Fig.2 is a schematic representation of this effect where the spectral amplitude versus frequency at a harmonic (NF) is indicated by the plot labelled M. As also shown, the spectrum at the same harmonic of a standard clock signal is given as an impulse function labelled I. The spectrum of the SSCG output clock signal at the same harmonic ideally assumes a trapezoidal shape as illustrated by the plot labelled T.
- Although in general the spectral "width" of the spread spectrum output clock signal at a harmonic is greater than the width of the standard non-modulated clock signal, the maximum amplitude for the harmonic is reduced. In an actual implementation, the amplitude of the spread spectrum modulated harmonic will not be uniform, but will exhibit some peaking near the centre frequency and at the edges as illustrated by the plot M.
- In order to minimize the amplitude of the signal for all frequencies, the modulation of the standard clock signal must be uniquely specified. Accordingly, the
SSCG 14 includes profile modulation means for frequency modulating the clock pulse generating means with a periodic waveform having a predetermined period and a predetermined frequency deviation profile as a function of the predetermined period. The modulation profiles described herein produce relatively optimized flat spectral amplitudes at each harmonic. In general, the preferred profiles are more complicated than a simple sine wave in order to thereby reduce the measurable spectral peaks of the EMI components. Stated in other terms, the present invention converts narrow band harmonics into broadband signals that significantly reduce the measured emissions for the FCC and other regulatory bodies worldwide. These emission reductions may permit corresponding cost reductions of about $20 or more per product, as compared to the cost of conventional measures to suppress or shield EMI emissions. - Fig. 3 illustrates a typical profile of the frequency deviation versus time as may be used within the
SSCG 14. The maximum deviation illustrated is 100 kHz. This maximum frequency deviation is desirably programmable via a serial link with an upper limit of the maximum deviation being preferably about 250 kHz for typical current applications. However, depending on the application, the maximum deviation may be much greater that 250 kHz as would be readily understood by those skilled in the art. As would be also readily understood by those skilled in the art, a standard, non-modulated clock signal may be obtained by programming the maximum deviation to 0. - The frequency of the signal modulating profile shown in Fig. 3 is 30 kHz. Significant peak amplitude reduction may also be achieved where the frequency is above 2 kHz, that is, where the period of the modulating waveform or profile is less than about 500 microseconds. This frequency is also desirably programmable via a serial link or may be fixed dependent on the application. The modulating profile illustrated is a linear combination of a standard triangular wave and its cubic. The values of the profile are given in TABLE 1 of EP-A-0655829.
- Referring now more particularly to Fig. 4, several preferred ranges of profiles of frequency deviation are illustrated. In particular, the profiles are expressed as a percentage of frequency deviation versus a percentage of the period (%Period) of the periodic waveform. The outermost range or envelope is illustrated by the dotted lines labelled F1, F2 in the second quadrant II, that is, between 0% and 25% of the period. Straightforward symmetry defines the boundaries in the other indicated quadrants as described. Accordingly, those of skill in the art may readily implement and scale the ranges for a desired application.
-
- As would be readily understood by those skilled in the art, the boundaries for the other quadrants defined by F1 and F2 may be as follows:
- Quadrant I (-25% to 0% Period):
Lower bound = - F1(-%Period),
Upper bound = - F2(-%Period); - Quadrant III (25% to 50% Period):
Lower bound = F2(50 - %Period),
Upper bound = F1(50 - %Period); - Quadrant IV (50% to 75% Period):
Lower bound = -F1(%Period - 50)
Upper bound = -F2(%Period - 50). -
- Accordingly, the other boundaries are given by:
- Quadrant I (-25% to 0% Period):
Lower bound = -F3(-%Period),
Upper bound = -F4(-%Period); - Quadrant III (25% to 50% Period):
Lower bound = F4(50 - %Period),
Upper bound = F3(50 - %Period); and - Quadrant IV (50% to 75% Period):
Lower bound = -F3(%Period - 50),
Upper bound = -F4(%Period - 50). -
- Accordingly, the solid line is defined in the other quadrants as follows:
- Quadrant I (-25% to 0% Period):
-F5 (-%Period); - Quadrant III (25% to 50% Period):
F5(50 - %Period); and - Quadrant IV (50% to 75% Period):
-F5(%Period - 50). - Fig. 5 illustrates yet another embodiment of a profile for the frequency deviation modulation which may be scaled to fit within the outermost profile defined by F1 and F2 as would be readily appreciated by those of skill in the art.
- Referring now to Fig. 6 a circuit embodiment for the
SSCG 14 is described. The block diagrams are similar to several conventional phase locked loop (PLL) frequency synthesizer chips; however, a modulation section is added which includes a programmable modulation generator in several embodiments, or an analog modulation generator in other embodiments. The modulation is fed into a voltage controlled oscillator (VCO) or oscillator tank circuit to give the desired modulation index. - The
SSCG 14 may desirably be programmable via an I2C serial bus or select lines to allow variation of the centre frequency, maximum frequency deviation and modulation frequency. A single +5V supply, minimal external circuitry and a crystal will produce a TTL and CMOS compatible output with controlled rise and fall times. In addition, all inputs are standard TTL compatible. - The following electrical characteristics (TABLE 2) and switching characteristics (TABLE 3) given below are also desirably met by the embodiments of the
SSCG 14 to be compatible with conventional digital circuits or microprocessors clock input requirements.TABLE 2 Electrical Characteristics Characteristic Symbol Min Typ Max Units Load Capacitance CL - 30 50 pf Quiescent Supply Current Icc - - 45 mA TABLE 3 Switching Characteristics Characteristic Symbol Min Typ Max Units Output Rise (0.8V to 2.0V) and Fall Time (2.0V to 0.8V) tTLH, t HL1 2 3 ns Max Frequency Deviation ΔF max 0 100 250 kHz Modulating Frequency* F mod15 30 50 kHz *Programmable via serial link. - Referring now to Fig. 6,
Y1 22 is a piezoelectric crystal used with anoscillator circuit 24 to generate a stable clock pulse train or unmodulated clock signal. A firstprogrammable counter 26 divides the unmodulated clock signal by an integer number (M). A voltage controlled oscillator 28 (VCO 1) generates an output clock signal that is proportional to the input voltage from aphase detector 30 through afilter 32. - A second
programmable counter 34 divides the signal fromVCO 28 by an integer number (N).Counters detector 30.Phase detector 30 andfilter 32 generate an analog signal that is proportional to the errors in phase between the first and secondprogrammable counters phase detector 30 andfilter 32 each represents theoscillator 24 frequency times N/M, when N and M are constant, as they are in the embodiment of Fig. 6.VCO 28 is operated as in a standard phase locked loop circuit. - The spread spectrum modulation is introduced in this embodiment by a
ROM 36 having stored therein modulation variation values that are fed into a digital to analog convertor (DAC) 38. An up/downcounter 40 is used to index the value ofROM 36, while a thirdprogrammable counter 42 sets the modulation frequency. - A second voltage controlled oscillator (VCO 2) 44 receives an input of the constant output from
filter 32 plus the input fromDAC 38, which varies the frequency ofVCO 44 according to the changes in input fromDAC 38.VCO 44 is connected throughbuffer 46 as the spread spectrum clock output. - It will be apparent that the modulation can be brought to a known condition by setting up/down
counter 40. Thus, by resettingcounter 40, the input toVCO 44 represents that for the start of a cycle andVCO 44 promptly adjusts to provide a corresponding frequency. - A second implementation circuit suitable for synchronization is shown in Fig. 7.
Element 50 is a reference frequency clock, which may be identical to the combination ofelements Clock 50 serves as a clock input to count-down counter 52. A second input online 54 to counter 52 is a reset input. -
Counter 52 receives number data fromROM table memory 56, which data is counted down once with each clock signal fromclock 50 untilcounter 52 reaches zero and produces a signal onoutput line 58. That signal online 58 is an input signal to up/downcounter 60 andphase detector 62. - Each count change of
counter 60 produces a different output, which changes the address to ROM table 56 and thereby applies the count data at that address to counter 52, to again begin a count down to zero bycounter 52. Separately, whencounter 60 is reset by a signal online 54, it produces a signal online 64 suitable as a reset signal of another spread spectrum clock circuit, which may be identical to that of Fig. 7. -
Phase detector 62 and the remaining elements of Fig. 7 are a standard phased locked loop. The second input to phasedetector 62 is the output of voltage controlledoscillator 66 online 68 divided by an integral number by acounter 70.Phase detector 62 produces a signal proportional to the time difference between leading edges of the signal online 58 and the signal fromcounter 70. This output is smoothed byfilter 72, as is conventional. - Summarizing the operation,
reference clock 50 steps down counter 52, which has been loaded by ROM table 56. Thus, the number from table 56 defines a delay beforecounter 52 reaches zero and issues a signal online 58. That signal is one input to phasedetector 62, while a divided feedback from theoutput 68 of the phased locked loop is the other. - The signal from counter 52 on
line 58 also steps up/downcounter 60. The next status ofcounter 60 defines an output which selects the next location in ROM table 56, thereby entering a different number incounter 52. - When subsequent clock pulses decrement the new count in
counter 52 to zero, the next signal is issued online 58 and the operations just recited are repeated. - Assuming that the desired changes in frequency are not rapid and filter 72 readily passes changes corresponding to the frequency of those changes, the content of ROM table 56 can directly correspond to the desired change. A very simplified and illustrative content might be 17 followed by 14, followed by 10, followed by 6, followed by 3, followed by 0. These are addressed as
counter 60 increases from 0 (which addresses the 17) to 5 (which addresses the 0), after which counter 60 would decrement on the next count, so that the next count is 4 (which addresses the 3). - The interplay between the phase locked
loop line 58 may be relatively frequent with respect to the frequency band which filter 72 passes, than the output does not closely follow individual changes. In that event the number contents in ROM table 56 might differ somewhat in order to achieve the desired output throughfilter 72, although the gross change in numbers in ROM table 56 would continue to correspond to the desired spread spectrum pattern. In such event the specific numbers in ROM table 56 will be best determined empirically. - In certain applications the clock timing may vary provided certain functions are synchronized to that varying pattern. In a laser printer, a laser beam is swept across a photoconductor as it is pulsed or not pulsed at the clock times. Those clock times may be in a spread spectrum without significant degradation of the printing if each sweep is synchronized to the same point in the spread spectrum. A similar problem exists for video displays created by electron beam sweep or similar sweeping.
- The reset input on
line 54 provides such synchronization. A start-of-sweep signal is conventionally available from a laser printhead (conventionally termed HSync). This HSync signal is applied to theline 54. That signal resets counter 60 and counter 52 to zero. This immediately brings the frequency of pulses online 58 to that defined by thecounter 60 being zero and then being stepped as described.Phase detector 62 immediately begins to change the frequency ofVCO 66 if the other input to phasedetector 62 represents a different phase. The resetting ofcounter 60 produces a signal online 64, which can reset a second spread spectrum clock circuit so that the two spread spectrum clock circuits are synchronized with themselves and with the input on theline 54. - Fig. 8 is an alternative embodiment which eliminates the
counter 70. Other elements are numbered the same as the corresponding elements in Fig. 7, as the other difference is in the content of ROM table 56. Since the reference clock is one of the two inputs to phasedetector 62, the content of ROM table 56 must be adjusted accordingly. In practice, the exact content of ROM table 56 will be best determined empirically. - As would be readily understood by those skilled in the art, in an implementation of any of the circuits described herein in a physical package, several such spread spectrum clock generating circuits (SSCG's) may be found in the same DIP. In addition, a standard phase locked loop frequency synthesizer may also be located in the same DIP to provide standard clock signals, if desired. The SSCG may also be included internally with a microprocessor or any other digital or analog circuit.
- Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.
Claims (10)
- A clock controlled electronic device including a clock to provide spread spectrum clock signals, said clock comprising a reference frequency clock, a stored table of digital values, a counter to address said table at different counts of said counter, a voltage controlled oscillator having a control input, and means to receive said stored digital values addressed with each change of the count of said counter and to convert said received digital values to control signals to said input of said voltage controlled oscillator, the output of said voltage controlled oscillator providing said spread spectrum clock signals.
- The clock controlled device as in claim 1, further comprising a reset input to said counter to receive a reset signal to synchronize said spread spectrum clock signal with said reset signal.
- The clock controlled device as in claim 1 or 2, further comprising a phase locked loop, a second counter receiving signals from said reference frequency clock and providing a control input to said phase locked loop, and means to combine a signal from said phase locked loop and from said converted signal, and to provide said combined signals as said control signal to said voltage controlled oscillator.
- A clock controlled electronic device including a clock to provide spread spectrum clock signals to said device, said clock comprising a reference frequency clock, a stored table of digital values, a first counter to address said table at different parts of said table determined by different counts of said first counter, a second counter to receive said stored digital values addressed with each change of the count of said first counter, means responsive to clock signals of said reference frequency clock to step said second counter after said second counter receives each said digital value, a phase detector responsive to the difference in phase of two inputs to produce an output representative of the phase difference of said two inputs of said phase detector, means responsive to said second counter reaching a predetermined value to provide a control signal to step the count of said first counter and to provide one input to said phase detector, a voltage controlled oscillator having an input receiving said output of said phase detector and an output connected to the second input of said phase detector to form a phase locked loop, the output of said phase locked loop providing said spread spectrum clock signals.
- The clock controlled device of claim 4, further comprising a reset input to said first counter and to said second counter to receive a reset signal to synchronize said spread spectrum clock signal with said reset signal.
- The clock controlled device of claim 4 or 5, in which said second counter receives said reference frequency clock signals and said one input of said phase detector is connected to be provided by said second counter reaching a predetermined value.
- The clock controlled device of claim 4, 5 or 6, in which said second counter is connected between said output of said voltage controlled oscillator and said second input of said phase detector, and said reference frequency clock signals are connected to provide said one input of said phase detector.
- A clock circuit comprising clock means for producing a reference frequency clock signal and modulating means for generating a spread spectrum clock signal from said reference signal in accordance with a predetermined frequency deviation profile, said circuit further comprising reset means for resetting said modulating means so that said modulating means modulates said reference signal from a set point in said profile.
- Scanning means incoporating a clock circuit as defined in claim 8, wherein the reset means resets the modulating means at the start of a scan.
- A laser printhead incorporating a clock circuit as defined in claim 8, wherein the reset means resets the modulating means in accordance with a start-of-sweep signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04023722A EP1494349B1 (en) | 1995-04-20 | 1996-04-22 | Spread spectrum clock generator |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US425832 | 1982-09-28 | ||
US08/425,832 US5631920A (en) | 1993-11-29 | 1995-04-20 | Spread spectrum clock generator |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04023722A Division EP1494349B1 (en) | 1995-04-20 | 1996-04-22 | Spread spectrum clock generator |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0739089A2 true EP0739089A2 (en) | 1996-10-23 |
EP0739089A3 EP0739089A3 (en) | 1998-09-16 |
EP0739089B1 EP0739089B1 (en) | 2004-10-20 |
Family
ID=23688216
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP96302821A Expired - Lifetime EP0739089B1 (en) | 1995-04-20 | 1996-04-22 | Spread spectrum clock generator |
EP04023722A Expired - Lifetime EP1494349B1 (en) | 1995-04-20 | 1996-04-22 | Spread spectrum clock generator |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04023722A Expired - Lifetime EP1494349B1 (en) | 1995-04-20 | 1996-04-22 | Spread spectrum clock generator |
Country Status (4)
Country | Link |
---|---|
US (2) | US5631920A (en) |
EP (2) | EP0739089B1 (en) |
JP (1) | JP3899395B2 (en) |
DE (2) | DE69636488T2 (en) |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2792101A1 (en) * | 1999-04-12 | 2000-10-13 | Lg Philips Lcd Co Ltd | DATA INTERFACE DEVICE |
US6175259B1 (en) | 1999-02-09 | 2001-01-16 | Cypress Semiconductor Corp. | Clock generator with programmable two-tone modulation for EMI reduction |
GB2315392B (en) * | 1996-07-11 | 2001-07-11 | 4Links Ltd | Communications system |
EP1133144A2 (en) * | 2000-01-17 | 2001-09-12 | Konica Corporation | Image forming apparatus and image reading device for use in the apparatus |
DE10049531A1 (en) * | 2000-10-06 | 2002-04-18 | Texas Instruments Deutschland | Clock generator has PLL circuit with analog controled oscillator, second oscillator designed so oscillation frequency is variable over defined range by digital, stepwise variable control signal |
US6553057B1 (en) | 1999-11-09 | 2003-04-22 | Cypress Semiconductor Corp. | Circuit and method for linear control of a spread spectrum transition |
WO2003036607A1 (en) * | 2001-10-25 | 2003-05-01 | Fujitsu Limited | Display control device |
EP1329840A2 (en) * | 2002-01-16 | 2003-07-23 | Xerox Corporation | Method and reducing electromagnetic emissions (emi) from led bar systems |
US6798303B2 (en) | 2002-01-30 | 2004-09-28 | Infineon Technologies Ag | Clock signal generating device |
US6850554B1 (en) | 1999-11-09 | 2005-02-01 | Cypress Semiconductor Corp. | Circuit and method for controlling a spread spectrum transition |
EP1376531A3 (en) * | 2002-06-18 | 2005-06-08 | Seiko Epson Corporation | Electronic apparatus with reduced electromagnetic interference noise |
EP1592154A2 (en) * | 2004-04-29 | 2005-11-02 | Linear Technology Corporation | Methods and circuits for frequency modulation that reduce the spectral noise of switching regulators |
US6980581B1 (en) | 2000-07-18 | 2005-12-27 | Cypress Semiconductor Corp. | Adaptive spread spectrum |
ES2267364A1 (en) * | 2004-11-23 | 2007-03-01 | Universitat Politecnica De Catalunya | Modulation circuit for reducing harmonics of interference in power converters has reduction circuitry whose operation depends on modulation of frequency of commutation signal |
EP1835724A2 (en) * | 2006-03-17 | 2007-09-19 | Ricoh Company, Ltd. | Black-level feedback device, image reading device, and black-level feedback control method |
EP1858157A1 (en) * | 2006-05-15 | 2007-11-21 | STMicroelectronics Pvt. Ltd. | Spread spectrum clock generation system |
EP1477956A3 (en) * | 2003-05-16 | 2008-05-07 | Canon Kabushiki Kaisha | Drive control apparatus and drive control method for a cold cathode field emission display panel |
WO2009018108A1 (en) * | 2007-07-27 | 2009-02-05 | Pulsecore Semiconductor Corporation | Usb system with spread spectrum emi reduction |
WO2009019460A1 (en) * | 2007-08-03 | 2009-02-12 | Wolfson Microelectronics Plc | Amplifier circuit and method of amplifying a signal in an amplifier circuit |
US7813411B1 (en) | 2005-06-30 | 2010-10-12 | Cypress Semiconductor Corporation | Spread spectrum frequency synthesizer with high order accumulation for frequency profile generation |
US7813410B1 (en) | 2005-09-02 | 2010-10-12 | Cypress Semiconductor Corporation | Initiating spread spectrum modulation |
US7912109B1 (en) | 2005-06-30 | 2011-03-22 | Cypress Semiconductor Corporation | Spread spectrum frequency synthesizer with first order accumulation for frequency profile generation |
US7932787B1 (en) | 2005-06-30 | 2011-04-26 | Cypress Semiconductor Corporation | Phase lock loop control system and method |
US7948327B1 (en) | 2005-06-30 | 2011-05-24 | Cypress Semiconductor Corporation | Simplified phase lock loop control model system and method |
US7961059B1 (en) | 2005-06-30 | 2011-06-14 | Cypress Semiconductor Corporation | Phase lock loop control system and method with non-consecutive feedback divide values |
US8174326B1 (en) | 2005-06-30 | 2012-05-08 | Cypress Semiconductor Corporation | Phase lock loop control error selection system and method |
WO2013174377A3 (en) * | 2012-05-23 | 2014-01-30 | Silicon Line Gmbh | Circuit arrangement and method for calibrating activation signals for voltage-controlled oscillators |
Families Citing this family (139)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69332417T2 (en) * | 1992-09-16 | 2003-08-14 | Hitachi Ltd | Transmission control for a motor vehicle |
US5982831A (en) * | 1996-02-21 | 1999-11-09 | Hewlett-Packard Company | Feed forward method and apparatus for generating a clock signal |
US5943382A (en) * | 1996-08-21 | 1999-08-24 | Neomagic Corp. | Dual-loop spread-spectrum clock generator with master PLL and slave voltage-modulation-locked loop |
US5757338A (en) * | 1996-08-21 | 1998-05-26 | Neomagic Corp. | EMI reduction for a flat-panel display controller using horizontal-line based spread spectrum |
JP3675063B2 (en) * | 1996-10-15 | 2005-07-27 | ブラザー工業株式会社 | Image reading system and image reading method |
US6169889B1 (en) | 1997-08-04 | 2001-01-02 | Motorola | Method and electronic device using random pulse characteristics in digital signals |
US6289068B1 (en) * | 1998-06-22 | 2001-09-11 | Xilinx, Inc. | Delay lock loop with clock phase shifter |
US7564283B1 (en) | 1998-06-22 | 2009-07-21 | Xilinx, Inc. | Automatic tap delay calibration for precise digital phase shift |
US6493830B2 (en) | 1998-07-03 | 2002-12-10 | Canon Kabushiki Kaisha | Clock control device used in image formation |
US6525842B1 (en) | 1998-07-09 | 2003-02-25 | Canon Kabushiki Kaisha | Image processing apparatus and method of the same and storage medium |
US6240123B1 (en) * | 1998-07-20 | 2001-05-29 | Intel Corporation | Asynchronous spread spectrum clocking |
US6442188B1 (en) * | 1998-07-20 | 2002-08-27 | Intel Corporation | Phase locked loop |
US6351485B1 (en) * | 1998-09-08 | 2002-02-26 | Fairchild Semiconductor Corporation | Spread spectrum modulation technique for frequency synthesizers |
US6294936B1 (en) | 1998-09-28 | 2001-09-25 | American Microsystems, Inc. | Spread-spectrum modulation methods and circuit for clock generator phase-locked loop |
US6167103A (en) * | 1998-10-08 | 2000-12-26 | Lexmark International, Inc. | Variable spread spectrum clock |
US6642758B1 (en) | 1998-11-03 | 2003-11-04 | Altera Corporation | Voltage, temperature, and process independent programmable phase shift for PLL |
US7109765B1 (en) | 1998-11-03 | 2006-09-19 | Altera Corporation | Programmable phase shift circuitry |
JP3267260B2 (en) | 1999-01-18 | 2002-03-18 | 日本電気株式会社 | Phase locked loop circuit and frequency modulation method using the same |
US6687319B1 (en) | 1999-02-04 | 2004-02-03 | Rambus Inc. | Spread spectrum clocking of digital signals |
JP3295777B2 (en) * | 1999-06-01 | 2002-06-24 | ローム株式会社 | PLL circuit |
US6292507B1 (en) * | 1999-09-01 | 2001-09-18 | Lexmark International, Inc. | Method and apparatus for compensating a spread spectrum clock generator |
JP3613787B2 (en) | 1999-10-18 | 2005-01-26 | 日本プレシジョン・サーキッツ株式会社 | Self-modulating clock generator |
US6895046B1 (en) | 1999-10-18 | 2005-05-17 | Bae Systems Information And Electronic Systems Integration Inc. | System and method of providing a spread spectrum pulse width modulator clock |
US6697416B1 (en) * | 1999-10-29 | 2004-02-24 | Texas Instruments Incorporated | Digital programmable, spread spectrum clock generator |
US6366174B1 (en) | 2000-02-21 | 2002-04-02 | Lexmark International, Inc. | Method and apparatus for providing a clock generation circuit for digitally controlled frequency or spread spectrum clocking |
US6643317B1 (en) | 2000-02-25 | 2003-11-04 | Electronics For Imaging, Inc. | Digital spread spectrum circuit |
JP2001255958A (en) * | 2000-03-10 | 2001-09-21 | Konica Corp | Clock-generating device, substrate and image-forming device and clock-generating method |
US6597226B1 (en) | 2000-07-13 | 2003-07-22 | Lexmark International, Inc. | Application specific integrated circuit architecture utilizing spread spectrum clock generator module for reducing EMI emissions |
US6665019B1 (en) * | 2000-07-28 | 2003-12-16 | Koninklijke Philips Electronics N.V. | Method and apparatus for spread spectrum clocking of digital video |
US7050478B1 (en) * | 2000-08-03 | 2006-05-23 | International Business Machines Corporation | Apparatus and method for synchronizing clock modulation with power supply modulation in a spread spectrum clock system |
US6462705B1 (en) | 2000-08-17 | 2002-10-08 | Mcewan Technologies, Llc | Spread spectrum radar clock |
US6404834B1 (en) * | 2000-09-20 | 2002-06-11 | Lexmark International, Inc. | Segmented spectrum clock generator apparatus and method for using same |
US7187742B1 (en) | 2000-10-06 | 2007-03-06 | Xilinx, Inc. | Synchronized multi-output digital clock manager |
KR100471054B1 (en) * | 2000-11-18 | 2005-03-07 | 삼성전자주식회사 | Computer and image processing method thereof |
KR20020074980A (en) * | 2001-03-23 | 2002-10-04 | (주)네오마이크로스 | Apparatus for generating spread spectrum frequency modulated clock pulses having reduced emi |
JP3567905B2 (en) | 2001-04-06 | 2004-09-22 | セイコーエプソン株式会社 | Oscillator with noise reduction function, writing device, and method of controlling writing device |
KR100811343B1 (en) * | 2001-05-02 | 2008-03-07 | 엘지전자 주식회사 | The apparatus of EMI's prevention for the plat panel display device |
US6798302B2 (en) * | 2001-05-06 | 2004-09-28 | Altera Corporation | Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system |
US6744277B1 (en) | 2001-05-06 | 2004-06-01 | Altera Corporation | Programmable current reference circuit |
US7242229B1 (en) | 2001-05-06 | 2007-07-10 | Altera Corporation | Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode |
US6856180B1 (en) | 2001-05-06 | 2005-02-15 | Altera Corporation | Programmable loop bandwidth in phase locked loop (PLL) circuit |
EP1289150A1 (en) * | 2001-08-24 | 2003-03-05 | STMicroelectronics S.r.l. | A process for generating a variable frequency signal, for instance for spreading the spectrum of a clock signal, and device therefor |
US8254430B1 (en) * | 2001-09-10 | 2012-08-28 | Narendar Venugopal | Method and apparatus for detection and control of spread spectrum EMI reduction |
US6952138B2 (en) * | 2001-09-12 | 2005-10-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Generation of a phase locked loop output signal having reduced spurious spectral components |
JP2003101408A (en) * | 2001-09-21 | 2003-04-04 | Citizen Watch Co Ltd | Oscillator |
KR100493024B1 (en) * | 2001-09-25 | 2005-06-07 | 삼성전자주식회사 | Phased locked loop for reducing the electro magnetic interference |
US6658043B2 (en) | 2001-10-26 | 2003-12-02 | Lexmark International, Inc. | Method and apparatus for providing multiple spread spectrum clock generator circuits with overlapping output frequencies |
JP3591503B2 (en) | 2001-11-08 | 2004-11-24 | セイコーエプソン株式会社 | An image processing apparatus that operates based on a frequency-spread clock and processes an input image signal |
US6501307B1 (en) | 2001-11-12 | 2002-12-31 | Pericom Semiconductor Corp. | Spread-spectrum clock buffer/driver that modulates clock period by switching loads |
KR100840673B1 (en) * | 2001-12-29 | 2008-06-24 | 엘지디스플레이 주식회사 | Flat panel display device and method for operating the same |
US7305020B2 (en) * | 2002-02-04 | 2007-12-04 | Vizionware, Inc. | Method and system of reducing electromagnetic interference emissions |
US6982707B2 (en) * | 2002-03-14 | 2006-01-03 | Genesis Microchip Inc. | Method and apparatus utilizing direct digital synthesizer and spread spectrum techniques for reducing EMI in digital display devices |
JP4106975B2 (en) * | 2002-06-19 | 2008-06-25 | セイコーエプソン株式会社 | Diffusion amount control device |
DE60205120T2 (en) * | 2002-10-18 | 2006-04-20 | Agilent Technologies, Inc. (n.d.Ges.d.Staates Delaware), Palo Alto | Apparatus and method for generating wander noise |
DE60328925D1 (en) * | 2002-12-24 | 2009-10-01 | Fujitsu Microelectronics Ltd | jitter |
KR100456285B1 (en) * | 2003-02-12 | 2004-11-09 | 한국과학기술원 | Spread spectrum clock generator based on phase inversion |
US20050105591A1 (en) * | 2003-02-28 | 2005-05-19 | Xemi, Inc. | Noise source synchronization for power spread signals |
US7561652B2 (en) * | 2003-04-22 | 2009-07-14 | Paul Kevin Hall | High frequency spread spectrum clock generation |
DE60310373T2 (en) * | 2003-04-28 | 2007-09-27 | Accent S.P.A. | Clock generator with spectral dispersion |
TWI221060B (en) | 2003-05-29 | 2004-09-11 | Himax Tech Inc | Apparatus for lowering electromagnetic wave interference and its method |
CN100438599C (en) * | 2003-06-13 | 2008-11-26 | 奇景光电股份有限公司 | Apparatus for reducing electromagnetic wave interference and method thereof |
US7015738B1 (en) * | 2003-06-18 | 2006-03-21 | Weixun Cao | Direct modulation of a voltage-controlled oscillator (VCO) with adaptive gain control |
US6919744B2 (en) * | 2003-08-20 | 2005-07-19 | Agere Systems Inc. | Spectrum profile control for a PLL and the like |
US7233210B2 (en) * | 2003-08-26 | 2007-06-19 | Toshiba America Electric Components, Inc. | Spread spectrum clock generator |
US7236057B2 (en) * | 2003-08-26 | 2007-06-26 | Toshiba America Electronic Components, Inc. | Spread spectrum clock generator |
KR100541548B1 (en) * | 2003-09-08 | 2006-01-11 | 삼성전자주식회사 | Spread spectrum clock generator and method thereof |
TWI252393B (en) * | 2003-09-08 | 2006-04-01 | Samsung Electronics Co Ltd | A spread spectrum clock generator and method and system of generating a spread spectrum clock |
JP4698136B2 (en) * | 2003-09-11 | 2011-06-08 | 富士通セミコンダクター株式会社 | Band distribution inspection device and band distribution inspection method |
JP2005101771A (en) * | 2003-09-22 | 2005-04-14 | Matsushita Electric Ind Co Ltd | Clock transferring circuit and method thereof |
US7015733B2 (en) * | 2003-10-10 | 2006-03-21 | Oki Electric Industry Co., Ltd. | Spread-spectrum clock generator using processing in the bitstream domain |
JP4364621B2 (en) * | 2003-12-04 | 2009-11-18 | 富士通マイクロエレクトロニクス株式会社 | Clock generator |
US7515646B2 (en) | 2004-02-05 | 2009-04-07 | Lexmark International, Inc. | Method and apparatus for reducing EMI emissions for data signals traveling over a data pathway |
US7486152B2 (en) | 2004-02-17 | 2009-02-03 | Murata Manufacturing Co., Ltd. | Voltage controlled oscillator |
JP4469628B2 (en) * | 2004-02-18 | 2010-05-26 | セイコーNpc株式会社 | Distributed modulation type clock generation circuit |
US7346095B1 (en) | 2004-02-20 | 2008-03-18 | Zilog, Inc. | Spread spectrum clock generator with controlled delay elements |
US7443905B1 (en) * | 2004-03-19 | 2008-10-28 | National Semiconductor Corporation | Apparatus and method for spread spectrum clock generator with accumulator |
US7167059B2 (en) * | 2004-04-08 | 2007-01-23 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Circuit for generating spread spectrum clock |
US7676012B1 (en) * | 2004-04-22 | 2010-03-09 | Pulsecore Semiconductor Corp. | Spread spectrum controllable delay clock buffer with zero cycle slip |
US7042258B2 (en) * | 2004-04-29 | 2006-05-09 | Agere Systems Inc. | Signal generator with selectable mode control |
JP4390646B2 (en) * | 2004-07-09 | 2009-12-24 | Necエレクトロニクス株式会社 | Spread spectrum clock generator and modulation method thereof |
US7313161B2 (en) * | 2004-09-10 | 2007-12-25 | Elite Semiconductor Memory Technology Inc. | Spread spectrum clock generator and method of generating spread spectrum clock |
US7161970B2 (en) * | 2004-09-10 | 2007-01-09 | Ftd Solutions Pte, Ltd. | Spread spectrum clock generator |
KR100712501B1 (en) * | 2004-11-08 | 2007-05-02 | 삼성전자주식회사 | A spread spectrum clock generator with PVT invariant frequency modulation ratio |
JP4587798B2 (en) * | 2004-12-08 | 2010-11-24 | ルネサスエレクトロニクス株式会社 | Spread spectrum clock generator |
US7330078B1 (en) * | 2004-12-20 | 2008-02-12 | Cypress Semiconductor Corporation | Apparatus and method for limiting the overshoot and undershoot when turning on the spread spectrum of a reference signal |
US7423494B1 (en) | 2005-01-05 | 2008-09-09 | National Semiconductor Corporation | Apparatus and method for a spread-spectrum oscillator for magnetic switched power converters |
US7504810B1 (en) | 2005-02-18 | 2009-03-17 | National Semiconductor Corporation | Apparatus and method for generating a spread-spectrum clock for a switching regulator |
US7512205B1 (en) * | 2005-03-01 | 2009-03-31 | Network Equipment Technologies, Inc. | Baud rate generation using phase lock loops |
US7701297B1 (en) | 2005-06-30 | 2010-04-20 | Cypress Semiconductor Corporation | Spread spectrum frequency synthesizer with improved frequency shape by adjusting the length of a standard curve used for spread spectrum modulation |
US7741918B1 (en) | 2005-06-30 | 2010-06-22 | Cypress Semiconductor Corporation | System and method for an enhanced noise shaping for spread spectrum modulation |
US8072277B1 (en) | 2005-06-30 | 2011-12-06 | Cypress Semiconductor Corporation | Spread spectrum frequency synthesizer |
DE102005050147B8 (en) | 2005-10-19 | 2008-01-24 | Infineon Technologies Ag | Circuit arrangement and method for reducing electromagnetic interference |
US20070206642A1 (en) * | 2005-11-10 | 2007-09-06 | X-Emi, Inc. | Bidirectional active signal management in cables and other interconnects |
JP2006154820A (en) * | 2005-11-24 | 2006-06-15 | Olympus Corp | Image display device |
JP4308191B2 (en) * | 2005-11-24 | 2009-08-05 | オリンパス株式会社 | Portable communication device |
JP2006101549A (en) * | 2005-11-24 | 2006-04-13 | Olympus Corp | Image recording apparatus |
JP4104624B2 (en) * | 2005-11-25 | 2008-06-18 | シャープ株式会社 | Image processing apparatus, image reading apparatus, and image forming apparatus |
US8035455B1 (en) | 2005-12-21 | 2011-10-11 | Cypress Semiconductor Corporation | Oscillator amplitude control network |
US7437590B2 (en) * | 2006-02-22 | 2008-10-14 | Analog Devices, Inc. | Spread-spectrum clocking |
US7759926B2 (en) * | 2006-02-24 | 2010-07-20 | Lattice Semiconductor Corporation | Dynamic phase offset measurement |
US7590163B1 (en) | 2006-05-19 | 2009-09-15 | Conexant Systems, Inc. | Spread spectrum clock generation |
US7342528B2 (en) * | 2006-06-15 | 2008-03-11 | Semiconductor Components Industries, L.L.C. | Circuit and method for reducing electromagnetic interference |
US8339689B1 (en) | 2006-06-30 | 2012-12-25 | Marvell International Ltd. | Exposure correction for scanners |
JP4874020B2 (en) * | 2006-07-13 | 2012-02-08 | 株式会社リコー | Spread spectrum clock generation circuit |
US20080247414A1 (en) * | 2007-04-03 | 2008-10-09 | Vizionware, Inc. | Clock stretching in an adaptive two-wire bus |
US20080246626A1 (en) * | 2007-04-03 | 2008-10-09 | Vizionware, Inc. | Data transaction direction detection in an adaptive two-wire bus |
US20080250175A1 (en) * | 2007-04-03 | 2008-10-09 | Vizionware, Inc. | Cable assembly having an adaptive two-wire bus |
US20080250170A1 (en) * | 2007-04-03 | 2008-10-09 | Vizionware, Inc. | Clock mode detection in an adaptive two-wire bus |
US20080250184A1 (en) * | 2007-04-03 | 2008-10-09 | Vizionware, Inc. | Adaptive two-wire bus |
US7929929B2 (en) * | 2007-09-25 | 2011-04-19 | Motorola Solutions, Inc. | Method and apparatus for spur reduction in a frequency synthesizer |
TWI345881B (en) * | 2007-12-03 | 2011-07-21 | Ind Tech Res Inst | Spread spectrum clock generating appartus |
US20090147827A1 (en) * | 2007-12-06 | 2009-06-11 | Richard Holmquist | Methods, Systems, and Computer Program Products for Implementing Spread Spectrum Using Digital Signal Processing Techniques |
US7970042B2 (en) * | 2008-01-11 | 2011-06-28 | Lexmark International, Inc. | Spread spectrum clock interoperability control and inspection circuit |
DE102008004241B4 (en) * | 2008-01-14 | 2012-01-12 | Erbe Elektromedizin Gmbh | Method for controlling an electrosurgical HF generator and electrosurgical unit |
JP5381001B2 (en) * | 2008-10-16 | 2014-01-08 | 富士通セミコンダクター株式会社 | Semiconductor integrated circuit and method for testing semiconductor integrated circuit |
US7656214B1 (en) * | 2008-11-18 | 2010-02-02 | Faraday Technology Corp. | Spread-spectrum clock generator |
TWI376877B (en) * | 2008-12-26 | 2012-11-11 | Ind Tech Res Inst | Clock generator and multimodulus frequency divider and delta-sigma modulator thereof |
US8171332B2 (en) * | 2009-05-12 | 2012-05-01 | Himax Technologies Limited | Integrated circuit with reduced electromagnetic interference induced by memory access and method for the same |
EP2475122A1 (en) * | 2009-09-04 | 2012-07-11 | NTT Advanced Technology Corporation | Information leakage prevention device and method |
JP5365437B2 (en) * | 2009-09-11 | 2013-12-11 | 株式会社リコー | Image reading apparatus and image forming apparatus |
US8842767B2 (en) * | 2009-11-04 | 2014-09-23 | Broadcom Corporation | System and method for un-interrupted operation of communications during interference |
US8269536B2 (en) * | 2009-12-30 | 2012-09-18 | Industrial Technology Research Institute | Onion waveform generator and spread spectrum clock generator using the same |
JP5636754B2 (en) * | 2010-06-16 | 2014-12-10 | 株式会社リコー | Image reading apparatus and image forming apparatus |
US20120033772A1 (en) * | 2010-08-08 | 2012-02-09 | Freescale Semiconductor, Inc | Synchroniser circuit and method |
US9661348B2 (en) | 2012-03-29 | 2017-05-23 | Intel Corporation | Method and system for generating side information at a video encoder to differentiate packet data |
US8975975B2 (en) | 2012-03-30 | 2015-03-10 | Intel Corporation | Spread spectrum clocking method for wireless mobile platforms |
US9048851B2 (en) * | 2013-03-15 | 2015-06-02 | Intel Corporation | Spread-spectrum apparatus for voltage regulator |
US9191128B2 (en) | 2013-12-17 | 2015-11-17 | National Applied Research Laboratories | Spread spectrum clock generator and method for generating spread spectrum clock signal |
US9660848B2 (en) | 2014-09-15 | 2017-05-23 | Analog Devices Global | Methods and structures to generate on/off keyed carrier signals for signal isolators |
US10536309B2 (en) | 2014-09-15 | 2020-01-14 | Analog Devices, Inc. | Demodulation of on-off-key modulated signals in signal isolator systems |
US10270630B2 (en) | 2014-09-15 | 2019-04-23 | Analog Devices, Inc. | Demodulation of on-off-key modulated signals in signal isolator systems |
US9813068B2 (en) * | 2014-10-03 | 2017-11-07 | Ricoh Company, Ltd. | Spread spectrum clock generator, electronic apparatus, and spread spectrum clock generation method |
US9998301B2 (en) | 2014-11-03 | 2018-06-12 | Analog Devices, Inc. | Signal isolator system with protection for common mode transients |
CN104378108B (en) * | 2014-12-04 | 2017-10-03 | 龙迅半导体(合肥)股份有限公司 | A kind of clock signal output intent and circuit |
KR101925042B1 (en) | 2017-08-17 | 2018-12-04 | 국민대학교산학협력단 | Clock Generator |
US10523225B2 (en) * | 2017-08-29 | 2019-12-31 | Texas Instruments Incorporated | Beating high-Q resonators oscillator |
EP3549990A1 (en) | 2018-04-04 | 2019-10-09 | Covestro Deutschland AG | Bicomponent system with improved adhesion |
US11139819B2 (en) | 2019-04-23 | 2021-10-05 | Boe Technology Group Co., Ltd. | Parameter determination method and device for spread spectrum circuit, and clock spread spectrum method and device |
JP7294051B2 (en) * | 2019-10-15 | 2023-06-20 | 富士電機株式会社 | Switching control circuit, power supply circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2128828A (en) * | 1982-10-20 | 1984-05-02 | Printronix Inc | Apparatus having reduced radio frequency interference |
EP0163313A2 (en) * | 1984-05-30 | 1985-12-04 | Tektronix, Inc. | Method and apparatus for spectral dispersion of the radiated energy from a digital system |
EP0655829A1 (en) * | 1993-11-29 | 1995-05-31 | Lexmark International, Inc. | Spread spectrum clock generator and associated method |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR671928A (en) * | 1929-03-22 | 1929-12-20 | Sparks Whithington Company | Improvements to warning devices |
US2671896A (en) * | 1942-12-18 | 1954-03-09 | Itt | Random impulse system |
US2352254A (en) * | 1943-07-23 | 1944-06-27 | Bell Telephone Labor Inc | Frequency modulated wave transmission |
US2953780A (en) * | 1959-04-09 | 1960-09-20 | Gen Precision Inc | Doppler simulator |
GB1090760A (en) * | 1964-04-24 | 1967-11-15 | Ass Elect Ind | Improvements in or relating to frequency modulated oscillator circuits |
US3388349A (en) * | 1964-11-09 | 1968-06-11 | Bell Telephone Labor Inc | Method for reducing interference caused by electromagnetic radiation from clock controlled systems |
US3354410A (en) * | 1965-07-22 | 1967-11-21 | Bell Telephone Labor Inc | Method for reducing interference caused by electromagnetic radiation from clock controlled systems |
US3878527A (en) * | 1970-10-07 | 1975-04-15 | Itt | Radiant energy receiver circuits |
US3764933A (en) * | 1972-09-27 | 1973-10-09 | Nasa | Controlled oscillator system with a time dependent output frequency |
FR2256582B1 (en) * | 1973-12-27 | 1976-11-19 | Trt Telecom Radio Electr | |
US4009450A (en) * | 1975-04-14 | 1977-02-22 | Motorola, Inc. | Phase locked loop tracking filter having enhanced attenuation of unwanted signals |
EP0060246A1 (en) * | 1980-09-10 | 1982-09-22 | Mostek Corporation | Delay stage for a clock generator |
US4585997A (en) * | 1983-12-08 | 1986-04-29 | Televideo Systems, Inc. | Method and apparatus for blanking noise present in an alternating electrical signal |
US4695808A (en) * | 1984-02-27 | 1987-09-22 | Ncr Corporation | Varying frequency oscillator for the reduction of radiated emissions of electronic equipment |
GB8432552D0 (en) * | 1984-12-21 | 1985-02-06 | Plessey Co Plc | Control circuits |
US4578649A (en) * | 1985-02-04 | 1986-03-25 | Motorola, Inc. | Random voltage source with substantially uniform distribution |
US4737968A (en) * | 1985-10-25 | 1988-04-12 | Phillips Petroleum Company | QPSK transmission system having phaselocked tracking filter for spectrum shaping |
JPS6489823A (en) * | 1987-09-30 | 1989-04-05 | Toshiba Corp | Control circuit for radio equipment |
WO1990014710A1 (en) * | 1989-05-22 | 1990-11-29 | Motorola, Inc. | Modulated clock source for logic circuits |
US4996684A (en) * | 1989-07-06 | 1991-02-26 | Northern Telecom Limited | Electronic systems and effective reduction of electromagnetic interference energy propagation from electronic systems |
US5028887A (en) * | 1989-08-31 | 1991-07-02 | Qualcomm, Inc. | Direct digital synthesizer driven phase lock loop frequency synthesizer with hard limiter |
SE8903799D0 (en) * | 1989-11-13 | 1989-11-13 | Ericsson Telefon Ab L M | PROCEDURE AND DEVICE TO VARY THE WIRE BANDWIDTH OF A FIXED TIP |
JPH03265014A (en) * | 1990-03-15 | 1991-11-26 | Hitachi Ltd | Computer system |
US5036298A (en) * | 1990-04-26 | 1991-07-30 | Analog Devices, Inc. | Clock recovery circuit without jitter peaking |
SE500276C2 (en) * | 1991-06-24 | 1994-05-24 | Shield Research In Sweden Ab | Method and apparatus for preventing external detection of signal information |
JPH0548338A (en) * | 1991-08-14 | 1993-02-26 | Nec Corp | Digital fm modulator |
FI89845C (en) * | 1991-09-04 | 1993-11-25 | Nokia Mobile Phones Ltd | Connection for generating broadcast signal in a radio telephone |
US5144260A (en) * | 1991-09-25 | 1992-09-01 | Rose Communications, Inc. | Method and apparatus for perturbation cancellation of a phase locked oscillator |
JP2861542B2 (en) * | 1991-10-25 | 1999-02-24 | 日本電気株式会社 | Phase locked loop synthesizer |
US5263055A (en) * | 1991-11-04 | 1993-11-16 | Motorola, Inc. | Apparatus and method for reducing harmonic interference generated by a clock signal |
US5249199A (en) * | 1992-10-30 | 1993-09-28 | Motorola, Inc. | Method and apparatus for reducing spurious noise levels in an audio system |
US5416434A (en) * | 1993-03-05 | 1995-05-16 | Hewlett-Packard Corporation | Adaptive clock generation with pseudo random variation |
US5491458A (en) * | 1994-11-08 | 1996-02-13 | Mccune, Jr.; Earl W. | Apparatus for spreading the spectrum of a signal and method therefor |
US5659587A (en) * | 1994-11-23 | 1997-08-19 | Tektronix, Inc. | Spread spectrum phase-locked loop clock generator with VCO driven by a symmetrical voltage ramp signal |
-
1995
- 1995-04-20 US US08/425,832 patent/US5631920A/en not_active Expired - Lifetime
-
1996
- 1996-04-19 JP JP12217296A patent/JP3899395B2/en not_active Expired - Lifetime
- 1996-04-22 DE DE69636488T patent/DE69636488T2/en not_active Expired - Fee Related
- 1996-04-22 DE DE69633651T patent/DE69633651T2/en not_active Expired - Fee Related
- 1996-04-22 EP EP96302821A patent/EP0739089B1/en not_active Expired - Lifetime
- 1996-04-22 EP EP04023722A patent/EP1494349B1/en not_active Expired - Lifetime
-
1997
- 1997-02-13 US US08/799,914 patent/US5872807A/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2128828A (en) * | 1982-10-20 | 1984-05-02 | Printronix Inc | Apparatus having reduced radio frequency interference |
EP0163313A2 (en) * | 1984-05-30 | 1985-12-04 | Tektronix, Inc. | Method and apparatus for spectral dispersion of the radiated energy from a digital system |
EP0655829A1 (en) * | 1993-11-29 | 1995-05-31 | Lexmark International, Inc. | Spread spectrum clock generator and associated method |
Cited By (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2315392B (en) * | 1996-07-11 | 2001-07-11 | 4Links Ltd | Communications system |
US6373306B1 (en) | 1999-02-09 | 2002-04-16 | Cypress Semiconductor Corp. | Clock generator with programmable two-tone modulation for EMI reduction |
US6175259B1 (en) | 1999-02-09 | 2001-01-16 | Cypress Semiconductor Corp. | Clock generator with programmable two-tone modulation for EMI reduction |
FR2792101A1 (en) * | 1999-04-12 | 2000-10-13 | Lg Philips Lcd Co Ltd | DATA INTERFACE DEVICE |
US6553057B1 (en) | 1999-11-09 | 2003-04-22 | Cypress Semiconductor Corp. | Circuit and method for linear control of a spread spectrum transition |
US6850554B1 (en) | 1999-11-09 | 2005-02-01 | Cypress Semiconductor Corp. | Circuit and method for controlling a spread spectrum transition |
EP1133144A3 (en) * | 2000-01-17 | 2002-10-02 | Konica Corporation | Image forming apparatus and image reading device for use in the apparatus |
EP2254323A1 (en) * | 2000-01-17 | 2010-11-24 | Konica Corporation | Image forming apparatus and image reading device for use in the apparatus |
EP1133144A2 (en) * | 2000-01-17 | 2001-09-12 | Konica Corporation | Image forming apparatus and image reading device for use in the apparatus |
EP2254322A1 (en) * | 2000-01-17 | 2010-11-24 | Konica Corporation | Image forming apparatus and image reading device for use in the apparatus |
EP2254324A1 (en) * | 2000-01-17 | 2010-11-24 | Konica Corporation | Image forming apparatus and image reading device for use in the apparatus |
US7068397B2 (en) | 2000-01-17 | 2006-06-27 | Konica Corporation | Image forming apparatus and image reading device for use in the apparatus |
US6980581B1 (en) | 2000-07-18 | 2005-12-27 | Cypress Semiconductor Corp. | Adaptive spread spectrum |
DE10049531A1 (en) * | 2000-10-06 | 2002-04-18 | Texas Instruments Deutschland | Clock generator has PLL circuit with analog controled oscillator, second oscillator designed so oscillation frequency is variable over defined range by digital, stepwise variable control signal |
DE10049531C2 (en) * | 2000-10-06 | 2002-07-18 | Texas Instruments Deutschland | clock generator |
WO2003036607A1 (en) * | 2001-10-25 | 2003-05-01 | Fujitsu Limited | Display control device |
US7446732B2 (en) | 2001-10-25 | 2008-11-04 | Fujitsu Limited | Display control device |
EP1329840A3 (en) * | 2002-01-16 | 2003-08-27 | Xerox Corporation | Method and reducing electromagnetic emissions (emi) from led bar systems |
EP1329840A2 (en) * | 2002-01-16 | 2003-07-23 | Xerox Corporation | Method and reducing electromagnetic emissions (emi) from led bar systems |
US6762784B2 (en) | 2002-01-16 | 2004-07-13 | Xerox Corporation | Method of reducing electromagnetic emissions (EMI) from LED bar systems |
US6798303B2 (en) | 2002-01-30 | 2004-09-28 | Infineon Technologies Ag | Clock signal generating device |
US7224349B2 (en) | 2002-06-18 | 2007-05-29 | Seiko Epson Corporation | Electronic apparatus |
EP1376531A3 (en) * | 2002-06-18 | 2005-06-08 | Seiko Epson Corporation | Electronic apparatus with reduced electromagnetic interference noise |
EP1477956A3 (en) * | 2003-05-16 | 2008-05-07 | Canon Kabushiki Kaisha | Drive control apparatus and drive control method for a cold cathode field emission display panel |
EP1592154A2 (en) * | 2004-04-29 | 2005-11-02 | Linear Technology Corporation | Methods and circuits for frequency modulation that reduce the spectral noise of switching regulators |
EP1592154A3 (en) * | 2004-04-29 | 2011-04-06 | Linear Technology Corporation | Methods and circuits for frequency modulation that reduce the spectral noise of switching regulators |
ES2267364A1 (en) * | 2004-11-23 | 2007-03-01 | Universitat Politecnica De Catalunya | Modulation circuit for reducing harmonics of interference in power converters has reduction circuitry whose operation depends on modulation of frequency of commutation signal |
US8174326B1 (en) | 2005-06-30 | 2012-05-08 | Cypress Semiconductor Corporation | Phase lock loop control error selection system and method |
US7813411B1 (en) | 2005-06-30 | 2010-10-12 | Cypress Semiconductor Corporation | Spread spectrum frequency synthesizer with high order accumulation for frequency profile generation |
US7912109B1 (en) | 2005-06-30 | 2011-03-22 | Cypress Semiconductor Corporation | Spread spectrum frequency synthesizer with first order accumulation for frequency profile generation |
US7932787B1 (en) | 2005-06-30 | 2011-04-26 | Cypress Semiconductor Corporation | Phase lock loop control system and method |
US7948327B1 (en) | 2005-06-30 | 2011-05-24 | Cypress Semiconductor Corporation | Simplified phase lock loop control model system and method |
US7961059B1 (en) | 2005-06-30 | 2011-06-14 | Cypress Semiconductor Corporation | Phase lock loop control system and method with non-consecutive feedback divide values |
US7813410B1 (en) | 2005-09-02 | 2010-10-12 | Cypress Semiconductor Corporation | Initiating spread spectrum modulation |
EP1835724A2 (en) * | 2006-03-17 | 2007-09-19 | Ricoh Company, Ltd. | Black-level feedback device, image reading device, and black-level feedback control method |
EP1835724A3 (en) * | 2006-03-17 | 2009-03-25 | Ricoh Company, Ltd. | Black-level feedback device, image reading device, and black-level feedback control method |
US7719724B2 (en) | 2006-03-17 | 2010-05-18 | Ricoh Company, Ltd. | Black-level feedback device, image reading device, and black-level feedback control method |
EP1858157A1 (en) * | 2006-05-15 | 2007-11-21 | STMicroelectronics Pvt. Ltd. | Spread spectrum clock generation system |
WO2009018108A1 (en) * | 2007-07-27 | 2009-02-05 | Pulsecore Semiconductor Corporation | Usb system with spread spectrum emi reduction |
WO2009019460A1 (en) * | 2007-08-03 | 2009-02-12 | Wolfson Microelectronics Plc | Amplifier circuit and method of amplifying a signal in an amplifier circuit |
US8198941B2 (en) | 2007-08-03 | 2012-06-12 | Wolfson Microelectronics Plc | Amplifier circuit and method of amplifying a signal in an amplifier circuit |
US8514025B2 (en) | 2007-08-03 | 2013-08-20 | Wolfson Microelectronics Plc | Amplifier circuit and method of amplifying a signal in an amplifier circuit |
US8988149B2 (en) | 2007-08-03 | 2015-03-24 | Cirrus Logic International (Uk) Limited | Amplifier circuit and method of amplifying a signal in an amplifier circuit |
US9252729B2 (en) | 2007-08-03 | 2016-02-02 | Cirrus Logic International Semiconductor Ltd. | Amplifier circuit and method of amplifying a signal in an amplifier circuit |
WO2013174377A3 (en) * | 2012-05-23 | 2014-01-30 | Silicon Line Gmbh | Circuit arrangement and method for calibrating activation signals for voltage-controlled oscillators |
US9484929B2 (en) | 2012-05-23 | 2016-11-01 | Silicon Line Gmbh | Circuit arrangement and method for calibrating activation signals for voltage-controlled oscillators |
Also Published As
Publication number | Publication date |
---|---|
DE69633651D1 (en) | 2004-11-25 |
DE69633651T2 (en) | 2006-03-09 |
EP0739089B1 (en) | 2004-10-20 |
EP1494349A1 (en) | 2005-01-05 |
EP1494349B1 (en) | 2006-08-23 |
DE69636488T2 (en) | 2007-08-16 |
US5631920A (en) | 1997-05-20 |
US5872807A (en) | 1999-02-16 |
JP3899395B2 (en) | 2007-03-28 |
EP0739089A3 (en) | 1998-09-16 |
DE69636488D1 (en) | 2006-10-05 |
JPH0998152A (en) | 1997-04-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1494349B1 (en) | Spread spectrum clock generator | |
EP1073194B1 (en) | Spread spectrum clock generator and associated method | |
EP1329019B1 (en) | Segmented spectrum clock generator apparatus and method for using same | |
US5943382A (en) | Dual-loop spread-spectrum clock generator with master PLL and slave voltage-modulation-locked loop | |
EP0521859B1 (en) | Direct digital synthesizer driven phase lock loop frequency synthesizer with hard limiter | |
US7397883B2 (en) | Spread spectrum type clock generation circuit for improving frequency modulation efficiency | |
US5736893A (en) | Digital method and apparatus for reducing EMI emissions in digitally-clocked systems | |
US6046646A (en) | Modulation of a phase locked loop for spreading the spectrum of an output clock signal | |
US4507796A (en) | Electronic apparatus having low radio frequency interference from system clock signal | |
US5463356A (en) | FM band multiple signal modulator | |
US6697416B1 (en) | Digital programmable, spread spectrum clock generator | |
US7313161B2 (en) | Spread spectrum clock generator and method of generating spread spectrum clock | |
Li et al. | Dual-loop spread-spectrum clock generator | |
US5430392A (en) | Clock system and method for reducing the measured level of unintentional electromagnetic emissions from an electronic device | |
EP1543622B1 (en) | Waveform lineariser | |
GB2547551A (en) | An electronic circuit | |
JPS6351563B2 (en) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB |
|
RHK1 | Main classification (correction) |
Ipc: H01S 3/03 |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB |
|
RHK1 | Main classification (correction) |
Ipc: H03B 29/00 |
|
17P | Request for examination filed |
Effective date: 19990226 |
|
17Q | First examination report despatched |
Effective date: 20010730 |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REF | Corresponds to: |
Ref document number: 69633651 Country of ref document: DE Date of ref document: 20041125 Kind code of ref document: P |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
ET | Fr: translation filed | ||
26N | No opposition filed |
Effective date: 20050721 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20080602 Year of fee payment: 13 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091103 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20130422 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20130422 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: S28 Free format text: APPLICATION FILED |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: S28 Free format text: RESTORATION ALLOWED Effective date: 20140612 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20150422 Year of fee payment: 20 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 20 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20151027 Year of fee payment: 20 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: PE20 Expiry date: 20160421 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION Effective date: 20160421 |