EP0834081A4 - Method and apparatus for testing a megacell in an asic using jtag - Google Patents
Method and apparatus for testing a megacell in an asic using jtagInfo
- Publication number
- EP0834081A4 EP0834081A4 EP96922381A EP96922381A EP0834081A4 EP 0834081 A4 EP0834081 A4 EP 0834081A4 EP 96922381 A EP96922381 A EP 96922381A EP 96922381 A EP96922381 A EP 96922381A EP 0834081 A4 EP0834081 A4 EP 0834081A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- test
- megacell
- circuitry
- inputs
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
Abstract
Description
Claims
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US48048395A | 1995-06-07 | 1995-06-07 | |
US480483 | 1995-06-07 | ||
US52839795A | 1995-09-14 | 1995-09-14 | |
US528397 | 1995-09-14 | ||
PCT/US1996/008577 WO1996041206A1 (en) | 1995-06-07 | 1996-06-06 | Method and apparatus for testing a megacell in an asic using jtag |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0834081A1 EP0834081A1 (en) | 1998-04-08 |
EP0834081A4 true EP0834081A4 (en) | 1999-03-24 |
EP0834081B1 EP0834081B1 (en) | 2004-02-25 |
Family
ID=27046602
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP96922381A Expired - Lifetime EP0834081B1 (en) | 1995-06-07 | 1996-06-06 | Method and apparatus for testing a megacell in an asic using jtag |
Country Status (10)
Country | Link |
---|---|
US (1) | US5805609A (en) |
EP (1) | EP0834081B1 (en) |
JP (1) | JP3698166B2 (en) |
KR (1) | KR100248258B1 (en) |
CN (1) | CN1089441C (en) |
AU (1) | AU6251896A (en) |
DE (1) | DE69631658T2 (en) |
IL (2) | IL120927A (en) |
TW (1) | TW297096B (en) |
WO (2) | WO1996041205A1 (en) |
Families Citing this family (60)
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US6324614B1 (en) * | 1997-08-26 | 2001-11-27 | Lee D. Whetsel | Tap with scannable control circuit for selecting first test data register in tap or second test data register in tap linking module for scanning data |
US6804725B1 (en) * | 1996-08-30 | 2004-10-12 | Texas Instruments Incorporated | IC with state machine controlled linking module |
GB9810512D0 (en) * | 1998-05-15 | 1998-07-15 | Sgs Thomson Microelectronics | Detecting communication errors across a chip boundary |
DE19981944D2 (en) | 1998-09-29 | 2002-08-29 | Siemens Ag | Application-specific module with reduced effort for revision |
KR20010112222A (en) * | 1998-11-30 | 2001-12-20 | 추후보정 | Method and software for user interface device in a last mile telecommunications cabling |
US6496544B1 (en) * | 1998-12-14 | 2002-12-17 | Cray Inc. | Digital computing system having adaptive communication components |
US7657810B2 (en) | 2006-02-03 | 2010-02-02 | Texas Instruments Incorporated | Scan testing using scan frames with embedded commands |
US7013415B1 (en) * | 1999-05-26 | 2006-03-14 | Renesas Technology Corp. | IC with internal interface switch for testability |
JP2001255356A (en) * | 2000-03-08 | 2001-09-21 | Matsushita Electric Ind Co Ltd | Test-pattern generation method and test method for semiconductor integrated circuit |
US6812726B1 (en) | 2002-11-27 | 2004-11-02 | Inapac Technology, Inc. | Entering test mode and accessing of a packaged semiconductor device |
US6754866B1 (en) * | 2001-09-28 | 2004-06-22 | Inapac Technology, Inc. | Testing of integrated circuit devices |
US7240254B2 (en) * | 2000-09-21 | 2007-07-03 | Inapac Technology, Inc | Multiple power levels for a chip within a multi-chip semiconductor package |
US7444575B2 (en) * | 2000-09-21 | 2008-10-28 | Inapac Technology, Inc. | Architecture and method for testing of an integrated circuit device |
US6732304B1 (en) * | 2000-09-21 | 2004-05-04 | Inapac Technology, Inc. | Chip testing within a multi-chip semiconductor package |
GB2379524A (en) * | 2001-09-06 | 2003-03-12 | Nec Technologies | Multiplexing pins on an ASIC |
US8286046B2 (en) | 2001-09-28 | 2012-10-09 | Rambus Inc. | Integrated circuit testing module including signal shaping interface |
US8166361B2 (en) | 2001-09-28 | 2012-04-24 | Rambus Inc. | Integrated circuit testing module configured for set-up and hold time testing |
US8001439B2 (en) * | 2001-09-28 | 2011-08-16 | Rambus Inc. | Integrated circuit testing module including signal shaping interface |
US7313740B2 (en) * | 2002-07-25 | 2007-12-25 | Inapac Technology, Inc. | Internally generating patterns for testing in an integrated circuit device |
US20040019841A1 (en) * | 2002-07-25 | 2004-01-29 | Ong Adrian E. | Internally generating patterns for testing in an integrated circuit device |
US7061263B1 (en) | 2001-11-15 | 2006-06-13 | Inapac Technology, Inc. | Layout and use of bond pads and probe pads for testing of integrated circuits devices |
JP4173768B2 (en) * | 2002-05-21 | 2008-10-29 | 松下電器産業株式会社 | Circuit device and operation method thereof |
US7219281B2 (en) * | 2002-07-29 | 2007-05-15 | Stmicroelectronics Pvt. Ltd. | Boundary scan of integrated circuits |
KR100500442B1 (en) * | 2002-11-07 | 2005-07-12 | 삼성전자주식회사 | Semiconductor memory device and test method thereof |
US8063650B2 (en) | 2002-11-27 | 2011-11-22 | Rambus Inc. | Testing fuse configurations in semiconductor devices |
US20050149783A1 (en) * | 2003-12-11 | 2005-07-07 | International Business Machines Corporation | Methods and apparatus for testing an IC |
US7284172B2 (en) * | 2004-04-30 | 2007-10-16 | International Business Machines Corporation | Access method for embedded JTAG TAP controller instruction registers |
US7814377B2 (en) * | 2004-07-09 | 2010-10-12 | Sandisk Corporation | Non-volatile memory system with self test capability |
DE102004043063B4 (en) * | 2004-09-06 | 2008-10-23 | Infineon Technologies Ag | Method for operating a semiconductor device with a test module |
CN100365423C (en) * | 2004-10-20 | 2008-01-30 | 华为技术有限公司 | Automatic connecting system for JTAG chain and implementing method thereof |
US7589648B1 (en) * | 2005-02-10 | 2009-09-15 | Lattice Semiconductor Corporation | Data decompression |
FR2888433A1 (en) * | 2005-07-05 | 2007-01-12 | St Microelectronics Sa | PROTECTION OF A DIGITAL QUANTITY CONTAINED IN AN INTEGRATED CIRCUIT COMPRISING A JTAG INTERFACE |
US7274203B2 (en) * | 2005-10-25 | 2007-09-25 | Freescale Semiconductor, Inc. | Design-for-test circuit for low pin count devices |
ATE472107T1 (en) * | 2005-11-02 | 2010-07-15 | Nxp Bv | IC TEST METHODS AND APPARATUS |
CN100442242C (en) * | 2006-02-28 | 2008-12-10 | 环达电脑(上海)有限公司 | Apparatus and system for testing host slot |
US7511641B1 (en) | 2006-09-19 | 2009-03-31 | Lattice Semiconductor Corporation | Efficient bitstream compression |
WO2008042403A2 (en) | 2006-10-03 | 2008-04-10 | Inapac Technologies, Inc. | Memory accessing circuit system |
US8079071B2 (en) | 2006-11-14 | 2011-12-13 | SanDisk Technologies, Inc. | Methods for accessing content based on a session ticket |
US20080114772A1 (en) * | 2006-11-14 | 2008-05-15 | Fabrice Jogand-Coulomb | Method for connecting to a network location associated with content |
US20080112562A1 (en) * | 2006-11-14 | 2008-05-15 | Fabrice Jogand-Coulomb | Methods for linking content with license |
US20080114693A1 (en) * | 2006-11-14 | 2008-05-15 | Fabrice Jogand-Coulomb | Method for allowing content protected by a first DRM system to be accessed by a second DRM system |
US8327454B2 (en) * | 2006-11-14 | 2012-12-04 | Sandisk Technologies Inc. | Method for allowing multiple users to access preview content |
US8763110B2 (en) * | 2006-11-14 | 2014-06-24 | Sandisk Technologies Inc. | Apparatuses for binding content to a separate memory device |
CN101102566B (en) * | 2007-06-25 | 2010-12-08 | 中兴通讯股份有限公司 | A design method and debugging method for mobile phone JTAG debugging interface signals |
US7657805B2 (en) * | 2007-07-02 | 2010-02-02 | Sun Microsystems, Inc. | Integrated circuit with blocking pin to coordinate entry into test mode |
US8051338B2 (en) * | 2007-07-19 | 2011-11-01 | Cray Inc. | Inter-asic data transport using link control block manager |
US7902865B1 (en) | 2007-11-15 | 2011-03-08 | Lattice Semiconductor Corporation | Compression and decompression of configuration data using repeated data frames |
US8621125B2 (en) * | 2009-10-13 | 2013-12-31 | Intellitech Corporation | System and method of sending and receiving data and commands using the TCK and TMS of IEEE 1149.1 |
CN102236066B (en) * | 2010-04-22 | 2015-07-01 | 上海华虹集成电路有限责任公司 | Method for realizing rapid debugging and locating of chip functional fault and debugging circuit |
CN103097902B (en) * | 2010-07-29 | 2015-12-09 | 德克萨斯仪器股份有限公司 | Improve test access port operation at full speed |
US8694844B2 (en) | 2010-07-29 | 2014-04-08 | Texas Instruments Incorporated | AT speed TAP with dual port router and command circuit |
CN102778645B (en) * | 2011-05-09 | 2014-09-17 | 京微雅格(北京)科技有限公司 | JTAG (joint test action group) main controller and realization method of JTAG main controller |
CN104899123B (en) * | 2015-04-24 | 2017-06-06 | 英业达科技有限公司 | The connecting test apparatus and method of the address setting signal of dimm socket on a kind of mainboard |
KR20160139496A (en) * | 2015-05-27 | 2016-12-07 | 에스케이하이닉스 주식회사 | Semiconductor device and semiconductor system |
CN108957283B (en) * | 2017-05-19 | 2021-08-03 | 龙芯中科技术股份有限公司 | Irradiation experiment board, monitoring terminal and ASIC chip irradiation experiment system |
CN107843828A (en) * | 2017-10-26 | 2018-03-27 | 电子科技大学 | A kind of digital circuit boundary scan control system based on FPGA |
CN109917277B (en) * | 2019-05-16 | 2019-08-23 | 上海燧原智能科技有限公司 | Virtual measuring method, device, equipment and storage medium |
US10746798B1 (en) | 2019-05-31 | 2020-08-18 | Nvidia Corp. | Field adaptable in-system test mechanisms |
US11204849B2 (en) * | 2020-03-13 | 2021-12-21 | Nvidia Corporation | Leveraging low power states for fault testing of processing cores at runtime |
CN113938125B (en) * | 2021-10-19 | 2023-02-24 | 浙江大学 | Multi-channel configurable testable and trimming digital signal isolator |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0330841A2 (en) * | 1988-01-29 | 1989-09-06 | Kabushiki Kaisha Toshiba | Logic circuit with a test function |
EP0549130A2 (en) * | 1991-12-26 | 1993-06-30 | AT&T Corp. | Partial-scan built-in self-test technique |
EP0651261A2 (en) * | 1993-11-02 | 1995-05-03 | International Business Machines Corporation | System and method for testing a circuit network having elements testable by different boundary scan standards |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4855669A (en) * | 1987-10-07 | 1989-08-08 | Xilinx, Inc. | System for scan testing of logic circuit networks |
US4947395A (en) * | 1989-02-10 | 1990-08-07 | Ncr Corporation | Bus executed scan testing method and apparatus |
US5115435A (en) * | 1989-10-19 | 1992-05-19 | Ncr Corporation | Method and apparatus for bus executed boundary scanning |
JP2627464B2 (en) * | 1990-03-29 | 1997-07-09 | 三菱電機株式会社 | Integrated circuit device |
JP2705326B2 (en) * | 1991-02-19 | 1998-01-28 | 日本電気株式会社 | Magneto-optical head device |
JP2741119B2 (en) * | 1991-09-17 | 1998-04-15 | 三菱電機株式会社 | Bypass scan path and integrated circuit device using the same |
US5448576A (en) * | 1992-10-29 | 1995-09-05 | Bull Hn Information Systems Inc. | Boundary scan architecture extension |
US5442640A (en) * | 1993-01-19 | 1995-08-15 | International Business Machines Corporation | Test and diagnosis of associated output logic for products having embedded arrays |
US5418470A (en) * | 1993-10-22 | 1995-05-23 | Tektronix, Inc. | Analog multi-channel probe system |
US5809036A (en) * | 1993-11-29 | 1998-09-15 | Motorola, Inc. | Boundary-scan testable system and method |
GB2288666B (en) * | 1994-04-12 | 1997-06-25 | Advanced Risc Mach Ltd | Integrated circuit control |
US5617431A (en) * | 1994-08-02 | 1997-04-01 | Advanced Micro Devices, Inc. | Method and apparatus to reuse existing test patterns to test a single integrated circuit containing previously existing cores |
US5596585A (en) * | 1995-06-07 | 1997-01-21 | Advanced Micro Devices, Inc. | Performance driven BIST technique |
-
1996
- 1996-06-06 TW TW085106886A patent/TW297096B/zh not_active IP Right Cessation
- 1996-06-06 WO PCT/US1996/008576 patent/WO1996041205A1/en active IP Right Grant
- 1996-06-06 EP EP96922381A patent/EP0834081B1/en not_active Expired - Lifetime
- 1996-06-06 CN CN96194624A patent/CN1089441C/en not_active Expired - Fee Related
- 1996-06-06 KR KR1019970708528A patent/KR100248258B1/en not_active IP Right Cessation
- 1996-06-06 IL IL12092796A patent/IL120927A/en not_active IP Right Cessation
- 1996-06-06 JP JP50112397A patent/JP3698166B2/en not_active Expired - Fee Related
- 1996-06-06 AU AU62518/96A patent/AU6251896A/en not_active Abandoned
- 1996-06-06 WO PCT/US1996/008577 patent/WO1996041206A1/en active IP Right Grant
- 1996-06-06 DE DE69631658T patent/DE69631658T2/en not_active Expired - Lifetime
-
1997
- 1997-05-28 IL IL12092797A patent/IL120927A0/en unknown
- 1997-06-27 US US08/883,803 patent/US5805609A/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0330841A2 (en) * | 1988-01-29 | 1989-09-06 | Kabushiki Kaisha Toshiba | Logic circuit with a test function |
EP0549130A2 (en) * | 1991-12-26 | 1993-06-30 | AT&T Corp. | Partial-scan built-in self-test technique |
EP0651261A2 (en) * | 1993-11-02 | 1995-05-03 | International Business Machines Corporation | System and method for testing a circuit network having elements testable by different boundary scan standards |
Non-Patent Citations (2)
Title |
---|
ROBINSON G D ET AL: "INTERCONNECT TESTING OF BOARDS WITH PARTIAL BOUNDARY SCAN", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE, WASHINGTON, SEPT. 10 - 14, 1990, no. CONF. 21, 10 September 1990 (1990-09-10), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 572 - 581, XP000203682 * |
See also references of WO9641206A1 * |
Also Published As
Publication number | Publication date |
---|---|
CN1089441C (en) | 2002-08-21 |
KR100248258B1 (en) | 2000-03-15 |
JPH11506833A (en) | 1999-06-15 |
DE69631658D1 (en) | 2004-04-01 |
EP0834081A1 (en) | 1998-04-08 |
DE69631658T2 (en) | 2004-12-16 |
IL120927A0 (en) | 1997-09-30 |
WO1996041206A1 (en) | 1996-12-19 |
US5805609A (en) | 1998-09-08 |
KR19990022049A (en) | 1999-03-25 |
EP0834081B1 (en) | 2004-02-25 |
JP3698166B2 (en) | 2005-09-21 |
WO1996041205A1 (en) | 1996-12-19 |
TW297096B (en) | 1997-02-01 |
AU6251896A (en) | 1996-12-30 |
IL120927A (en) | 2000-06-01 |
CN1187244A (en) | 1998-07-08 |
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