EP0852765B1 - Memory management - Google Patents
Memory management Download PDFInfo
- Publication number
- EP0852765B1 EP0852765B1 EP96901894A EP96901894A EP0852765B1 EP 0852765 B1 EP0852765 B1 EP 0852765B1 EP 96901894 A EP96901894 A EP 96901894A EP 96901894 A EP96901894 A EP 96901894A EP 0852765 B1 EP0852765 B1 EP 0852765B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- address
- data
- data block
- address field
- field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
- G06F3/0664—Virtualisation aspects at device level, e.g. emulation of a storage device or system
Definitions
- This invention relates to data storage systems and, in particular, to a method of managing a memory in which data can only be written in unwritten memory locations, so that the information stored in the memory can be updated without erasing entire blocks each time the data stored is to be changed.
- One application of the present invention is in solid state memories which use FLASH memory for the main storage of data and which use FLASH lookup tables to perform the logical to physical address translation.
- This invention may be used with a number of different memory cells, such as FLASH EPROM cells, chalcogenide memory cells, and ferro-optic cells.
- Solid state disks receive addresses from the host they are serving in the form of a logical sector address (or by a transformation of Cylinder-Head-Sector addressing from the host).
- This logical sector addressing is continuous.
- the logical sector address is mapped to a physical sector address.
- the physical sector address defines the ordering of sectors in physical memory. Since logical sectors may be assigned to physical sectors in any order, the translation cannot be performed by an algorithm: some form of mapping is required. This mapping is usually performed by means of a lookup table. However, if the lookup table is also composed of FLASH memory cells then individual entries can only be updated by means of a block erasure. This is very inefficient.
- WO 94 20906 relates to a FLASH file system. It uses a block allocation map to store information on the blocks in main FLASH memory which can be written to. When a block is to be updated the allocation map is scanned until a free block is located. A transfer unit is used to facilitate memory reclaiming of the system. The transfer unit is an unwritten erased block of memory. The active (currently valid) data from a block of memory that contains old data (the old block) is written to the same locations in the transfer unit (the new block) and the old block is erased. The old block then becomes the transfer unit.
- the invention disclosed in WO 94 20906 requires a random access memory to reflect the changes in the block allocation map. The present invention does not require a random access memory, all of the functions necessary to manage the data updating can be performed on non-volatile block erasable memory such as FLASH EPROM.
- EP 0 597 706 relates to a solid state peripheral storage device which uses a MAP ROM to map the logical sector address provided by the host to a physical address in the semiconductor memory.
- the addresses of any bad sectors in semiconductor memory are recorded in the MAP ROM.
- a microsequencer is used to control the mapping.
- the MAP ROM is updated when a new physical address is required.
- the invention relates to floating-gate memories; the method of updating the MAP ROM described in the patent application shows that the MAP ROM could not be a FLASH memory because the MAP ROM must be byte erasable to enable each entry to be updated independently.
- WO 95 10083 discloses the use of a CAM (content addressable memory) to search for an address which includes a flag field. The address is searched so that only an address with its flag set to a particular value is found as a match. When an address stores data which becomes obsolete its flag is reset. Thus, only the address with valid data has its flag set, the same logical address (but different physical address) having old data has its flag reset.
- a CAM content addressable memory
- the present invention provides a data storage system as set out in claims 1 to 6.
- Figures 1A, 1B and 1C illustrate the principle of translating between two addresses using an indirect address field and a direct address field.
- Every solid state memory system must convert logical sector addresses received from the host to physical addresses which can be used to address the particular solid state memory devices which are used as the main memory store. Thus, some logical to physical address conversion is required.
- This embodiment of the present invention uses two lookup tables to maintain a mapping between a logical sector address and its corresponding physical sector address. In other embodiments of this invention only one table may be used, the table performing the same function as the two lookup tables or the previous embodiment.
- a lookup table entry 10 for each logical sector address value is located in the primary lookup table 12 at a location defined by an address equal to the logical sector address plus the primary lookup table offset.
- Each entry in the primary lookup table 12 contains at least three fields: one field stores a main memory address 14, another field stores a linked address 16; and the third field is a pointer flag 18.
- Each used entry in the primary lookup table 12 either points directly at the physical address of a sector in main memory 20 or provides an indirect pointer to a secondary lookup table 22.
- the means of determining whether the primary lookup table entry points to the main memory 20 or whether it points to the secondary lookup table 22 is to read the pointer flag IS in the relevant table entry. If the pointer flag 18 is erased (shown by the letter E in Figures 1A and 1B) then the main memory address is valid. If the pointer is unerased (shown by the letter U in Figures 1A and 1B) then the secondary lookup table address is valid.
- Figure 1B illustrates how the lookup tables are updated to ensure correct mapping between the logical sector address and the new physical address.
- the entry 26 in the primary lookup table 12 now needs to be updated with the address of the main memory location 28 for the new data. This is done by writing the pointer flag in the entry corresponding to the logical sector address 26 to logic zero (unset) and the linked address to one of the unused entries in the secondary lookup table 22 (hereinafter referred to as the xxx secondary table entry 32).
- the pointer flag can be written because it occupies an addressable unit and because it has not been written to since the erase cycle: the inactive state of the pointer is the erased state (logic one).
- the address of the memory location to which the new data was written is stored in the main memory address field 14 of the xxx secondary lookup table entry 32.
- this latest data is stored in another unused location (this will be referred to as the latest unused location) in main memory 34.
- the primary lookup table 12 is not altered. but the xxx entry in the secondary lookup table 2 now has its pointer flag 30 written so that it is unset (logic zero) and the linked address field is written so that it points to an unused entry in the secondary lookup table (this will be referred to as the yyy secondary lookup table entry 36).
- the address of the latest unused location is then stored in the main memory field 14 of the yyy secondary lookup table entry 36. This process may continue until the number of unused entries in the secondary lookup table 22 drops below a predetermined value.
- the secondary lookup table 22 becomes full then a clean-up operation is required.
- a new lookup table must be created before the old one is erased to safeguard the information.
- One way of performing a clean-up operation is to reserve at least one erasable FLASH block in the erased state either above or below the primary lookup table 12.
- One entry from the primary lookup table 12 is copied to the erased block and the old entry is then erased.
- the main memory address field 14 for that entry is copied from the relevant valid secondary lookup table entry (the entry with its pointer flag in the erased condition). In effect the primary lookup table 12 moves up or down by one erase block. Once this process is complete the secondary lookup table 22 can be erased.
- a main memory address In other embodiments of the present invention only two fields are used: a main memory address and a secondary lookup table address. If the secondary lookup table address contains valid data then that address is read instead of the main memory address. If the secondary lookup table address does not contain valid data then the main memory address is read instead.
Abstract
Description
- This invention relates to data storage systems and, in particular, to a method of managing a memory in which data can only be written in unwritten memory locations, so that the information stored in the memory can be updated without erasing entire blocks each time the data stored is to be changed. One application of the present invention is in solid state memories which use FLASH memory for the main storage of data and which use FLASH lookup tables to perform the logical to physical address translation. This invention may be used with a number of different memory cells, such as FLASH EPROM cells, chalcogenide memory cells, and ferro-optic cells. Solid state disks receive addresses from the host they are serving in the form of a logical sector address (or by a transformation of Cylinder-Head-Sector addressing from the host). This logical sector addressing is continuous. The logical sector address is mapped to a physical sector address. The physical sector address defines the ordering of sectors in physical memory. Since logical sectors may be assigned to physical sectors in any order, the translation cannot be performed by an algorithm: some form of mapping is required. This mapping is usually performed by means of a lookup table. However, if the lookup table is also composed of FLASH memory cells then individual entries can only be updated by means of a block erasure. This is very inefficient.
- In recent years there has been a flurry of activity in the realm of solid state disk devices. This activity has been intensified with the advent of laptop and palmtop portable computers. and the PCMCIA standard. A number of patent applications which have been filed relate to the control methods needed for using FLASH memory as the main data store.
- WO 94 20906 relates to a FLASH file system. It uses a block allocation map to store information on the blocks in main FLASH memory which can be written to. When a block is to be updated the allocation map is scanned until a free block is located. A transfer unit is used to facilitate memory reclaiming of the system. The transfer unit is an unwritten erased block of memory. The active (currently valid) data from a block of memory that contains old data (the old block) is written to the same locations in the transfer unit (the new block) and the old block is erased. The old block then becomes the transfer unit. The invention disclosed in WO 94 20906 requires a random access memory to reflect the changes in the block allocation map. The present invention does not require a random access memory, all of the functions necessary to manage the data updating can be performed on non-volatile block erasable memory such as FLASH EPROM.
- EP 0 597 706 relates to a solid state peripheral storage device which uses a MAP ROM to map the logical sector address provided by the host to a physical address in the semiconductor memory. The addresses of any bad sectors in semiconductor memory are recorded in the MAP ROM. A microsequencer is used to control the mapping. The MAP ROM is updated when a new physical address is required. The invention relates to floating-gate memories; the method of updating the MAP ROM described in the patent application shows that the MAP ROM could not be a FLASH memory because the MAP ROM must be byte erasable to enable each entry to be updated independently.
- WO 95 10083 discloses the use of a CAM (content addressable memory) to search for an address which includes a flag field. The address is searched so that only an address with its flag set to a particular value is found as a match. When an address stores data which becomes obsolete its flag is reset. Thus, only the address with valid data has its flag set, the same logical address (but different physical address) having old data has its flag reset.
- The present invention provides a data storage system as set out in claims 1 to 6.
- The invention will now be particularly described, by way of example, with reference to the accompanying drawings, in which:
Figures 1A, 1B and 1C illustrate the principle of translating between two addresses using an indirect address field and a direct address field. - Every solid state memory system must convert logical sector addresses received from the host to physical addresses which can be used to address the particular solid state memory devices which are used as the main memory store. Thus, some logical to physical address conversion is required. This embodiment of the present invention uses two lookup tables to maintain a mapping between a logical sector address and its corresponding physical sector address. In other embodiments of this invention only one table may be used, the table performing the same function as the two lookup tables or the previous embodiment.
- Referring to Figure 1A, a lookup table entry 10 for each logical sector address value is located in the primary lookup table 12 at a location defined by an address equal to the logical sector address plus the primary lookup table offset.
- Each entry in the primary lookup table 12 contains at least three fields: one field stores a main memory address 14, another field stores a linked address 16; and the third field is a pointer flag 18. Each used entry in the primary lookup table 12 either points directly at the physical address of a sector in main memory 20 or provides an indirect pointer to a secondary lookup table 22. In the present embodiment the means of determining whether the primary lookup table entry points to the main memory 20 or whether it points to the secondary lookup table 22 is to read the pointer flag IS in the relevant table entry. If the pointer flag 18 is erased (shown by the letter E in Figures 1A and 1B) then the main memory address is valid. If the pointer is unerased (shown by the letter U in Figures 1A and 1B) then the secondary lookup table address is valid.
- Consider the case when there is no data stored in the main memory 20. When data is first written then a logical sector address is supplied by the host together with the data to be stored. The data is stored in a physical location 24 in main memory 20 and the address of this physical location 24 in main memory 20 is stored in the primary lookup table 12 at an entry 26 corresponding to the logical sector address supplied by the host. If, at some later time the data is deleted by the host and new data is sent with the same logical sector address as the old data, then the new data is stored in an unused main memory location 28 (the previous main memory location 24 cannot be overwritten because FLASH memory needs an erase cycle after being written). The primary lookup table 12 must now be updated. This is illustrated in Figure IB.
- Figure 1B illustrates how the lookup tables are updated to ensure correct mapping between the logical sector address and the new physical address. The entry 26 in the primary lookup table 12 now needs to be updated with the address of the main memory location 28 for the new data. This is done by writing the pointer flag in the entry corresponding to the logical sector address 26 to logic zero (unset) and the linked address to one of the unused entries in the secondary lookup table 22 (hereinafter referred to as the xxx secondary table entry 32). The pointer flag can be written because it occupies an addressable unit and because it has not been written to since the erase cycle: the inactive state of the pointer is the erased state (logic one). The address of the memory location to which the new data was written is stored in the main memory address field 14 of the xxx secondary lookup table entry 32.
- If, at some later time, the new data is deleted by the host and more data is sent (this will be referred to as the latest data) then this latest data is stored in another unused location (this will be referred to as the latest unused location) in main memory 34. This is illustrated in Figure 1C. The primary lookup table 12 is not altered. but the xxx entry in the secondary lookup table 2 now has its pointer flag 30 written so that it is unset (logic zero) and the linked address field is written so that it points to an unused entry in the secondary lookup table (this will be referred to as the yyy secondary lookup table entry 36). The address of the latest unused location is then stored in the main memory field 14 of the yyy secondary lookup table entry 36. This process may continue until the number of unused entries in the secondary lookup table 22 drops below a predetermined value.
- Once the secondary lookup table 22 becomes full then a clean-up operation is required. When the primary lookup table 12 is cleaned-up, a new lookup table must be created before the old one is erased to safeguard the information. One way of performing a clean-up operation is to reserve at least one erasable FLASH block in the erased state either above or below the primary lookup table 12. One entry from the primary lookup table 12 is copied to the erased block and the old entry is then erased. As each entry is copied, the main memory address field 14 for that entry is copied from the relevant valid secondary lookup table entry (the entry with its pointer flag in the erased condition). In effect the primary lookup table 12 moves up or down by one erase block. Once this process is complete the secondary lookup table 22 can be erased.
- In other embodiments of the present invention only two fields are used: a main memory address and a secondary lookup table address. If the secondary lookup table address contains valid data then that address is read instead of the main memory address. If the secondary lookup table address does not contain valid data then the main memory address is read instead.
Claims (6)
- A data storage system for use with a host system and comprising: a plurality of erasable solid-state data storage means (20), wherein each of said storage means is locatable by a unique physical address and each of said storage means, once written, must be erased prior to being rewritten; and control means (12, 22) including non-volatile block erasable storage means for storing a look-up table mapping a plurality of logical addresses received from the host to a corresponding plurality of physical addresses of said data storage means, characterised in that said storage means of the control means comprises a plurality of data blocks, there being a respective said data block for each of said logical addresses, and the control means further includes a plurality of spare data blocks, and wherein each said data block and each said spare data block comprises a direct address field (14) and an indirect address field (16), and the control means further includes means for programming the direct address field of the respective said data block of the storage means, the first time a said logical address is supplied from the host with data for writing to the data storage means, with a physical address corresponding to said logical address, and means for programming the indirect address field of said respective data block with the address of an unused said spare data block, and the direct address field of the said spare data block with a new physical address corresponding to the same said logical address, the next time that new data is written to the same said logical address.
- A data storage system according to claim 1 characterised in that the control means further includes means for programming the indirect address field of said spare data block with the address of another unused spare data block, and the direct address field of the latter said unused spare data block with a latest physical address corresponding to the same said logical address, each subsequent time that new data is written to the same said logical address, until the number of unused spare data blocks drops below a predetermined minimum.
- A data storage system according to claim 1 characterised in that each said data block further includes a pointer flag field (18) and the control means includes means for storing a pointer flag in said pointer flag field, for indicating whether the direct address field or the indirect address field of the data block is to be read.
- A data storage system according to claim 3 characterised in that said pointer flag field of each said data block is writable independently of the rest of the data block.
- A data storage system according to claim 3 or 4 characterised in that said pointer flag field of each said data block has an erased state indicating that the indirect address field of the data block is not programmed, and an unerased state indicating that the indirect address field of the data block is programmed.
- A data storage system according to any one of the preceding claims characterised in that the system incorporates means to clean up the data blocks when the number of unused spare data blocks drops below a predetermined threshold.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9519669 | 1995-09-27 | ||
GB9519669A GB2291990A (en) | 1995-09-27 | 1995-09-27 | Flash-memory management system |
PCT/GB1996/000249 WO1997012324A1 (en) | 1995-09-27 | 1996-02-06 | Memory management |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0852765A1 EP0852765A1 (en) | 1998-07-15 |
EP0852765B1 true EP0852765B1 (en) | 2001-09-19 |
Family
ID=10781331
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP96901894A Expired - Lifetime EP0852765B1 (en) | 1995-09-27 | 1996-02-06 | Memory management |
Country Status (8)
Country | Link |
---|---|
EP (1) | EP0852765B1 (en) |
JP (3) | JP2000505215A (en) |
KR (1) | KR19990063714A (en) |
CN (1) | CN1197520A (en) |
AT (1) | ATE205946T1 (en) |
DE (1) | DE69615385D1 (en) |
GB (1) | GB2291990A (en) |
WO (1) | WO1997012324A1 (en) |
Cited By (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007019175A2 (en) * | 2005-08-03 | 2007-02-15 | Sandisk Corporation | Indexing of file data in reprogrammable non-volatile memories that directly store data files |
US7634624B2 (en) | 2001-09-28 | 2009-12-15 | Micron Technology, Inc. | Memory system for data storage and retrieval |
US7669003B2 (en) | 2005-08-03 | 2010-02-23 | Sandisk Corporation | Reprogrammable non-volatile memory systems with indexing of directly stored data files |
US7681057B2 (en) | 2001-09-28 | 2010-03-16 | Lexar Media, Inc. | Power management of non-volatile memory systems |
US7725628B1 (en) | 2004-04-20 | 2010-05-25 | Lexar Media, Inc. | Direct secondary device interface by a host |
US7734862B2 (en) | 2000-07-21 | 2010-06-08 | Lexar Media, Inc. | Block management for mass storage |
US7743290B2 (en) | 2004-08-27 | 2010-06-22 | Lexar Media, Inc. | Status of overall health of nonvolatile memory |
US7747837B2 (en) | 2005-12-21 | 2010-06-29 | Sandisk Corporation | Method and system for accessing non-volatile storage devices |
US7774576B2 (en) | 1995-07-31 | 2010-08-10 | Lexar Media, Inc. | Direct logical block addressing flash memory mass storage architecture |
US7814262B2 (en) | 2005-10-13 | 2010-10-12 | Sandisk Corporation | Memory system storing transformed units of data in fixed sized storage blocks |
US7865659B2 (en) | 2004-04-30 | 2011-01-04 | Micron Technology, Inc. | Removable storage device |
US7877539B2 (en) | 2005-02-16 | 2011-01-25 | Sandisk Corporation | Direct data file storage in flash memories |
US7908426B2 (en) | 1995-07-31 | 2011-03-15 | Lexar Media, Inc. | Moving sectors within a block of information in a flash memory mass storage architecture |
US7944762B2 (en) | 2001-09-28 | 2011-05-17 | Micron Technology, Inc. | Non-volatile memory control |
US7949845B2 (en) | 2005-08-03 | 2011-05-24 | Sandisk Corporation | Indexing of file data in reprogrammable non-volatile memories that directly store data files |
US7949822B2 (en) | 2004-08-27 | 2011-05-24 | Micron Technology, Inc. | Storage capacity status |
US7984233B2 (en) | 2005-02-16 | 2011-07-19 | Sandisk Corporation | Direct data file storage implementation techniques in flash memories |
US8055832B2 (en) | 2005-08-03 | 2011-11-08 | SanDisk Technologies, Inc. | Management of memory blocks that directly store data files |
US8078797B2 (en) | 1995-07-31 | 2011-12-13 | Micron Technology, Inc. | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
US8166488B2 (en) | 2002-02-22 | 2012-04-24 | Micron Technology, Inc. | Methods of directly accessing a mass storage data device |
US8171203B2 (en) | 1995-07-31 | 2012-05-01 | Micron Technology, Inc. | Faster write operations to nonvolatile memory using FSInfo sector manipulation |
US8214583B2 (en) | 2005-02-16 | 2012-07-03 | Sandisk Technologies Inc. | Direct file data programming and deletion in flash memories |
US8386695B2 (en) | 2001-09-28 | 2013-02-26 | Micron Technology, Inc. | Methods and apparatus for writing data to non-volatile memory |
Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2317720A (en) * | 1996-09-30 | 1998-04-01 | Nokia Mobile Phones Ltd | Managing Flash memory |
JPH11203191A (en) * | 1997-11-13 | 1999-07-30 | Seiko Epson Corp | Nonvolatile storage device, control method of nonvolatile storage device and information recording medium recorded with program for controlling nonvolatile storage device |
US6226728B1 (en) * | 1998-04-21 | 2001-05-01 | Intel Corporation | Dynamic allocation for efficient management of variable sized data within a nonvolatile memory |
GB9903490D0 (en) * | 1999-02-17 | 1999-04-07 | Memory Corp Plc | Memory system |
US6148354A (en) | 1999-04-05 | 2000-11-14 | M-Systems Flash Disk Pioneers Ltd. | Architecture for a universal serial bus-based PC flash disk |
GB2349242A (en) * | 1999-04-20 | 2000-10-25 | Inventec Corp | Flash memory architecture and rewrite method |
FR2799046B1 (en) * | 1999-09-24 | 2004-02-27 | Aton Systemes Sa | METHOD FOR THE RANDOM WRITING OF SECTORS OF A LOWER SIZE THAN THAT OF AN ERASE BLOCK IN A BLOCK ERASABLE MEMORY FOR WHICH ANY WRITING OF DATA REQUIRES THE ERASE OF THE BLOCK CONTAINING THE SAID DATA |
CN1088218C (en) | 1999-11-14 | 2002-07-24 | 邓国顺 | Electronic flash storage method and device for data processing system |
EP1376608A1 (en) * | 2002-06-28 | 2004-01-02 | Cp8 | Programming method in a nonvolatile memory and system for realisation of such a method |
KR100484147B1 (en) * | 2002-07-26 | 2005-04-18 | 삼성전자주식회사 | Flash memory management method |
CN100359886C (en) * | 2002-12-26 | 2008-01-02 | 华为技术有限公司 | Method for establishing and searching improved multi-stage searching table |
KR100562906B1 (en) * | 2003-10-08 | 2006-03-21 | 삼성전자주식회사 | Flash memory controling apparatus for xip in serial flash memory considering page priority and method using thereof and flash memory chip thereof |
US7356665B2 (en) * | 2003-12-17 | 2008-04-08 | International Business Machines Corporation | Method and system for machine memory power and availability management in a processing system supporting multiple virtual machines |
DE102004062245A1 (en) * | 2004-12-23 | 2006-07-13 | Giesecke & Devrient Gmbh | Management of data objects in a non-volatile overwritable memory |
US9104315B2 (en) | 2005-02-04 | 2015-08-11 | Sandisk Technologies Inc. | Systems and methods for a mass data storage system having a file-based interface to a host and a non-file-based interface to secondary storage |
KR100781517B1 (en) * | 2006-02-16 | 2007-12-03 | 삼성전자주식회사 | Mapping table managing apparatus and method for nonvolatile memory |
US7500023B2 (en) | 2006-10-10 | 2009-03-03 | International Business Machines Corporation | Facilitating input/output processing by using transport control words to reduce input/output communications |
US7502873B2 (en) | 2006-10-10 | 2009-03-10 | International Business Machines Corporation | Facilitating access to status and measurement data associated with input/output processing |
US8190841B2 (en) * | 2007-03-21 | 2012-05-29 | Intel Corporation | Method of managing sectors of a non-volatile memory |
KR101424782B1 (en) * | 2007-07-19 | 2014-08-04 | 삼성전자주식회사 | Solid state disk controller and data processing method thereof |
US8122179B2 (en) * | 2007-12-14 | 2012-02-21 | Silicon Motion, Inc. | Memory apparatus and method of evenly using the blocks of a flash memory |
US7908403B2 (en) | 2008-02-14 | 2011-03-15 | International Business Machines Corporation | Reserved device access contention reduction |
US8108570B2 (en) | 2008-02-14 | 2012-01-31 | International Business Machines Corporation | Determining the state of an I/O operation |
US7840718B2 (en) | 2008-02-14 | 2010-11-23 | International Business Machines Corporation | Processing of data to suspend operations in an input/output processing log-out system |
US7904605B2 (en) | 2008-02-14 | 2011-03-08 | International Business Machines Corporation | Computer command and response for determining the state of an I/O operation |
US8214562B2 (en) | 2008-02-14 | 2012-07-03 | International Business Machines Corporation | Processing of data to perform system changes in an input/output processing system |
US8166206B2 (en) | 2008-02-14 | 2012-04-24 | International Business Machines Corporation | Cancel instruction and command for determining the state of an I/O operation |
US8082481B2 (en) | 2008-02-14 | 2011-12-20 | International Business Machines Corporation | Multiple CRC insertion in an output data stream |
US8478915B2 (en) | 2008-02-14 | 2013-07-02 | International Business Machines Corporation | Determining extended capability of a channel path |
US8176222B2 (en) | 2008-02-14 | 2012-05-08 | International Business Machines Corporation | Early termination of an I/O operation in an I/O processing system |
US8117347B2 (en) | 2008-02-14 | 2012-02-14 | International Business Machines Corporation | Providing indirect data addressing for a control block at a channel subsystem of an I/O processing system |
US7890668B2 (en) | 2008-02-14 | 2011-02-15 | International Business Machines Corporation | Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous |
US8312189B2 (en) | 2008-02-14 | 2012-11-13 | International Business Machines Corporation | Processing of data to monitor input/output operations |
US7917813B2 (en) | 2008-02-14 | 2011-03-29 | International Business Machines Corporation | Exception condition determination at a control unit in an I/O processing system |
US8095847B2 (en) | 2008-02-14 | 2012-01-10 | International Business Machines Corporation | Exception condition handling at a channel subsystem in an I/O processing system |
US7941570B2 (en) | 2008-02-14 | 2011-05-10 | International Business Machines Corporation | Bi-directional data transfer within a single I/O operation |
US8001298B2 (en) | 2008-02-14 | 2011-08-16 | International Business Machines Corporation | Providing extended measurement data in an I/O processing system |
US7840717B2 (en) | 2008-02-14 | 2010-11-23 | International Business Machines Corporation | Processing a variable length device command word at a control unit in an I/O processing system |
US7937507B2 (en) | 2008-02-14 | 2011-05-03 | International Business Machines Corporation | Extended measurement word determination at a channel subsystem of an I/O processing system |
US8196149B2 (en) | 2008-02-14 | 2012-06-05 | International Business Machines Corporation | Processing of data to determine compatability in an input/output processing system |
US7899944B2 (en) | 2008-02-14 | 2011-03-01 | International Business Machines Corporation | Open exchange limiting in an I/O processing system |
US9052837B2 (en) | 2008-02-14 | 2015-06-09 | International Business Machines Corporation | Processing communication data in a ships passing condition |
US8055807B2 (en) | 2008-07-31 | 2011-11-08 | International Business Machines Corporation | Transport control channel program chain linking including determining sequence order |
US7904606B2 (en) | 2008-07-31 | 2011-03-08 | International Business Machines Corporation | Transport control channel program chain linked branching |
US7937504B2 (en) | 2008-07-31 | 2011-05-03 | International Business Machines Corporation | Transport control channel program message pairing |
TWI409819B (en) * | 2009-03-03 | 2013-09-21 | Silicon Motion Inc | Method of evenly using a plurality of blocks of a flash memory, and associated memory device and controller thereof |
US8332542B2 (en) | 2009-11-12 | 2012-12-11 | International Business Machines Corporation | Communication with input/output system devices |
JP5010723B2 (en) * | 2010-09-22 | 2012-08-29 | 株式会社東芝 | Semiconductor memory control device |
US8677027B2 (en) | 2011-06-01 | 2014-03-18 | International Business Machines Corporation | Fibre channel input/output data routing system and method |
US8583988B2 (en) | 2011-06-01 | 2013-11-12 | International Business Machines Corporation | Fibre channel input/output data routing system and method |
US8364854B2 (en) | 2011-06-01 | 2013-01-29 | International Business Machines Corporation | Fibre channel input/output data routing system and method |
US9021155B2 (en) | 2011-06-01 | 2015-04-28 | International Business Machines Corporation | Fibre channel input/output data routing including discarding of data transfer requests in response to error detection |
US8364853B2 (en) | 2011-06-01 | 2013-01-29 | International Business Machines Corporation | Fibre channel input/output data routing system and method |
US8738811B2 (en) | 2011-06-01 | 2014-05-27 | International Business Machines Corporation | Fibre channel input/output data routing system and method |
US8473641B2 (en) | 2011-06-30 | 2013-06-25 | International Business Machines Corporation | Facilitating transport mode input/output operations between a channel subsystem and input/output devices |
US8549185B2 (en) | 2011-06-30 | 2013-10-01 | International Business Machines Corporation | Facilitating transport mode input/output operations between a channel subsystem and input/output devices |
US8312176B1 (en) | 2011-06-30 | 2012-11-13 | International Business Machines Corporation | Facilitating transport mode input/output operations between a channel subsystem and input/output devices |
US8346978B1 (en) | 2011-06-30 | 2013-01-01 | International Business Machines Corporation | Facilitating transport mode input/output operations between a channel subsystem and input/output devices |
US8862856B2 (en) * | 2012-04-09 | 2014-10-14 | HGST Netherlands B.V. | Implementing remapping command with indirection update for indirected storage |
US8918542B2 (en) | 2013-03-15 | 2014-12-23 | International Business Machines Corporation | Facilitating transport mode data transfer between a channel subsystem and input/output devices |
US8990439B2 (en) | 2013-05-29 | 2015-03-24 | International Business Machines Corporation | Transport mode data transfer between a channel subsystem and input/output devices |
JP6179355B2 (en) * | 2013-10-31 | 2017-08-16 | 富士通株式会社 | Information processing apparatus, data transfer control method, and data transfer control program |
KR102280241B1 (en) * | 2019-07-03 | 2021-07-21 | 에스케이텔레콤 주식회사 | System for controlling memory-access, apparatus for controlling memory-access and method for controlling memory-access using the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8613071D0 (en) * | 1986-05-29 | 1986-07-02 | Univ Manchester | Data packet shortening |
FR2604280B1 (en) * | 1986-09-19 | 1988-11-10 | Picard Michel | METHOD FOR MANAGING FILES ON A NON-ERASABLE INFORMATION MEDIUM |
JP2606305B2 (en) * | 1988-07-21 | 1997-04-30 | 松下電器産業株式会社 | Data processing device |
GB2251323B (en) * | 1990-12-31 | 1994-10-12 | Intel Corp | Disk emulation for a non-volatile semiconductor memory |
US5404485A (en) * | 1993-03-08 | 1995-04-04 | M-Systems Flash Disk Pioneers Ltd. | Flash file system |
US5485595A (en) * | 1993-03-26 | 1996-01-16 | Cirrus Logic, Inc. | Flash memory mass storage architecture incorporating wear leveling technique without using cam cells |
-
1995
- 1995-09-27 GB GB9519669A patent/GB2291990A/en not_active Withdrawn
-
1996
- 1996-02-06 WO PCT/GB1996/000249 patent/WO1997012324A1/en not_active Application Discontinuation
- 1996-02-06 CN CN96197203A patent/CN1197520A/en active Pending
- 1996-02-06 JP JP9513195A patent/JP2000505215A/en active Pending
- 1996-02-06 DE DE69615385T patent/DE69615385D1/en not_active Expired - Lifetime
- 1996-02-06 EP EP96901894A patent/EP0852765B1/en not_active Expired - Lifetime
- 1996-02-06 KR KR1019980702181A patent/KR19990063714A/en not_active Application Discontinuation
- 1996-02-06 AT AT96901894T patent/ATE205946T1/en not_active IP Right Cessation
-
2006
- 2006-07-14 JP JP2006194909A patent/JP2006294061A/en not_active Withdrawn
-
2007
- 2007-07-23 JP JP2007191421A patent/JP2007280428A/en active Pending
Cited By (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7774576B2 (en) | 1995-07-31 | 2010-08-10 | Lexar Media, Inc. | Direct logical block addressing flash memory mass storage architecture |
US8078797B2 (en) | 1995-07-31 | 2011-12-13 | Micron Technology, Inc. | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
US8032694B2 (en) | 1995-07-31 | 2011-10-04 | Micron Technology, Inc. | Direct logical block addressing flash memory mass storage architecture |
US8397019B2 (en) | 1995-07-31 | 2013-03-12 | Micron Technology, Inc. | Memory for accessing multiple sectors of information substantially concurrently |
US7908426B2 (en) | 1995-07-31 | 2011-03-15 | Lexar Media, Inc. | Moving sectors within a block of information in a flash memory mass storage architecture |
US8554985B2 (en) | 1995-07-31 | 2013-10-08 | Micron Technology, Inc. | Memory block identified by group of logical block addresses, storage device with movable sectors, and methods |
US8171203B2 (en) | 1995-07-31 | 2012-05-01 | Micron Technology, Inc. | Faster write operations to nonvolatile memory using FSInfo sector manipulation |
US8793430B2 (en) | 1995-07-31 | 2014-07-29 | Micron Technology, Inc. | Electronic system having memory with a physical block having a sector storing data and indicating a move status of another sector of the physical block |
US9026721B2 (en) | 1995-07-31 | 2015-05-05 | Micron Technology, Inc. | Managing defective areas of memory |
US7734862B2 (en) | 2000-07-21 | 2010-06-08 | Lexar Media, Inc. | Block management for mass storage |
US8019932B2 (en) | 2000-07-21 | 2011-09-13 | Micron Technology, Inc. | Block management for mass storage |
US8250294B2 (en) | 2000-07-21 | 2012-08-21 | Micron Technology, Inc. | Block management for mass storage |
US9489301B2 (en) | 2001-09-28 | 2016-11-08 | Micron Technology, Inc. | Memory systems |
US9032134B2 (en) | 2001-09-28 | 2015-05-12 | Micron Technology, Inc. | Methods of operating a memory system that include outputting a data pattern from a sector allocation table to a host if a logical sector is indicated as being erased |
US7917709B2 (en) | 2001-09-28 | 2011-03-29 | Lexar Media, Inc. | Memory system for data storage and retrieval |
US7944762B2 (en) | 2001-09-28 | 2011-05-17 | Micron Technology, Inc. | Non-volatile memory control |
US7681057B2 (en) | 2001-09-28 | 2010-03-16 | Lexar Media, Inc. | Power management of non-volatile memory systems |
US8386695B2 (en) | 2001-09-28 | 2013-02-26 | Micron Technology, Inc. | Methods and apparatus for writing data to non-volatile memory |
US8208322B2 (en) | 2001-09-28 | 2012-06-26 | Micron Technology, Inc. | Non-volatile memory control |
US8135925B2 (en) | 2001-09-28 | 2012-03-13 | Micron Technology, Inc. | Methods of operating a memory system |
US7634624B2 (en) | 2001-09-28 | 2009-12-15 | Micron Technology, Inc. | Memory system for data storage and retrieval |
US8694722B2 (en) | 2001-09-28 | 2014-04-08 | Micron Technology, Inc. | Memory systems |
US9213606B2 (en) | 2002-02-22 | 2015-12-15 | Micron Technology, Inc. | Image rescue |
US8166488B2 (en) | 2002-02-22 | 2012-04-24 | Micron Technology, Inc. | Methods of directly accessing a mass storage data device |
US8090886B2 (en) | 2004-04-20 | 2012-01-03 | Micron Technology, Inc. | Direct secondary device interface by a host |
US7725628B1 (en) | 2004-04-20 | 2010-05-25 | Lexar Media, Inc. | Direct secondary device interface by a host |
US8316165B2 (en) | 2004-04-20 | 2012-11-20 | Micron Technology, Inc. | Direct secondary device interface by a host |
US7865659B2 (en) | 2004-04-30 | 2011-01-04 | Micron Technology, Inc. | Removable storage device |
US8612671B2 (en) | 2004-04-30 | 2013-12-17 | Micron Technology, Inc. | Removable devices |
US8151041B2 (en) | 2004-04-30 | 2012-04-03 | Micron Technology, Inc. | Removable storage device |
US10049207B2 (en) | 2004-04-30 | 2018-08-14 | Micron Technology, Inc. | Methods of operating storage systems including encrypting a key salt |
US9576154B2 (en) | 2004-04-30 | 2017-02-21 | Micron Technology, Inc. | Methods of operating storage systems including using a key to determine whether a password can be changed |
US8296545B2 (en) | 2004-08-27 | 2012-10-23 | Micron Technology, Inc. | Storage capacity status |
US7949822B2 (en) | 2004-08-27 | 2011-05-24 | Micron Technology, Inc. | Storage capacity status |
US7743290B2 (en) | 2004-08-27 | 2010-06-22 | Lexar Media, Inc. | Status of overall health of nonvolatile memory |
US8214583B2 (en) | 2005-02-16 | 2012-07-03 | Sandisk Technologies Inc. | Direct file data programming and deletion in flash memories |
US7984233B2 (en) | 2005-02-16 | 2011-07-19 | Sandisk Corporation | Direct data file storage implementation techniques in flash memories |
US7877539B2 (en) | 2005-02-16 | 2011-01-25 | Sandisk Corporation | Direct data file storage in flash memories |
US7949845B2 (en) | 2005-08-03 | 2011-05-24 | Sandisk Corporation | Indexing of file data in reprogrammable non-volatile memories that directly store data files |
WO2007019175A2 (en) * | 2005-08-03 | 2007-02-15 | Sandisk Corporation | Indexing of file data in reprogrammable non-volatile memories that directly store data files |
US7669003B2 (en) | 2005-08-03 | 2010-02-23 | Sandisk Corporation | Reprogrammable non-volatile memory systems with indexing of directly stored data files |
WO2007019175A3 (en) * | 2005-08-03 | 2007-09-07 | Sandisk Corp | Indexing of file data in reprogrammable non-volatile memories that directly store data files |
CN101233480B (en) * | 2005-08-03 | 2012-08-29 | 桑迪士克股份有限公司 | Reprogrammable non-volatile memory systems with indexing of directly stored data files |
US8055832B2 (en) | 2005-08-03 | 2011-11-08 | SanDisk Technologies, Inc. | Management of memory blocks that directly store data files |
US7814262B2 (en) | 2005-10-13 | 2010-10-12 | Sandisk Corporation | Memory system storing transformed units of data in fixed sized storage blocks |
US7747837B2 (en) | 2005-12-21 | 2010-06-29 | Sandisk Corporation | Method and system for accessing non-volatile storage devices |
US8209516B2 (en) | 2005-12-21 | 2012-06-26 | Sandisk Technologies Inc. | Method and system for dual mode access for storage devices |
Also Published As
Publication number | Publication date |
---|---|
JP2000505215A (en) | 2000-04-25 |
GB2291990A (en) | 1996-02-07 |
JP2006294061A (en) | 2006-10-26 |
CN1197520A (en) | 1998-10-28 |
ATE205946T1 (en) | 2001-10-15 |
DE69615385D1 (en) | 2001-10-25 |
JP2007280428A (en) | 2007-10-25 |
GB9519669D0 (en) | 1995-11-29 |
KR19990063714A (en) | 1999-07-26 |
WO1997012324A1 (en) | 1997-04-03 |
EP0852765A1 (en) | 1998-07-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0852765B1 (en) | Memory management | |
EP0688450B1 (en) | Flash file system | |
JP4695801B2 (en) | Method and apparatus for reducing block write operation time performed on non-volatile memory | |
US6327639B1 (en) | Method and apparatus for storing location identification information within non-volatile memory devices | |
US6115785A (en) | Direct logical block addressing flash memory mass storage architecture | |
US7191306B2 (en) | Flash memory, and flash memory access method and apparatus | |
US7814265B2 (en) | Single sector write operation in flash memory | |
USRE45222E1 (en) | Method of writing of writing to a flash memory including data blocks and log blocks, using a logical address having a block address portion and page identifying portion, a block address table and a page table | |
US20060168392A1 (en) | Flash memory file system | |
US5809558A (en) | Method and data storage system for storing data in blocks without file reallocation before erasure | |
KR100608602B1 (en) | Flash memory, Mapping controlling apparatus and method for the same | |
US20080270680A1 (en) | Controller for Non-Volatile Memories and Methods of Operating the Memory Controller | |
US20010023472A1 (en) | Data storage control method and apparatus for external storage device using a plurality of flash memories | |
KR19990063715A (en) | Memory system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19980403 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LI LU MC NL PT SE |
|
17Q | First examination report despatched |
Effective date: 19990614 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: MEMORY CORPORATION PLC |
|
GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LI LU MC NL PT SE |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20010919 Ref country code: LI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20010919 Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED. Effective date: 20010919 Ref country code: FR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20010919 Ref country code: CH Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20010919 Ref country code: BE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20010919 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20010919 |
|
REF | Corresponds to: |
Ref document number: 205946 Country of ref document: AT Date of ref document: 20011015 Kind code of ref document: T |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D |
|
REF | Corresponds to: |
Ref document number: 69615385 Country of ref document: DE Date of ref document: 20011025 |
|
RAP2 | Party data changed (patent owner data changed or rights of a patent transferred) |
Owner name: MEMQUEST, INC |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20011219 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20011219 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20011219 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20011220 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20011221 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: IF02 |
|
NLT2 | Nl: modifications (of names), taken from the european patent patent bulletin |
Owner name: MEMQUEST, INC |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20020206 Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20020206 |
|
NLV1 | Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act | ||
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20020326 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
EN | Fr: translation not filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20020901 |
|
26N | No opposition filed | ||
REG | Reference to a national code |
Ref country code: IE Ref legal event code: MM4A |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20130207 Year of fee payment: 18 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20130711 AND 20130717 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20140206 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20140206 |