EP0958674B1 - System for protecting cryptographic processing and memory resources for postal franking machines - Google Patents
System for protecting cryptographic processing and memory resources for postal franking machines Download PDFInfo
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- EP0958674B1 EP0958674B1 EP97947255A EP97947255A EP0958674B1 EP 0958674 B1 EP0958674 B1 EP 0958674B1 EP 97947255 A EP97947255 A EP 97947255A EP 97947255 A EP97947255 A EP 97947255A EP 0958674 B1 EP0958674 B1 EP 0958674B1
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- Prior art keywords
- security device
- postal
- postal security
- memory
- psd
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
- G07B17/00—Franking apparatus
- G07B17/00733—Cryptography or similar special procedures in a franking system
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
- G07B17/00—Franking apparatus
- G07B17/00016—Relations between apparatus, e.g. franking machine at customer or apparatus at post office, in a franking system
- G07B17/0008—Communication details outside or between apparatus
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
- G07B17/00—Franking apparatus
- G07B17/00016—Relations between apparatus, e.g. franking machine at customer or apparatus at post office, in a franking system
- G07B17/0008—Communication details outside or between apparatus
- G07B2017/00153—Communication details outside or between apparatus for sending information
- G07B2017/00177—Communication details outside or between apparatus for sending information from a portable device, e.g. a card or a PCMCIA
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
- G07B17/00—Franking apparatus
- G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
- G07B17/00193—Constructional details of apparatus in a franking system
- G07B2017/00258—Electronic hardware aspects, e.g. type of circuits used
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
- G07B17/00—Franking apparatus
- G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
- G07B17/00314—Communication within apparatus, personal computer [PC] system, or server, e.g. between printhead and central unit in a franking machine
- G07B2017/00322—Communication between components/modules/parts, e.g. printer, printhead, keyboard, conveyor or central unit
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
- G07B17/00—Franking apparatus
- G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
- G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
- G07B2017/00395—Memory organization
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
- G07B17/00—Franking apparatus
- G07B17/00733—Cryptography or similar special procedures in a franking system
- G07B2017/00959—Cryptographic modules, e.g. a PC encryption board
- G07B2017/00967—PSD [Postal Security Device] as defined by the USPS [US Postal Service]
Definitions
- This invention is directed to a system for protecting cryptographic processing and memory resources for postal franking machines.
- a postal customer may obtain postage from the postal authority in several ways, including the purchase of stamps and the use of a postage meter.
- a postage meter When a postage meter is used, there is a security concern since the meter is dispensing value, and without sufficient security, the value could be stolen from a meter by unscrupulous parties.
- Concerns include use of the meter to dispense postage for which the Postal Authority has not been compensated and use of the meter which was not authorized by the lawful operator of the meter.
- WO 93/06542 shows a system designed to protect the privacy or integrity of encrypted data in a tamper-proof housing of a plug-in card.
- the plug-in card is insertable into one of the expansion bus connections which are situated on the motherboard of a computer.
- the circuits and information carriers inside the tamper-proof housing can only be accessed as long as a number of electronic and program conditions are met.
- One of these conditions is, that protection means in the card are addressed at regular intervals, e.g. every 55 milliseconds. If this is not done, the card is blocked.
- the external programs and processes must operate in a manner perfectly synchronised with the internal operation of the plug-in card.
- an ASIC embodiment of a PSD is shown generally at 5 and includes zeroing circuitry 10, read-only-memory 12, random-access-memory 14, switching/control logic 16, a control cryptographic processor 18, non-volatile memory 20, crypto key retention 22, signature algorithm execution 24, random number generator 26, real time clock 28, interrupt control and porting 30, clock circuit 36, secure hash acceleration circuit 44, secure memory management unit 54, and host interface 44 all within a cryptographic boundary 34.
- the Random Number Generator 26 within this block provides a source for non-predictable random numbers typically required in systems employing cryptographic technology.
- the clock circuit 28 is an on-chip realtime clock for secure time keeping.
- a battery 32 for retaining memory contents in the absence of main power to the ASIC, and one or more crystals 37 which provide clock reference timing for the various subcircuits within the ASIC.
- a PSD contains working memory, storage memory, and firmware necessary to execute cryptographic algorithms, within its cryptographic boundary, including, but not limited to DES and RSA encryption, as well as digital signature creation and validation. Information that must be retained, as Master Key, Public Key, Private Key, and the like are secured within a non-volatile memory or battery backed up memory of the PSD.
- the battery and crystals are outside the cryptographic boundary of the ASIC in this embodiment, these components can be also integrated into the same package as the ASIC silicon die.
- the ASIC provides physical security to the data stored thereon as the circuits are inaccessible without destroying circuit operation.
- the secure data stored on an ASIC includes data encryption keys which cannot be extracted or modified without destroying PSD operation.
- the encryption engine 24 includes the capability of receiving data, processing the received data by performing encryption or decryption operations.
- the individual components of the ASIC may also be integrated within a PCMCIA Card, or preferably the custom integrated circuit (ASIC) is further integrated and embodied as a PCMCIA Card.
- the PCMCIA Card provides additional physical security through its housing for the processing unit for the storage and accounting of all funds, audit and secure support data required to produce and validate the addition and removal of postage value.
- one of the preferred embodiments encloses the ASIC or it components in a PCMCIA card. More generally, the invention contemplates enclosing the ASIC or its components in any package having a relatively small form factor. For example, any form factor that is more or less pocket-sized or that is more or less capable of being mailed in an envelope will be convenient.
- Such a package must necessarily have a communications port capable to interfacing with the postal franking device and a host, discussed below, preferably a parallel data and address bus such as is employed in a PCMCIA card.
- the port could be a serial bus such as a high-speed universal serial bus.
- an infrared (LED-phototransistor) link may be used.
- Said secure processing unit contains working memory, storage memory, and firmware necessary to execute cryptographic algorithms, within a cryptographic boundary, including but not limited to DES and RSA, as well as digital signature creation and validation. Information which must be retained, such as Master Keys, Public Keys, Private Keys, and the like are secured within a non-volatile memory or battery backed up memory.
- the security of the PSD implemented in a PCMCIA Card is a combination of data integrity, authentication, non-repudiation, and confidentiality.
- Data integrity is realized through the use of cryptographic checksums (one-way hashes) over the data. This function produces a small value that uniquely represents the data, such that if any single bit is altered the hash value changes significantly.
- the digital signature is obtained by performing a cryptographic operation on the resultant hash of the data. Authentication is realized by the fact that the receiving party can verify the digital signature on a transmission and be assured the transmission was originated by a trusted source and not other fraudulent parties.
- Non-repudiation is achieved by the fact that the originator of the message cannot deny the message contents as it is possible to generate the verifiable digital signature only with the originator's unique private key. Confidentiality is the use of encryption to protect the data from unauthorized disclosure.
- the PSD cannot operate as a standalone device and requires a host system to perform its functions.
- the PSD typically communicates directly with a host system to carry out its primary objective of indicia creation. Additionally, through the host system a user can access the PSD to review the ascending and descending register values, piece count, watchdog timeout date, and refill history logs; activate PSD diagnostics; and with proper supervisor authorization, set up and delete PINs for individual users.
- the PSD may also provide the user with certain operational error messages such as a low-postage warning and watchdog timeout condition through the host user interface.
- the host system may also maintain certain log files; these log files are required to be signed by the PSD with its private key. The host system will transfer the data to sign to the PSD and the PSD will return a digital signature and a certificate (which contains the public key which is unique to the PSD) that can be used later to verify the digital signature.
- the PSD supports input and output functions with appropriate interfacing devices compatible with the PSD physical, link layer, and application protocols. Due to the secure nature of the PSD, the device does not provide user accessible diagnostic features. Rather, the PSD has an extensive built-in self test suite which is run upon power up. The tests preferably include the normal code memory verification tests, RAM tests, verification of accounting register and data log integrity, and execution of sample cryptographic calculations with known results to verify full functionality of the PSD. Upon successful completion of these tests, the PSD will be enabled to dispense postage funds. If any of the tests fail, the PSD will output its current ascending register and descending values. The host may also obtain the same information via a device audit request message.
- the PSD Upon the receipt and verification of a Host infrastructure-generated device audit message, preferably the PSD will reset its internal watchdog timer to accommodate control and transaction date information.
- the PSD of the present invention need not be physically located with the postal franking device; it only need be in communication with the postal franking device.
- it may be located on the host or a computer network.
- the PSD including a PCMCIA Card
- the PSD may be connected to the franking device for operation and then disconnected and connected to the host for creation of the log files, etc., through a standard PCMCIA slot.
- a block diagram of the embodiment of the PCMCIA Card PSD of the present invention interfacing with a host controller including host controller 64, timeout circuit 66, memory arbiter 68, controller 70, and memory 72. It is envisioned that a number of forms of attack can be executed against the PCMCIA Card PSD wherein an attacker attempts to obtain additional data from the PSD, or otherwise compromise its integrity, by holding the bus for an excessive period of time.
- Timeout circuit 66 operates to limit the amount of time host controller 64 may have to complete a bus transaction, and will terminate a host-initiated bus transaction if the transaction exceeds a predetermined time limit.
- host 64 When host 64 wishes to access the PSD implemented in a PCMCIA Card, it waits until read signal 74 is asserted and then asserts select signal 76. This signal is input to timeout circuit 66, which initiates a predetermined timeout interval. Host controller 64 then initiates a read or write cycle by asserting the appropriate read and write signals and setting up the address and data busses accordingly.
- Timeout circuit 66 provides a separate select signal 78 to memory arbiter 68, which is effectively a dual port memory controller containing logic which defines conditions under which controller 70 and host controller 64 have access to memory 72.
- arbiter 68 asserts a hold signal 80 to controller 70, which tells controller 70 to temporarily hold off any further accesses of memory 72. Under these circumstances, controller 70 is typically idle unless it is performing an internal operation not requiring an external memory access.
- -Arbiter 68 allows read and write signals 82 and 84, as well as address and data busses 86 and 88, to pass onto memory 72.
- host controller 64 deasserts select signal 74 to timeout circuit 66 to indicate the normal end of the bus transfer.
- Timeout circuit 66 likewise deasserts select signal 78 to arbiter 68, which removes host controller's signal levels on the read, write, address and data busses (82, 84, and 86) to memory 72 and signals the controller 70 that it can access memory 72 by deasserting hold signal 80.
- timeout circuit 66 deasserts ready signal 74 to the host controller and select signal 78 to arbiter 68. This causes arbiter 68 to remove host controller's 64 read (84), write (82) address (88) and data (86) signals from memory 72. Hold signal 80 to controller 70 is released to controller 70 can again access memory 72.
- timeout circuit 66 could also signal controller 70 that the fault occurred by asserting interrupt signal 90 to that device.
- Logic in the controller 70's software could be invoked to categorize the problem as a random fault or an attempt to compromise the PSD. If controller 70 determines tampering has been attempted, the controller would refuse further host controller 64 accesses and force the customer to report the situation to the manufacturer, for example, remotely through a telephone call or other network communication or by returning the device.
- a preferred embodiment of the PSD implemented on a PCMCIA Card would restrict the area in memory 72 that host controller 64 can access. For example, access can be limited to no access, read-only, write-only, read-write, etc., and the address range in memory 72 can be restricted to a subset available to controller 70. In this manner, controller 70 can hide certain information, such as its most critical security parameters, from both observation or overwriting.
- Host interface 42 incorporates timeout circuit 66, PCMCIA memory arbiter 68, and PSD controller 70. Controller 70 corresponds to crypto processor 18 in figure 1. Timeout circuit 66 and arbiter 68 would thus preferably be incorporated into the PSD ASIC but may be added as discrete circuits on the PCMCIA card.
- the PSD of the present invention may be used with existing public/private key cryptographical techniques known in the art. See, for example, U.S. Patent Nos. 5,237,506, 5,606,507 and 5, 666, 284.
- the speed with which such encryption is performed may be increased by the use within the PSD of a Secure Memory Management Unit 96 (SMMU).
- SMMU Secure Memory Management Unit 96
- this is obtained from Atalla Corp., of San Jose, California, which is a Tandem Company, and VLSI Technology, of San Jose, California.
- Memory 98 external to the PSD contains encrypted code.
- SMMU 96 obtains the encrypted code 100 in portions to be processed by encryption engine 104, is such a manner that it acts as a feed for encryption engine 104.
- the encryption engine 104 utilizes the appropriate decryption key provided to it by the SMMU 96.
- This decryption key is securely stored in the PSD ASIC and is never output and so is never known to a potential attacker.
- the decrypted output from encryption engine 104 is then placed into RAM 106 (also 14 in Fig. 1).
- Fig. 3 shows the output of RAM 106 going to processor 108 (also 18 in Fig. 1).
- Fig. 3 depicts secure high speed instruction cache operation.
- the overall benefit of the SMMU is realized by the fact that a would-be attacker cannot substitute software instructions into the code to alter the intended functionality and that could give the attacker access to the master, private, or public keys held within the PSD ASIC.
Description
- This invention is directed to a system for protecting cryptographic processing and memory resources for postal franking machines.
- In countries throughout the world, a postal customer may obtain postage from the postal authority in several ways, including the purchase of stamps and the use of a postage meter. When a postage meter is used, there is a security concern since the meter is dispensing value, and without sufficient security, the value could be stolen from a meter by unscrupulous parties. Concerns include use of the meter to dispense postage for which the Postal Authority has not been compensated and use of the meter which was not authorized by the lawful operator of the meter.
- These security concerns have always been present, even when a postage meter was essentially a purely mechanical letterpress. As the postage meter evolved through the 20th century to an electronic configuration, letter-press printing was represented in a rotary drum movement impressing an image onto a mailpiece, as well as a flat-bed approach meshing a mailpiece on a platen assembly against a printing die to produce an image onto a mailpiece. The postage meter is now taking on a new role of digitally printing postage, thus no longer requiring letter-press printing.
- When a postage meter utilizes letter-press printing, security concerns are typically addressed, in part, by the physical attributes of the meter. Not only do the attributes of the meter (case material, etc.) provide protection against the unauthorized use of the meter, the attributes also provide a means to detect whether an attempt has been made to make unauthorized use of the meter evidenced by visible deliberate damage to the meter's case. With evolution of the "meter," greater security against fraudulent attacks on the meter is needed. With the increase in the availability of elaborate technologies and sophisticated hacking capabilities, Postal Authorities around the world, including the United States Postal Service, are concerned with the ability to defraud the Postal Authorities by falsifying postal indicium, particularly when such indicium is digitally printed.
- One approach which as been taken to increase the security of evolved meters is to employ cryptographics to the creation and application of the postal indicia. In order for this approach to be an effective security measure, however, there must be sufficient physical security for the cryptographic processing and memory to eliminate a successful fraudulent attack on the system. In order for this to be a commercially viable approach, cryptographic processing must be performed in a timely manner.
- WO 93/06542 shows a system designed to protect the privacy or integrity of encrypted data in a tamper-proof housing of a plug-in card. The plug-in card is insertable into one of the expansion bus connections which are situated on the motherboard of a computer. The circuits and information carriers inside the tamper-proof housing can only be accessed as long as a number of electronic and program conditions are met. One of these conditions is, that protection means in the card are addressed at regular intervals, e.g. every 55 milliseconds. If this is not done, the card is blocked. In order for the plug-in card to operate correctly, the external programs and processes must operate in a manner perfectly synchronised with the internal operation of the plug-in card.
- In "Applied Cryptography", Bruce Schneier, John Wiley & Sons, 2nd ed. 1996, section 24.13, the basic concepts and uses of smart cards are described.
- The invention is defined in the independent claims. Particular embodiments are specified in the dependent claims.
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- Fig. 1 is a block diagram showing the basic functional makeup of the PSD cryptographic processor in the present invention.
- Fig. 2 is a block diagram of the PCMCIA Card PSD of the present invention.
- Fig. 3 is a block diagram showing the PSD of the present invention operating in secure high speed instruction cache operation.
- Referring to Fig. 1, an ASIC embodiment of a PSD is shown generally at 5 and includes
zeroing circuitry 10, read-only-memory 12, random-access-memory 14, switching/control logic 16, a controlcryptographic processor 18,non-volatile memory 20,crypto key retention 22,signature algorithm execution 24,random number generator 26,real time clock 28, interrupt control andporting 30,clock circuit 36, securehash acceleration circuit 44, securememory management unit 54, andhost interface 44 all within a cryptographic boundary 34. TheRandom Number Generator 26 within this block provides a source for non-predictable random numbers typically required in systems employing cryptographic technology. Theclock circuit 28 is an on-chip realtime clock for secure time keeping. External to the ASIC PSD are abattery 32 for retaining memory contents in the absence of main power to the ASIC, and one ormore crystals 37 which provide clock reference timing for the various subcircuits within the ASIC. Such a PSD contains working memory, storage memory, and firmware necessary to execute cryptographic algorithms, within its cryptographic boundary, including, but not limited to DES and RSA encryption, as well as digital signature creation and validation. Information that must be retained, as Master Key, Public Key, Private Key, and the like are secured within a non-volatile memory or battery backed up memory of the PSD. Although the battery and crystals are outside the cryptographic boundary of the ASIC in this embodiment, these components can be also integrated into the same package as the ASIC silicon die. - The ASIC provides physical security to the data stored thereon as the circuits are inaccessible without destroying circuit operation. The secure data stored on an ASIC includes data encryption keys which cannot be extracted or modified without destroying PSD operation. The
encryption engine 24 includes the capability of receiving data, processing the received data by performing encryption or decryption operations. - The individual components of the ASIC may also be integrated within a PCMCIA Card, or preferably the custom integrated circuit (ASIC) is further integrated and embodied as a PCMCIA Card. The PCMCIA Card provides additional physical security through its housing for the processing unit for the storage and accounting of all funds, audit and secure support data required to produce and validate the addition and removal of postage value. As described above, one of the preferred embodiments encloses the ASIC or it components in a PCMCIA card. More generally, the invention contemplates enclosing the ASIC or its components in any package having a relatively small form factor. For example, any form factor that is more or less pocket-sized or that is more or less capable of being mailed in an envelope will be convenient. Such a package must necessarily have a communications port capable to interfacing with the postal franking device and a host, discussed below, preferably a parallel data and address bus such as is employed in a PCMCIA card. Alternatively the port could be a serial bus such as a high-speed universal serial bus. If the application does not require high speed, an infrared (LED-phototransistor) link may be used. Said secure processing unit contains working memory, storage memory, and firmware necessary to execute cryptographic algorithms, within a cryptographic boundary, including but not limited to DES and RSA, as well as digital signature creation and validation. Information which must be retained, such as Master Keys, Public Keys, Private Keys, and the like are secured within a non-volatile memory or battery backed up memory.
- The security of the PSD implemented in a PCMCIA Card is a combination of data integrity, authentication, non-repudiation, and confidentiality. Data integrity is realized through the use of cryptographic checksums (one-way hashes) over the data. This function produces a small value that uniquely represents the data, such that if any single bit is altered the hash value changes significantly. The digital signature is obtained by performing a cryptographic operation on the resultant hash of the data. Authentication is realized by the fact that the receiving party can verify the digital signature on a transmission and be assured the transmission was originated by a trusted source and not other fraudulent parties. Non-repudiation is achieved by the fact that the originator of the message cannot deny the message contents as it is possible to generate the verifiable digital signature only with the originator's unique private key. Confidentiality is the use of encryption to protect the data from unauthorized disclosure.
- To ensure operational security, the PSD cannot operate as a standalone device and requires a host system to perform its functions. The PSD typically communicates directly with a host system to carry out its primary objective of indicia creation. Additionally, through the host system a user can access the PSD to review the ascending and descending register values, piece count, watchdog timeout date, and refill history logs; activate PSD diagnostics; and with proper supervisor authorization, set up and delete PINs for individual users. The PSD may also provide the user with certain operational error messages such as a low-postage warning and watchdog timeout condition through the host user interface. The host system may also maintain certain log files; these log files are required to be signed by the PSD with its private key. The host system will transfer the data to sign to the PSD and the PSD will return a digital signature and a certificate (which contains the public key which is unique to the PSD) that can be used later to verify the digital signature.
- The PSD supports input and output functions with appropriate interfacing devices compatible with the PSD physical, link layer, and application protocols. Due to the secure nature of the PSD, the device does not provide user accessible diagnostic features. Rather, the PSD has an extensive built-in self test suite which is run upon power up. The tests preferably include the normal code memory verification tests, RAM tests, verification of accounting register and data log integrity, and execution of sample cryptographic calculations with known results to verify full functionality of the PSD. Upon successful completion of these tests, the PSD will be enabled to dispense postage funds. If any of the tests fail, the PSD will output its current ascending register and descending values. The host may also obtain the same information via a device audit request message. This will provide the host with additional information which may be forwarded to a Host infrastructure for the purposes of auditing the PSD. Upon the receipt and verification of a Host infrastructure-generated device audit message, preferably the PSD will reset its internal watchdog timer to accommodate control and transaction date information.
- It is understood by one skilled in the art that the PSD of the present invention need not be physically located with the postal franking device; it only need be in communication with the postal franking device. For example, it may be located on the host or a computer network. In the instance of the PSD including a PCMCIA Card, the PSD may be connected to the franking device for operation and then disconnected and connected to the host for creation of the log files, etc., through a standard PCMCIA slot.
- Referring now to Fig. 2, a block diagram of the embodiment of the PCMCIA Card PSD of the present invention interfacing with a host controller is shown, including
host controller 64,timeout circuit 66,memory arbiter 68,controller 70, andmemory 72. It is envisioned that a number of forms of attack can be executed against the PCMCIA Card PSD wherein an attacker attempts to obtain additional data from the PSD, or otherwise compromise its integrity, by holding the bus for an excessive period of time.Timeout circuit 66 operates to limit the amount oftime host controller 64 may have to complete a bus transaction, and will terminate a host-initiated bus transaction if the transaction exceeds a predetermined time limit. - When
host 64 wishes to access the PSD implemented in a PCMCIA Card, it waits until readsignal 74 is asserted and then assertsselect signal 76. This signal is input totimeout circuit 66, which initiates a predetermined timeout interval.Host controller 64 then initiates a read or write cycle by asserting the appropriate read and write signals and setting up the address and data busses accordingly. -
Timeout circuit 66 provides a separateselect signal 78 tomemory arbiter 68, which is effectively a dual port memory controller containing logic which defines conditions under whichcontroller 70 andhost controller 64 have access tomemory 72. Whenhost controller 64 has access tomemory 72,arbiter 68 asserts ahold signal 80 tocontroller 70, which tellscontroller 70 to temporarily hold off any further accesses ofmemory 72. Under these circumstances,controller 70 is typically idle unless it is performing an internal operation not requiring an external memory access. - -
Arbiter 68 allows read and writesignals memory 72. Following a successful bus transaction,host controller 64 deasserts selectsignal 74 totimeout circuit 66 to indicate the normal end of the bus transfer.Timeout circuit 66 likewise deassertsselect signal 78 toarbiter 68, which removes host controller's signal levels on the read, write, address and data busses (82, 84, and 86) tomemory 72 and signals thecontroller 70 that it can accessmemory 72 bydeasserting hold signal 80. - If
host controller 64 takes too long to complete the bus access,timeout circuit 66 deassertsready signal 74 to the host controller andselect signal 78 toarbiter 68. This causesarbiter 68 to remove host controller's 64 read (84), write (82) address (88) and data (86) signals frommemory 72. Holdsignal 80 tocontroller 70 is released tocontroller 70 can again accessmemory 72. Alternatively,timeout circuit 66 could also signalcontroller 70 that the fault occurred by asserting interruptsignal 90 to that device. Logic in thecontroller 70's software could be invoked to categorize the problem as a random fault or an attempt to compromise the PSD. Ifcontroller 70 determines tampering has been attempted, the controller would refusefurther host controller 64 accesses and force the customer to report the situation to the manufacturer, for example, remotely through a telephone call or other network communication or by returning the device. - A preferred embodiment of the PSD implemented on a PCMCIA Card would restrict the area in
memory 72 thathost controller 64 can access. For example, access can be limited to no access, read-only, write-only, read-write, etc., and the address range inmemory 72 can be restricted to a subset available tocontroller 70. In this manner,controller 70 can hide certain information, such as its most critical security parameters, from both observation or overwriting. -
Host interface 42 incorporatestimeout circuit 66,PCMCIA memory arbiter 68, andPSD controller 70.Controller 70 corresponds tocrypto processor 18 in figure 1.Timeout circuit 66 andarbiter 68 would thus preferably be incorporated into the PSD ASIC but may be added as discrete circuits on the PCMCIA card. - The PSD of the present invention may be used with existing public/private key cryptographical techniques known in the art. See, for example, U.S. Patent Nos. 5,237,506, 5,606,507 and 5, 666, 284. The speed with which such encryption is performed, however, may be increased by the use within the PSD of a Secure Memory Management Unit 96 (SMMU). Preferably, this is obtained from Atalla Corp., of San Jose, California, which is a Tandem Company, and VLSI Technology, of San Jose, California.
- As shown in Fig. 3,
Memory 98 external to the PSD contains encrypted code.SMMU 96 obtains theencrypted code 100 in portions to be processed byencryption engine 104, is such a manner that it acts as a feed forencryption engine 104. Theencryption engine 104 utilizes the appropriate decryption key provided to it by theSMMU 96. This decryption key is securely stored in the PSD ASIC and is never output and so is never known to a potential attacker. The decrypted output fromencryption engine 104 is then placed into RAM 106 (also 14 in Fig. 1). Fig. 3 shows the output ofRAM 106 going to processor 108 (also 18 in Fig. 1). Thus, Fig. 3 depicts secure high speed instruction cache operation. The overall benefit of the SMMU is realized by the fact that a would-be attacker cannot substitute software instructions into the code to alter the intended functionality and that could give the attacker access to the master, private, or public keys held within the PSD ASIC. - While there have been described what are believed to be the preferred embodiments of the invention, those skilled in the art will recognize that other and further modifications may be made thereto without departing from the invention.
Claims (8)
- A postal security device in the form of an application specific integrated circuit (5) for protecting cryptographic processing and memory resources (72) for postal franking machines, with the application specific integrated circuit (5) comprising:a) a communications bus (82, 84, 86) for communicating between the cryptographic processing and memory resources (72) and a host controller (64); characterized in that the application specific integrated circuit (5) further comprisesb) a timeout circuit (66) disposed for monitoring the amount of time the host controller (64) is taking to complete a bus transaction;c) the timeout circuit (66) further disposed for comparing the monitored amount of time to a predetermined reference time;d) means for refusing to permit completion of the bus transaction if the monitored amount of time exceeds the predetermined reference time.
- The postal security device of claim 1, comprising means for executing a suite of self-tests to verify full functionality of the postal security device.
- The postal security device of one of the preceding claims, wherein the application specific integrated circuit (5) is embodied within a PCMCIA card.
- The postal security device of one of the preceding claims, comprising a secure data memory which cannot be extracted or modified without destroying operation of the postal security device, and a further data memory that can be read and/or modified by a user.
- The postal security device of one of the preceding claims, comprising a signature algorithm execution means (24) for generating a check sum representation of generated data to provide a unique digital signature that may be verified.
- A method for protecting cryptographic processing and memory resources (72) for postal franking machines disposed within a postal security device in the form of an application specific integrated circuit (5) Card, characterized in that the method comprises the steps of:a) a timeout circuit (66) monitoring the amount of time a host controller is taking to complete a bus transaction over a communications bus (82, 84, 86) for communicating between the cryptographic processing and memory resources (72) and a host controller (64);b) a timeout circuit (66) comparing the monitored amount of time to a predetermined reference time;c) refusing to permit completion of the bus transaction if the monitored amount of time exceeds the predetermined reference time.
- The method of claim 6, comprising executing a suite of self-tests to verify full functionality of the postal security device.
- The method of claim 6 or claim 7, comprising generating, by a signature algorithm execution means (24), a check sum representation of generated data to provide a unique digital signature that may be verified.
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3053796P | 1996-11-07 | 1996-11-07 | |
US30537P | 1996-11-07 | ||
US5004397P | 1997-06-18 | 1997-06-18 | |
US50043P | 1997-06-18 | ||
US5410597P | 1997-07-29 | 1997-07-29 | |
US54105P | 1997-07-29 | ||
PCT/US1997/015856 WO1998020461A2 (en) | 1996-11-07 | 1997-11-07 | System for protecting cryptographic processing and memory resources for postal franking machines |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0958674A2 EP0958674A2 (en) | 1999-11-24 |
EP0958674A4 EP0958674A4 (en) | 2004-07-07 |
EP0958674B1 true EP0958674B1 (en) | 2006-06-28 |
Family
ID=27363669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP97947255A Expired - Lifetime EP0958674B1 (en) | 1996-11-07 | 1997-11-07 | System for protecting cryptographic processing and memory resources for postal franking machines |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0958674B1 (en) |
CA (1) | CA2271097A1 (en) |
DE (1) | DE69736246T2 (en) |
WO (1) | WO1998020461A2 (en) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5822738A (en) | 1995-11-22 | 1998-10-13 | F.M.E. Corporation | Method and apparatus for a modular postage accounting system |
US6424954B1 (en) * | 1998-02-17 | 2002-07-23 | Neopost Inc. | Postage metering system |
US6269350B1 (en) | 1998-07-24 | 2001-07-31 | Neopost Inc. | Method and apparatus for placing automated service calls for postage meter and base |
DE19812903A1 (en) * | 1998-03-18 | 1999-09-23 | Francotyp Postalia Gmbh | Franking device and a method for generating valid data for franking imprints |
US7028014B1 (en) * | 1998-03-18 | 2006-04-11 | Ascom Hasler Mailing Systems | Tamper resistant postal security device with long battery life |
US6591251B1 (en) | 1998-07-22 | 2003-07-08 | Neopost Inc. | Method, apparatus, and code for maintaining secure postage data |
US6523013B2 (en) | 1998-07-24 | 2003-02-18 | Neopost, Inc. | Method and apparatus for performing automated fraud reporting |
US6594760B1 (en) | 1998-12-21 | 2003-07-15 | Pitney Bowes Inc. | System and method for suppressing conducted emissions by a cryptographic device |
US6381589B1 (en) | 1999-02-16 | 2002-04-30 | Neopost Inc. | Method and apparatus for performing secure processing of postal data |
EP1035518B1 (en) * | 1999-03-12 | 2008-06-25 | Francotyp-Postalia GmbH | Arrangement for the protection of a security module |
DE19912781A1 (en) | 1999-03-12 | 2000-11-23 | Francotyp Postalia Gmbh | Method for protecting a security module and arrangement for carrying out the method |
DE19912780A1 (en) | 1999-03-12 | 2000-09-14 | Francotyp Postalia Gmbh | Arrangement for a security module |
DE29905219U1 (en) | 1999-03-12 | 1999-06-17 | Francotyp Postalia Gmbh | Security module with status signaling |
AU1475901A (en) | 1999-11-10 | 2001-06-06 | Neopost, Inc. | System and method of printing labels |
US6766455B1 (en) | 1999-12-09 | 2004-07-20 | Pitney Bowes Inc. | System and method for preventing differential power analysis attacks (DPA) on a cryptographic device |
GB2363868B (en) * | 2000-06-19 | 2004-12-01 | Pitney Bowes Ltd | Secure data storage on open systems |
US7085725B1 (en) | 2000-07-07 | 2006-08-01 | Neopost Inc. | Methods of distributing postage label sheets with security features |
DE10056989A1 (en) * | 2000-11-17 | 2002-05-23 | Secware Technologies Ag | Application-specific integrated circuit for encoding and decoding data streams has PCMCIA interface connectable to card storing key information |
EP1386249A4 (en) * | 2001-02-23 | 2008-12-31 | Ascom Hasler Mailing Sys Inc | Removable data carrier |
US6865637B1 (en) * | 2001-06-26 | 2005-03-08 | Alcatel | Memory card and system for updating distributed memory |
DE10137505B4 (en) * | 2001-07-16 | 2005-06-23 | Francotyp-Postalia Ag & Co. Kg | Arrangement and method for changing the functionality of a security module |
US7069253B2 (en) | 2002-09-26 | 2006-06-27 | Neopost Inc. | Techniques for tracking mailpieces and accounting for postage payment |
US20040103067A1 (en) * | 2002-11-26 | 2004-05-27 | Mattern James M. | Metering funds debit and credit for multi use |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4743747A (en) * | 1985-08-06 | 1988-05-10 | Pitney Bowes Inc. | Postage and mailing information applying system |
US4814591A (en) * | 1987-04-13 | 1989-03-21 | Kabushiki Kaisha Toshiba | Portable medium |
GB8804689D0 (en) * | 1988-02-29 | 1988-03-30 | Alcatel Business Systems | Franking system |
JPH04213242A (en) * | 1990-12-07 | 1992-08-04 | Hitachi Ltd | Limited multiple address communication system |
CA2071577A1 (en) * | 1991-06-21 | 1992-12-22 | Gerald L. Dawson | Electronic combination lock with high security features |
NL9101594A (en) * | 1991-09-20 | 1993-04-16 | Tres Automatisering B V | COMPUTER SYSTEM WITH SECURITY. |
JP2731310B2 (en) * | 1992-01-07 | 1998-03-25 | 株式会社テック | Product sales registration device |
US5389738A (en) * | 1992-05-04 | 1995-02-14 | Motorola, Inc. | Tamperproof arrangement for an integrated circuit device |
FR2706655B1 (en) * | 1993-06-17 | 1995-08-25 | Gemplus Card Int | Method of controlling a printer to obtain postage. |
IL110891A (en) * | 1993-09-14 | 1999-03-12 | Spyrus | System and method for data access control |
US5448641A (en) * | 1993-10-08 | 1995-09-05 | Pitney Bowes Inc. | Postal rating system with verifiable integrity |
US5535279A (en) * | 1994-12-15 | 1996-07-09 | Pitney Bowes Inc. | Postage accounting system including means for transmitting a bit-mapped image of variable information for driving an external printer |
US5602921A (en) * | 1994-12-15 | 1997-02-11 | Pitney Bowes Inc. | Postage accounting system including means for transmitting ASCII encoded variable information for driving an external printer |
US5682427A (en) * | 1994-12-15 | 1997-10-28 | Pitney Bowes Inc. | Postage metering system with dedicated and non-dedicated postage printing means |
US5590198A (en) * | 1995-12-19 | 1996-12-31 | Pitney Bowes Inc. | Open metering system with super password vault access |
-
1997
- 1997-11-07 WO PCT/US1997/015856 patent/WO1998020461A2/en active Search and Examination
- 1997-11-07 CA CA002271097A patent/CA2271097A1/en not_active Abandoned
- 1997-11-07 DE DE69736246T patent/DE69736246T2/en not_active Expired - Lifetime
- 1997-11-07 EP EP97947255A patent/EP0958674B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CA2271097A1 (en) | 1998-05-14 |
EP0958674A2 (en) | 1999-11-24 |
DE69736246T2 (en) | 2007-05-16 |
EP0958674A4 (en) | 2004-07-07 |
WO1998020461A2 (en) | 1998-05-14 |
DE69736246D1 (en) | 2006-08-10 |
WO1998020461A3 (en) | 1998-10-08 |
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