EP1026600A3 - Method and apparatus for interfacing with RAM - Google Patents

Method and apparatus for interfacing with RAM Download PDF

Info

Publication number
EP1026600A3
EP1026600A3 EP00201754A EP00201754A EP1026600A3 EP 1026600 A3 EP1026600 A3 EP 1026600A3 EP 00201754 A EP00201754 A EP 00201754A EP 00201754 A EP00201754 A EP 00201754A EP 1026600 A3 EP1026600 A3 EP 1026600A3
Authority
EP
European Patent Office
Prior art keywords
clock rate
sender
receiver
ram
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP00201754A
Other languages
German (de)
French (fr)
Other versions
EP1026600B1 (en
EP1026600A2 (en
Inventor
Anthony Mark Jones
William Philip Robbins
Donald William Walker Patterson
Adrian Philip Wise
Helen Rosemary Finch
Martin William Sotheran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Discovision Associates
Original Assignee
Discovision Associates
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9405914A external-priority patent/GB9405914D0/en
Priority claimed from GB9415387A external-priority patent/GB9415387D0/en
Priority claimed from GB9415365A external-priority patent/GB9415365D0/en
Priority claimed from GB9415391A external-priority patent/GB9415391D0/en
Priority claimed from GB9415413A external-priority patent/GB9415413D0/en
Application filed by Discovision Associates filed Critical Discovision Associates
Publication of EP1026600A2 publication Critical patent/EP1026600A2/en
Publication of EP1026600A3 publication Critical patent/EP1026600A3/en
Application granted granted Critical
Publication of EP1026600B1 publication Critical patent/EP1026600B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

An apparatus for connecting a bus to a RAM comprising :a single address generator providing complete addresses that is clocked at a first clock rate;a RAM interface, comprising :a plurality of swing buffers connected to a bus for receiving therefrom a plurality of data words from a source at a second clock rate ;a control coupled to said swing buffersa two-wire link connecting said control with said address generator wherein a request/acknowledge protocol is implemented therebetween via said link, wherein said two-wire link comprises a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready; wherein the interface is clocked at a third clock rate that is asynchronous with said first clock rate and said second clock rate, and data is transferred between a selected swing buffer and a RAM in response to a first signal that is generated by said control when said control receives an address from the address generator and said control receives a second signal from said selected swing buffer via said communication link
EP00201754A 1994-03-24 1995-02-28 Method and apparatus for interfacing with RAM Expired - Lifetime EP1026600B1 (en)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
GB9405914A GB9405914D0 (en) 1994-03-24 1994-03-24 Video decompression
GB9405914 1994-03-24
GB9415387 1994-07-29
GB9415387A GB9415387D0 (en) 1994-07-29 1994-07-29 Method and apparatus for addressing memory
GB9415365 1994-07-29
GB9415365A GB9415365D0 (en) 1994-07-29 1994-07-29 Method for accessing ram
GB9415391 1994-07-29
GB9415413 1994-07-29
GB9415391A GB9415391D0 (en) 1994-07-29 1994-07-29 Method for accessing banks of dram
GB9415413A GB9415413D0 (en) 1994-07-29 1994-07-29 Method and apparatus for video decompression
EP95301272A EP0674266A3 (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
EP95301272A Division EP0674266A3 (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram

Publications (3)

Publication Number Publication Date
EP1026600A2 EP1026600A2 (en) 2000-08-09
EP1026600A3 true EP1026600A3 (en) 2000-11-08
EP1026600B1 EP1026600B1 (en) 2004-10-06

Family

ID=27517237

Family Applications (6)

Application Number Title Priority Date Filing Date
EP95301272A Withdrawn EP0674266A3 (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram
EP98202092A Withdrawn EP0895167A3 (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram
EP98202091A Ceased EP0895166A3 (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram
EP98202090A Withdrawn EP0895422A3 (en) 1994-03-24 1995-02-28 Image formatter for processing encoded video data
EP00201754A Expired - Lifetime EP1026600B1 (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with RAM
EP98202093A Ceased EP0895161A3 (en) 1994-03-24 1995-02-28 Method for addressing variable width memory data

Family Applications Before (4)

Application Number Title Priority Date Filing Date
EP95301272A Withdrawn EP0674266A3 (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram
EP98202092A Withdrawn EP0895167A3 (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram
EP98202091A Ceased EP0895166A3 (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram
EP98202090A Withdrawn EP0895422A3 (en) 1994-03-24 1995-02-28 Image formatter for processing encoded video data

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP98202093A Ceased EP0895161A3 (en) 1994-03-24 1995-02-28 Method for addressing variable width memory data

Country Status (3)

Country Link
EP (6) EP0674266A3 (en)
AT (1) ATE278988T1 (en)
DE (1) DE69533630T2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6336180B1 (en) 1997-04-30 2002-01-01 Canon Kabushiki Kaisha Method, apparatus and system for managing virtual memory with virtual-physical mapping
US6217234B1 (en) * 1994-07-29 2001-04-17 Discovision Associates Apparatus and method for processing data with an arithmetic unit
EP0793390A3 (en) * 1996-02-28 1999-11-03 Koninklijke Philips Electronics N.V. MPEG signals decoding device
AUPO648397A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Improvements in multiprocessor architecture operation
US6311258B1 (en) 1997-04-03 2001-10-30 Canon Kabushiki Kaisha Data buffer apparatus and method for storing graphical data using data encoders and decoders
AUPO647997A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
US6507898B1 (en) 1997-04-30 2003-01-14 Canon Kabushiki Kaisha Reconfigurable data cache controller
US6707463B1 (en) 1997-04-30 2004-03-16 Canon Kabushiki Kaisha Data normalization technique
US6674536B2 (en) 1997-04-30 2004-01-06 Canon Kabushiki Kaisha Multi-instruction stream processor
FR2766937B1 (en) * 1997-07-31 2001-04-27 Sqware T PROTOCOL AND SYSTEM FOR BUS LINKING BETWEEN ELEMENTS OF A MICROCONTROLLER
JP2000010863A (en) * 1998-06-24 2000-01-14 Sony Computer Entertainment Inc Device and method for information processing, and provision medium
US6851052B1 (en) * 1998-12-10 2005-02-01 Telcordia Technologies, Inc. Method and device for generating approximate message authentication codes
US7212440B2 (en) 2004-12-30 2007-05-01 Sandisk Corporation On-chip data grouping and alignment

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0468480A2 (en) * 1990-07-25 1992-01-29 Oki Electric Industry Co., Ltd. Synchronous burst-access memory and word-line driving circuit therefor
US5138448A (en) * 1989-08-22 1992-08-11 Laboratoire European De Researches Electronique Avancees Device for conversion of frame frequency and number of lines for a high-definition television receiver
US5231605A (en) * 1991-01-31 1993-07-27 Micron Technology, Inc. DRAM compressed data test mode with expected data
US5265212A (en) * 1992-04-01 1993-11-23 Digital Equipment Corporation Sharing of bus access among multiple state machines with minimal wait time and prioritization of like cycle types

Family Cites Families (11)

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Publication number Priority date Publication date Assignee Title
EP0576749B1 (en) * 1992-06-30 1999-06-02 Discovision Associates Data pipeline system
JPS53114617A (en) * 1977-03-17 1978-10-06 Toshiba Corp Memory unit for picture processing
US4135242A (en) * 1977-11-07 1979-01-16 Ncr Corporation Method and processor having bit-addressable scratch pad memory
GB2039106B (en) * 1979-01-02 1983-03-23 Honeywell Inf Systems Number format conversion in computer
US4564915A (en) * 1980-04-11 1986-01-14 Ampex Corporation YIQ Computer graphics system
DE3138897A1 (en) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München CIRCUIT FOR THE PROCESSING OF STORAGE OPERANDS FOR DECIMAL AND LOGICAL COMMANDS
US4800431A (en) * 1984-03-19 1989-01-24 Schlumberger Systems And Services, Inc. Video stream processing frame buffer controller
JPS6180940A (en) * 1984-09-28 1986-04-24 Hitachi Ltd Data transmission system
JP2520404B2 (en) * 1986-11-10 1996-07-31 日本電気株式会社 Compression decoding device
DE3782500T2 (en) * 1987-12-23 1993-05-06 Ibm SHARED STORAGE INTERFACE FOR DATA PROCESSING SYSTEM.
US5289577A (en) * 1992-06-04 1994-02-22 International Business Machines Incorporated Process-pipeline architecture for image/video processing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5138448A (en) * 1989-08-22 1992-08-11 Laboratoire European De Researches Electronique Avancees Device for conversion of frame frequency and number of lines for a high-definition television receiver
EP0468480A2 (en) * 1990-07-25 1992-01-29 Oki Electric Industry Co., Ltd. Synchronous burst-access memory and word-line driving circuit therefor
US5231605A (en) * 1991-01-31 1993-07-27 Micron Technology, Inc. DRAM compressed data test mode with expected data
US5265212A (en) * 1992-04-01 1993-11-23 Digital Equipment Corporation Sharing of bus access among multiple state machines with minimal wait time and prioritization of like cycle types

Also Published As

Publication number Publication date
EP0895422A2 (en) 1999-02-03
EP0895167A2 (en) 1999-02-03
EP0895161A3 (en) 1999-02-10
EP0895161A2 (en) 1999-02-03
ATE278988T1 (en) 2004-10-15
EP0674266A3 (en) 1997-12-03
EP0895422A3 (en) 1999-03-10
DE69533630T2 (en) 2005-02-24
DE69533630D1 (en) 2004-11-11
EP1026600B1 (en) 2004-10-06
EP1026600A2 (en) 2000-08-09
EP0674266A2 (en) 1995-09-27
EP0895167A3 (en) 1999-03-10
EP0895166A3 (en) 1999-03-10
EP0895166A2 (en) 1999-02-03

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