EP1148544A1 - Method for thinning a substrate - Google Patents

Abstract

The invention relates to a method for rapidly thinning a semiconductor substrate with a high degree of precision. Said method can be carried out independently of both the tolerance of an assembly support (8) and of an adhesive joint (7) that is used to fix the substrate to the assembly support (8). To this end, a first layer (2), doped with a p-dopant is formed in the substrate (1). Then the substrate (1) is first pared down by grinding its rear surface (9) and subsequently thinned by a wet-chemical etching process. The first doped layer (2) acts as an etch stop.

Description

The present invention relates to a method for thinning of a semiconductor substrate.

In the three-dimensional integration of integrated circuits becomes a thinned semiconductor substrate on a second Semiconductor substrate arranged and with this mechanically and electrically connected. This procedure is for example in "Semiconductor Wafer Bonding: Science and Technology, Q.Y. Tong, Wiley-Interscience Publication "on pages 146 to 153. In this process is the thinning process of the semiconductor substrate one of the most technologically sophisticated and most expensive process steps.

For the three-dimensional integration, two completely processed wafers are usually initially provided. The first wafer serves as a carrier, the second wafer is thinned using the following method and arranged on the first wafer. For thinning, the second wafer, which is the side with the electrical circuits, is first provided with an adhesive layer and connected to an assembly carrier. The back of the second wafer is then thinned, usually using up to three processes sequentially. A grinding process is usually used first, followed by a chemical etching process and a chemical mechanical polishing (CMP). The aim of this method is to obtain the semiconductor substrate in the range of 10 μ m, a residual thickness, must be set in consideration of the following process steps especially in the planarity and compliance with the exact target thickness value.

The three mentioned thinning processes include due to their different ways of working each different Disadvantages, so the best result by a combination the known method is achieved. Grinding is that fastest procedure and is therefore used as the first step to remove most of the semiconductor layer. However, the substrate surface is damaged by grinding that in a subsequent chemical Etching step are removed. The chemical etching step has however, the disadvantage that the etched surface is not is planar, but a ripple in the range of +/- 3% of the has layer thickness removed by the etching step. Out for this reason, in a third step, a chemical mechanical Polishing performed CMP, reducing the ripple the surface is polished. The CMP step is slow and expensive and is therefore only used for post-treatment of the Surface used.

Mechanical is the process with the greatest stock removal Grinding used. The grinding abrasion arises through the Adjustment of the system plane-parallel to the mounting bracket, to which the second substrate wafer is attached. Here is too take into account that a not parallel to the mounting bracket attached wafer is ground at an angle. Because the substrate wafer for example attached to the mounting bracket with adhesive is located between the substrate and the mounting bracket an adhesive joint. The adhesive joint has a different Layer thickness as e.g. with a wedge shape is formed, the substrate is not plane-parallel to aligned with the mounting bracket. In the subsequent grinding process the substrate wafer is therefore not plane-parallel sanded its surface on which the electrical Circuits are arranged. For example, this problem can occur can be solved by making the adhesive joint very thin becomes. However, this has the disadvantage that none are filled Glue can be used when peeling off later of the substrate from the mounting carrier would be advantageous, because e.g. Solvent the adhesive from thick adhesive joints more easily can detach. The adjustment accuracy also works of the mounting bracket compared to the grinding plate in accuracy of the grinding process.

On the other hand, the grinding process cannot be dispensed with, since etching processes are too imprecise and CMP is too slow.

For example, a method is known in which a buried oxide layer is used as an etch stop. Wafers which have such a buried oxide layer are known as so-called SOI wafers (silicon on insulator). These wafers are significantly more expensive than standard wafers and require a different process control in the production of circuits in the silicon substrate compared to conventional silicon wafers. This makes it necessary to adapt the process technology. A particular disadvantage of SOI wafers is that they have high internal mechanical stresses. If SOI wafers are thinned to a few 10 µm and below, this leads to the silicon layer being peeled off the mounting carrier and the silicon layer being rolled up.

It is the object of the invention to specify a method with a semiconductor substrate can be thinned very precisely and quickly can.

• Bereitstellen eines Substrats mit einer Vorderseite und einer Rückseite;
• Bilden einer Nutzschicht auf der Vorderseite des Substrats;
• Bilden einer ersten dotierten Schicht in dem Substrat;
• naßchemisches Ätzen des Substrates, wobei das Substrat von der Rückseite gedünnt wird und die erste dotierte Schicht als Ätzstopp verwendet wird.

According to the invention, the object is achieved by a method for thinning a substrate with the steps:

• Providing a substrate having a front and a back;
• Forming a wear layer on the front of the substrate;
• Forming a first doped layer in the substrate;
• wet chemical etching of the substrate, the substrate being thinned from the back and the first doped layer being used as an etching stop.

By using a doped layer according to the invention is advantageously in the substrate as an etch stop self-aligned process step used to thin the substrate. The etching of the back of the wafer stops in this case self-aligned on the doped layer, so that even at oblique grinding of the back of the wafer a plane parallel Alignment from the front with the circuits to the Back of the thinned wafer is reached. It is e.g. out "Q.Y. Tong, Semiconductor Wafer Bonding: Science and Technology," Pages 146 to 153, known that p-doped silicon for wet etching solutions such as KOH solution (potassium hydroxide) or EDT solution (ethylenediamine pyrocatechol water) as an etch stop act because the p-doping essential for the etching free electrodes. This phenomenon is the basis of the Micromechanics and has been extensively studied there for a long time and applied. The present invention is therefore based insist that a highly p-doped etch stop layer under the wear layer used to manufacture the integrated circuit serves, is buried. In addition to silicon, the substrate also all other known semiconductor substrates such as gallium arsenide, Gallium-aluminum-arsenide, indium-phosphide, aluminum-antimonide, Gallium nitride, gallium phosphite etc. are suitable.

In a further process step it is provided that the first doped layer epitaxially on the front of the Substrate is grown. The growing up of an epitaxial Doping layer has the advantage that it has a very good single crystallinity guaranteed with low defect density of the substrate becomes.

In addition, it is contemplated that another layer epitaxially is grown on the first doped layer. The further layer is intended to be electrical in it Circuits e.g. in CMOS technology (complementary metal oxide semiconductor) are formed.

It is further provided that the first doped layer formed by implantation of dopant in the substrate becomes. The implantation of dopant enables formation a buried doped layer even without epitaxial Grow up.

A further process step provides that a second doped Layer between the front of the substrate and the first doped layer is formed, the second doped Layer is doped with a second type of dopant, that of the first dopant type of the first doped layer is opposite. Since the first doped layer at one diffused thermally driven diffusion step and thus dopant from the doped layer in the overlying diffuses another layer, the properties the shift changed. This is endowed by the second Compensated layer that has a counter-doping. To becomes the second doped layer with a dopant concentration formed which is less than the dopant concentration the first doping layer and between the front of the substrate and the first doped layer is. This arrangement makes the doping of the diffused out first doped layer by doping the second doping layer compensated.

A further process step provides that the second doped Layer as a counter doping for the first doped Layer is formed. Due to the counter-doping, the doped layer in the counter-doping area as neutral endowed.

In addition, a process step provides that a mask is formed on the front of the substrate and as Implantation mask used for the formation of the doped layer is formed so that the doped layer is structured becomes. The structured doped layer has the advantage that it is only used in the doped areas Etching stop mask acts, so that with the back etching process Structuring can be carried out using the doped Leaves areas and etches away the undoped areas.

It is also provided that the back of the substrate is etched is, the structured doped layer as an etching mask is used and thereby arranged on the substrate Chips are separated from each other. Through this process step can e.g. a subsequent sawing process is saved in which the individual chips are sawn from the wafer composite be detached.

It is also provided that the back of the substrate is etched is, the structured doped layer as an etching mask is used and thereby removes the edge of the substrate becomes. Since the thinned wafer is usually on a Carrier wafer arranged and electrically connected to this the edge of the thinned and placed on the carrier wafer bonded wafer is an exposed, sensitive area. By removing this edge, the thinned on the carrier wafer attached wafers from mechanical stress and Destruction protected.

In a further advantageous method step, the doped layer with boron p-doped. The introduction of on-board funding enables the use of KOH or EDT as etching substances.

Another advantageous embodiment of the invention The method provides that the doped layer with germanium is endowed. Germanium can also be used as an etch stop because it induces tension in the substrate. Farther Germanium can be used to relieve tension, which occur due to the on-board funding. Because boron a smaller atomic radius than silicon and germanium one has a larger atomic radius than silicon, this leads to a Tension compensation.

Another advantageous process step provides that the doped layer is doped with nitrogen. nitrogen can also be used as an etch stop because nitrogen with silicon to silicon nitride and suitable for Etching substances cannot be etched.

Another variant of the method provides that the doped Layer is doped with carbon. Carbon connects with silicon to silicon carbide and also works for suitable etching agents as an etching stop.

In a further process step it is provided that a circuit is formed on the front of the substrate. The circuit is usually made in CMOS technology, which are compatible with the substrate thinning specified here is.

Another advantageous process step provides that the surface of the substrate is attached to a carrier becomes. The attachment of the substrate with its surface a carrier allows the substrate to be viewed from its back is thinned here. Usually a is used for fastening Glue used.

It is also provided that the back of the substrate is ground becomes. Grinding the substrate has the advantage that a quick and inexpensive material removal from the back of the substrate.

Another advantageous process step provides that the back of the substrate is etched. Etching the back of the substrate e.g. after sanding the back of the substrate carried out to remove substrate damage, created by grinding.

Further advantageous embodiments of the invention are in the dependent claims.

The invention is described below using exemplary embodiments and figures explained in more detail.

Figur 1

ein Substrat mit dotierten Schichten, das an einem Montageträger befestigt ist;

Figur 2

eine Dotierstoffkonzentration, die über dem Substratquerschnitt aufgezeichnet ist.

The figures show:

Figure 1

a substrate with doped layers, which is attached to a mounting bracket;

Figure 2

a dopant concentration recorded over the substrate cross section.

In Figure 1, a substrate 1 is shown, the first doped Layer 2 has. Above the first endowed Layer 2 is another layer 3. Above the another layer 3, a second doped layer 4 is arranged. In this embodiment, the first has doped Layer 2 ap doping and the second doped layer 4 shows an n-doping. The substrate is in this embodiment made of silicon. On the second endowed Layer 4 has a wear layer 5 arranged on it Circuit element layer 6 is formed. The circuit element layer 6 includes, for example, CMOS components, resistors and capacitors. On the circuit element layer 6 the front 10 of the substrate 1 is arranged. The backside 9 is on the opposite side of the substrate 1 arranged. In the arrangement shown in Figure 1 is the circuit element layer 6 by means of an adhesive layer 7 connected to a mounting bracket 8. The specified stack of layers is formed on the lower substrate part 15.

A suitable first doped layer 2 and second doped layer 4 can be applied, for example, by means of epitaxial deposition with the addition of suitable dopants. For this purpose, a boron-doped layer is first grown on the starting substrate 15 in an epitaxial system using a CVD (chemical vapor deposition) process. Examples of suitable precursors (process gases) are silane, dichlorosilane, trichlorosilane or tetrachlorosilane in order to provide the silicon content for the CVD process. The separation temperature is between 600 ° C and 1200 ° C and the pressure between 1 and 760 Torr. Depending on the doping of the epitaxially grown doping layer, the dopant is also supplied in gaseous form. Diborane is introduced into the epitaxy system for a boron doping, phosphine for a phosphorus doping and arsine for an arsenic doping with the carrier gas hydrogen. This enables deposition rates of several µm to be achieved per minute.

In the epitaxial Aufscheidung the first doped layer 2 is first boron-doped etch stop nm as having a thickness of at least 150, but preferably formed m to 2 μ 0.5. The doping is formed between 5 x 10 ¹⁸ to 5 x 10 ²⁰ per cm ³ . A further silicon layer 3 is then deposited. A second doped layer 4 with n-dopant is deposited on the further silicon layer 3. An epitaxial CVD method is also used for this, but using phosphine or arsine. The doping of the first doped layer 2 is partially compensated for by the second doped layer 4. A silicon wear layer 5 with a thickness of up to 50 μm is then grown on the second doped layer 4. Advantageously, a smaller thickness to 15 μ m can be selected here, to make small the thickness of the thinned wafer. The circuit element layer 6 is now formed in the useful layer 5, in that integrated circuits such as CMOS transistors, resistors and capacitors are formed in the conventional manner in the useful layer 5. After completion of the circuit elements in the circuit element layer 6, the wafer shown in Figure 1 is thinned. For this purpose, the substrate 1 is glued to an assembly carrier 8 by means of an adhesive layer 7 and roughly thinned to approximately 50 μm by a grinding process. The coarse thinning can certainly leave a thicker or thinner substrate residue, but care must be taken that the first doped layer 2 is not completely removed, since in this case it can no longer act as an etch stop. A wet etching process with KOH or EDT is now carried out as the second thinning step, since this etching process can be carried out highly selectively with respect to the first doped layer 2 and stops there. Tilting of the substrate 1, which results in the substrate 1 being ground obliquely, can be corrected by this method. The first doping layer 2, the further layer 3 and the second doped layer 4 can then be removed by a conventional etching process step in order to avoid later undesired diffusion of dopants during operation of the circuit.

Alternatively, the doped layer 2 in the wafer can be achieved by implanting dopant atoms. For this purpose, an implantation energy of 2.5 MeV can be used, for example, so that the maximum of the dopant concentration of boron lies at a depth of approximately 3.5 μm below the silicon surface 10. With this method, extremely thin substrates can be produced, for example. For this purpose, the substrate is first implanted with a boron dopant implantation with an implantation energy of 2.5 MeV and a dopant concentration of 10 ²⁰ boron atoms per cm ³ . The boron concentration directly on the substrate surface 10 is approximately four orders of magnitude lower and therefore does not interfere with the normal manufacturing process of the circuit element layer 6. If appropriate, a trough implantation can be carried out in order to adapt the components of the circuit element layer 6 to the buried first doped layer 2, which is doped with boron.

Alternatively, an etch stop layer can also be implemented by implantation of germanium, nitrogen or carbon atoms become.

The high dose boron implantation causes tension in the Crystal lattice, causing disruption in the growth of the epitaxial grown, subsequent silicon layer can lead. This is because the atomic radius of boron is less than that of silicon. The tension in the crystal lattice can can be avoided by at the same time germanium atoms, the one have a larger atomic radius than silicon in the crystal lattice to be built in. Germanium behaves electrically neutral and does not interfere with the function of the first doped layer 2 as an etch stop, but compensates for the mechanical tension.

If a mask made of an oxide layer is arranged on the substrate 1, which partially covers the substrate surface and partially exposed, the implantation of the first doped Layer 2 is done through the mask. This will be the first doped layer 2 structured and the thinning The back of the wafer can also be used for structuring of the wafer to be thinned. For example, can the wafer edge be removed to damage the thin chips in subsequent processes, e.g. by transport in wafer boxes and by wafer handlers or clamping devices in process chambers to avoid. The areas of the wafer, on which the wafer later saws into individual chips is sawed, excluded from the implantation, by the etching process that performs the thinning of the wafers simultaneously the chips have been separated. This will for example, damage when sawing the wafer later avoided.

A structured doping of the first doped layer 2 can also be achieved with epitaxial deposition by first deposited a thin oxide layer on the substrate and is structured with photolithography. On the Open areas where the silicon is exposed can be selective a highly boron-doped silicon layer can be grown. The selective epitaxy grows on the thin oxide layer no doped silicon layer. After removing the Oxide mask can epitaxially silicon to the desired area Target thickness can be grown.

With reference to Figure 2 is a graph with a first axis 13 shown, which indicates the dopant concentration, and one second axis 14, which points into the substrate depth. Farther the front 10 of the substrate 1 is shown and along the axis 14, which runs into the substrate depth, the Doping profile of the first diffused doping layer 11 and of the second diffused doping layer 12. The first doped layer 2 from FIG. 1 and the second doped Layer 4 from FIG. 1 run through a temperature step to the doping profiles shown in FIG. 2 (11, 12). Compensates near the substrate surface 10 the second diffused doping layer 12 the electrical Effect of the first diffused doping layer 11.

Reference list

1

Semiconductor substrate

2nd

First doped layer

3rd

another layer

4th

Second doped layer

5

Wear layer

6

Circuit element layer

7

Adhesive layer

8th

Mounting bracket

9

back

10th

front

11

First diffused doping layer

12th

Second diffused doping layer

13

Dopant concentration

14

Substrate depth

15

Lower substrate area

Claims (17)

Method for thinning a substrate, comprising the steps: Providing a substrate (1) with a front (10) and a back (9); Forming a wear layer on the front side (10) of the substrate (1); Forming a first doped layer (2) in the substrate (1); wet chemical etching of the substrate (1), the substrate (1) being thinned from the rear (9) and the first doped layer (2) being used as an etching stop. Method according to claim 1,
characterized in that
the first doped layer (2) is grown epitaxially on the front side (10) of the substrate (1). Method according to claim 2,
characterized in that
a further layer (3) is grown epitaxially on the first doped layer (2). Method according to claim 1,
characterized in that
the first doped layer (2) is formed by implanting dopant in the substrate (1). Method according to one of claims 1 to 4,
characterized in that
a second doped layer (4) is formed between the front side (10) of the substrate (1) and the first doped layer (2), the second doped layer (4) being doped with a second dopant type that corresponds to the first dopant type of the first doped layer (2) is opposite. Method according to one of claims 1 to 5,
characterized in that
the second doped layer (4) is formed as a counter-doping for the first doped layer (2). Method according to one of claims 1 to 6,
characterized in that
a mask is formed on the front side (10) of the substrate (1) and is used as an implantation mask for the formation of the first doped layer (2), so that the first doped layer (2) is structured. Method according to claim 7,
characterized in that
the back (9) of the substrate (1) is etched, the structured doped layer being used as an etching mask, and chips arranged on the substrate (1) are thereby separated from one another. Method according to claim 7 or 8,
characterized in that
the back (9) of the substrate (1) is etched, the structured doped layer being used as an etching mask and the edge of the substrate (1) being thereby removed. Method according to one of claims 1 to 9,
characterized in that
the first doped layer (2) is p-doped with boron. Method according to one of claims 1 to 10,
characterized in that
the first doped layer (2) is doped with germanium. Method according to one of claims 1 to 11,
characterized in that
the first doped layer (2) is doped with nitrogen. Method according to one of claims 1 to 12,
characterized in that
the first doped layer (2) is doped with carbon. Method according to one of claims 1 to 13,
characterized in that
a circuit is formed on the front (10) of the substrate (1). Method according to one of claims 1 to 14,
characterized in that
the substrate is attached with its front side (10) to a mounting bracket (8). Method according to one of claims 1 to 15,
characterized in that
the back (9) of the substrate (1) is ground off. Method according to one of claims 1 to 16,
characterized in that
the back (9) of the substrate (1) is etched.

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