EP1160642A1 - Current limiting circuit - Google Patents

Current limiting circuit Download PDF

Info

Publication number
EP1160642A1
EP1160642A1 EP01109666A EP01109666A EP1160642A1 EP 1160642 A1 EP1160642 A1 EP 1160642A1 EP 01109666 A EP01109666 A EP 01109666A EP 01109666 A EP01109666 A EP 01109666A EP 1160642 A1 EP1160642 A1 EP 1160642A1
Authority
EP
European Patent Office
Prior art keywords
current
fet
load
input
current mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP01109666A
Other languages
German (de)
French (fr)
Other versions
EP1160642B1 (en
Inventor
Jürgen Dr.-Ing. Boldt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IDT Europe GmbH
Original Assignee
Zentrum Mikroelektronik Dresden GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zentrum Mikroelektronik Dresden GmbH filed Critical Zentrum Mikroelektronik Dresden GmbH
Publication of EP1160642A1 publication Critical patent/EP1160642A1/en
Application granted granted Critical
Publication of EP1160642B1 publication Critical patent/EP1160642B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the invention relates to a circuit arrangement for current limitation variable load currents in circuits with a Power supply for a series connection, consisting of one Load current control FET and a consumer, the series connection is switched between power supply and ground, with a differential amplifier that with a first and a second input and an output is provided, on which second input a reference voltage source is connected and the output is connected to the gate of the load current control FET is and an operating voltage source.
  • the load current path as a series connection of a current source resistor, a load current control FET and the consumer is running.
  • a differential amplifier switched so that an input of the differential amplifier a reference voltage, the other input that Voltage potential, which is above the current source resistance has set, evaluates and at the output the amplified Differential signal through the gate of the load current control FET Regulates load current.
  • the current source resistance is dimensioned that when there is a maximum load current in the load current path the load current control FET with the load current limit is used.
  • Such current limiter circuits prove to be disadvantageous in that for feeding electricity into the consumer, e.g. by a current source resistance, a voltage swing between Operating voltage source and consumer must be provided so that for the consumer only a significantly reduced Usable range of the operating voltage can be made available can.
  • the invention is based on the object of a load current limitation so that the consumer the operating voltage range as complete as possible poses.
  • the object underlying the invention is achieved by Circuit arrangement solved in such a way that the current feed via a newly introduced current mirror, one of which Current path, the load current path via the load current control FET carries the load current of the consumer, whose other Stro mpfad is executed as a current mirror control path and the over the current mirror control FET a mirrored load current wearing.
  • Current mirrors are the transistors of the current mirror, load current control FET and current mirror control FET, e.g. on the same substrate of a circuit, have a common gate connection and are dimensioned in their geometry so that when driving both transistors in the same Working point the ratio load current: mirrored Load current behaves as n: 1.
  • load current control FETs form and current mirror control FET a current mirror and are connected to the Operating voltage connected.
  • the Load current control FET By connecting the Load current control FET with the consumer flows in it Current path of the current mirror a load current. That about the consumer the voltage potential that arises is transmitted via a connected input of the operational amplifier sampled. Since the operational amplifier has the gate of the output side Current mirror coupling FET controls and by connecting the other input of the operational amplifier with the source connection of the current mirror coupling FET switched as a voltage follower the potential at the drain connection of the Current mirror control FET by the load current at the consumer generated voltage potential. This ensures that the current mirror ratio is exactly 1: n. The factor n mirrored load current generated across the current limiting resistor a voltage drop.
  • This potential is due to Input of the differential amplifier. There it will be with the Reference voltage at the other input of the differential amplifier switched reference voltage source compared. If this potential exceeds the reference voltage of the reference voltage source this is how it controls the output of the differential amplifier amplified difference signal by controlling the common gate connections of current mirror control FET and Load current control FET due to potential increase in its source drain The path closes and the current limitation begins. The point of use this current limitation can be adjusted by adjusting the current limiting resistor or the reference voltage source.

Abstract

The circuit provides current limiting for varying load currents in circuits with a current supply for a series circuit including a load current control FET and a load. A differential amplifier (3) is provided. A reference voltage source is connected to the second input of the amplifier. The output is connected to the gate of the FET. A current mirror including a mirror control FET and the load current control FET (1) is arranged such that the sources of both FETs are connected to an operating voltage source (9). The mirror is in a control path comprising a current mirror coupling FET whose source is connected to the drain of the mirror control FET, and whose drain is connected to the first input of the amplifier (3). The drain of the coupling FET is connected in series with a current limiting resistor (6) to earth. The amplifier output is connected to the gate of the mirror control FET. A second differential amplifier (7) is provided. The first input is connected to the source of the coupling FET. The second input is connected to the load (2) and to the drain of the load FET (1). The output is connected to the gate of the coupling FET.

Description

Die Erfindung betrifft eine Schaltungsanordnung zur Strombegrenzung veränderlicher Lastströme in Schaltungen mit einer Stromeinspeisung für eine Reihenschaltung, bestehend aus einem Laststrom-Steuer-FET und einem Verbraucher, wobei die Reihenschaltung zwischen Stromeinspeisung und Masse geschaltet wird, mit einem Differenzverstärker, der mit einem ersten und einem zweiten Eingang sowie einem Ausgang versehen ist, wobei an dem zweiten Eingang eine Referenzspannungsquelle angeschlossen ist und der Ausgang mit dem Gate des Laststrom-Steuer-FET verbunden ist und einer Betriebsspannungsquelle.The invention relates to a circuit arrangement for current limitation variable load currents in circuits with a Power supply for a series connection, consisting of one Load current control FET and a consumer, the series connection is switched between power supply and ground, with a differential amplifier that with a first and a second input and an output is provided, on which second input a reference voltage source is connected and the output is connected to the gate of the load current control FET is and an operating voltage source.

Treten in Schaltungen Verbraucher mit hohen Lastströmen auf, variieren diese insbesondere in ihrer Größe sehr stark, ergeben sich wegen des nur endlich kleinen Innenwiderstandes der Betriebsspannungsquelle Schwankungen der Betriebsspannung, die sich auf alle angeschlossenen Schaltungsteile störend auswirken. Daher kommen zur Betriebsspannungsstabilisierung verschiedene technische Lösungen, insbesondere Strombegrenzungs-schaltungen für die Begrenzung des Laststromes, zum Einsatz. Diese Strombegrenzungsschaltungen werden so dimensioniert, daß sie im Laststrompfad nur solch einen maximalen Laststrom für den Verbraucher zur Verfügung stellen, bei dem einerseits die Funktion des Verbrauchers nicht beeinträchtigt wird, anderseits die bei dieser Belastung der Betriebsspannungsquelle resultierende Betriebsspannungsänderung sich für alle Schaltungsteile nicht störend auswirkt.If consumers with high load currents occur in circuits, these vary greatly, especially in size because of the finite internal resistance Operating voltage source fluctuations in the operating voltage interfere with all connected circuit parts. For this reason, various stabilization voltages come technical solutions, in particular current limiting circuits for the limitation of the load current. These current limiting circuits are dimensioned so that in the load current path only such a maximum load current for make available to the consumer, on the one hand the Function of the consumer is not affected, on the other hand the at this load on the operating voltage source resulting operating voltage change for all circuit parts does not interfere.

Es ist nunmehr bekannt, daß in derartigen Strombegrenzungs-schaltungen der Laststrompfad als eine Reihenschaltung von einem Stromquellenwiderstand, einem Laststrom-Steuer-FET und des Verbrauchers ausgeführt wird. Zusätzlich wird ein Differenzverstärker so geschaltet, daß ein Eingang des Differenzverstärkers eine Referenzspannung, der andere Eingang das Spannungspotential, welches sich über dem Stromquellenwiderstand eingestellt hat, auswertet und am Ausgang das verstärkte Differenzsignal über das Gate des Laststrom-Steuer-FET den Laststrom regelt. Der Stromqellenwiderstand ist so dimensioniert, daß bei anliegendem maximalen Lastrom im Laststrompfad der Laststrom-Steuer-FET mit der Laststrombegrenzung einsetzt.It is now known that in such current limiting circuits the load current path as a series connection of a current source resistor, a load current control FET and the consumer is running. In addition, a differential amplifier switched so that an input of the differential amplifier a reference voltage, the other input that Voltage potential, which is above the current source resistance has set, evaluates and at the output the amplified Differential signal through the gate of the load current control FET Regulates load current. The current source resistance is dimensioned that when there is a maximum load current in the load current path the load current control FET with the load current limit is used.

Als nachteilig erweisen sich solche Strombegrenzerschaltungen dahingehend, daß zur Stromeinspeisung in den Verbraucher, z.B. durch einen Stromquellenwiderstand, ein Spannungshub zwischen Betriebsspannungsquelle und Verbraucher vorgesehen werden muß, so daß für den Verbraucher nur ein erheblich verringerter Nutzbereich der Betriebsspannung zur Verfügung gestellt werden kann.Such current limiter circuits prove to be disadvantageous in that for feeding electricity into the consumer, e.g. by a current source resistance, a voltage swing between Operating voltage source and consumer must be provided so that for the consumer only a significantly reduced Usable range of the operating voltage can be made available can.

Der Erfindung liegt nunmehr die Aufgabe zugrunde, eine Laststrombegrenzung so auszuführen, daß diese dem Verbraucher den möglichst vollständigen Betriebsspannungsbereich zu Verfügung stellt.The invention is based on the object of a load current limitation so that the consumer the operating voltage range as complete as possible poses.

Die der Erfindung zugrunde liegenden Aufgabe wird durch die Schaltungsanordnung derartig gelöst, daß die Stromeinspeisung über einen neu eingeführten Stromspiegel erfolgt, dessen einer Strompfad, der Laststrompfad, der über den Laststrom-Steuer-FET den Laststrom des Verbrauchers trägt, dessen anderer Stro mpfad als Stromspiegel-Steuerpfad ausgeführt wird und der über den Stromspiegel-Steuer-FET einen gespiegelter Laststrom trägt. Gemäß dem üblichen konstruktivem Aufbau von Stromspiegeln sind die Transistoren des Stromspiegels, Laststrom-Steuer-FET und Stromspiegel-Steuer-FET, z.B. auf dem gleichen Substrat eines Schaltkreises angeordnet, haben einen gemeinsamen Gateanschluß und sind in ihrer Geometrie so dimensioniert, daß bei Ansteuerung beider Transistoren im gleichem Arbeitspunkt sich das Verhältnis Laststrom : gespiegelter Laststrom wie n:1 verhält.The object underlying the invention is achieved by Circuit arrangement solved in such a way that the current feed via a newly introduced current mirror, one of which Current path, the load current path via the load current control FET carries the load current of the consumer, whose other Stro mpfad is executed as a current mirror control path and the over the current mirror control FET a mirrored load current wearing. According to the usual design of Current mirrors are the transistors of the current mirror, load current control FET and current mirror control FET, e.g. on the same substrate of a circuit, have a common gate connection and are dimensioned in their geometry so that when driving both transistors in the same Working point the ratio load current: mirrored Load current behaves as n: 1.

Erfindungsgemäß wird das über dem Verbraucher sich einstellende Spannungspotential nicht unmittelbar vom Differenzverstärker ausgewertet, sondern dieses wird mittels zusätzlich ausgeführtem Spannungsfolger-Operationsverstärker abgetastet und ausgangsseitig über das Gate eines Stromspiegel-Koppel-FET so eingekoppelt, daß die Laststromgröße des Laststrompfades im Stromspiegel-Steuerpfad über einen Strombegrenzungswiderstand potentialmäßig repräsentiert wird. Hierbei wird dieses repräsentative Spannungspotential an einem Eingang des Differenzverstärkers ausgewertet und es wird gemeinsam mit der am anderen Eingang anliegenden Referenzspannung am Ausgang des Differenzverstärkers ein verstärktes Differenzsignal gebildet und zur Ansteuerung des gemeinsamen Gates der Stromspiegel-FET verwendet. Diese Ansteuerung der Stromspiegel-FET erfolgt in einem solchen Arbeitspunkt, der bei Erreichen des vorgesehenen maximalen Laststromes die Source-Drainspannung der Stromspiegel-FET noch als Restspannung hinreichend klein realisiert damit diese für die Verbraucherfunktion vernachlässigbar ist.According to the situation that arises above the consumer Voltage potential not directly from the differential amplifier evaluated, but this is by means of additional executed voltage follower operational amplifier sampled and on the output side via the gate of a current mirror coupling FET so coupled that the load current magnitude of the load current path in the current mirror control path via a current limiting resistor is represented in terms of potential. Here this is representative voltage potential at an input of the differential amplifier evaluated and it is jointly with the am reference voltage present at the output of the other input Differential amplifier formed an amplified differential signal and for driving the common gate of the current mirror FET used. This control of the current mirror FET takes place in such an operating point, which is reached when the intended maximum load current is the source-drain voltage of the current mirror FET realized as a sufficiently small residual voltage so that it is negligible for the consumer function.

Die Erfindung soll nachfolgend anhand eines Ausführungsbeispieles näher erläutert werden. Die zugehörige Zeichnung zeigt ein Blockschaltbild der erfindungsgemäßen SchaltungsanordnungThe invention is intended to be explained below using an exemplary embodiment are explained in more detail. The accompanying drawing shows a block diagram of the circuit arrangement according to the invention

Wie in der Zeichnung ersichtlich, bilden Laststrom-Steuer-FET und Stromspiegel-Steuer-FET einen Stromspiegel und sind an die Betriebsspannung angeschlossen. Durch die Reihenschaltung des Laststrom-Steuer-FET mit dem Verbraucher fließt in diesem Strompfad des Stromspiegels ein Laststrom. Das über dem Verbraucher sich einstellende Spannungspotential wird über einen angeschlossenen Eingang des Operationsverstärkers abgetastet. Da der Operationsverstärker ausgangsseitig das Gate des Stromspiegel-Koppel-FET ansteuert und durch die Verbindung des anderen Eingangs des Operationsverstärkers mit dem Source-Anschluß des Stromspiegel-Koppel-FET als Spannungsfolger geschaltet ist, folgt auch das Potential am Drain-Anschluß des Stromspiegel-Steuer-FET dem durch den Laststrom am Verbraucher erzeugten Spannungspotential. Dadurch ist gewährleistet, daß das Stromspiegelverhältnis exakt 1:n beträgt. Der um den Faktor n gespiegelte Laststrom erzeugt über dem Strombegrenzungswiderstand einen Spannungsabfall. Dieses Potential liegt am Eingang des Differenzverstärkers an. Dort wird es mit der Referenzspannung der an dem anderen Eingang des Differenzverstärkers geschalteten Referenzspannungsquelle verglichen. Übersteigt dieses Potential die Referenzspannung der Referenzspannungsquelle so steuert das am Ausgang des Differenzverstärkers verstärkte Differenzsignal durch die Ansteuerung der gemeinsamen Gate-Anschlüsse von Stromspiegel-Steuer-FET und Laststrom-Steuer-FET durch Potentialanstieg deren Source-Drain Strecke zu und die Strombegrenzung setzt ein. Der Einsatzpunkt dieser Strombegrenzung kann durch Abgleich des Strombegrenzungswiderstandes oder der Referenzspannungsquelle erfolgen. As can be seen in the drawing, load current control FETs form and current mirror control FET a current mirror and are connected to the Operating voltage connected. By connecting the Load current control FET with the consumer flows in it Current path of the current mirror a load current. That about the consumer the voltage potential that arises is transmitted via a connected input of the operational amplifier sampled. Since the operational amplifier has the gate of the output side Current mirror coupling FET controls and by connecting the other input of the operational amplifier with the source connection of the current mirror coupling FET switched as a voltage follower the potential at the drain connection of the Current mirror control FET by the load current at the consumer generated voltage potential. This ensures that the current mirror ratio is exactly 1: n. The factor n mirrored load current generated across the current limiting resistor a voltage drop. This potential is due to Input of the differential amplifier. There it will be with the Reference voltage at the other input of the differential amplifier switched reference voltage source compared. If this potential exceeds the reference voltage of the reference voltage source this is how it controls the output of the differential amplifier amplified difference signal by controlling the common gate connections of current mirror control FET and Load current control FET due to potential increase in its source drain The path closes and the current limitation begins. The point of use this current limitation can be adjusted by adjusting the current limiting resistor or the reference voltage source.

BezugszeichenlisteReference list

11
Laststrom-Steuer-FETLoad current control FET
22nd
Verbraucherconsumer
33rd
DifferenzverstärkerDifferential amplifier
44th
Stromspiegel-Steuer-FETCurrent mirror control FET
55
Stromspiegel-Koppel-FETCurrent mirror coupling FET
66
StrombegrenzungswiderstandCurrent limiting resistor
77
zweiter Differenzverstärkersecond differential amplifier
88th
ReferenzspannungsquelleReference voltage source
99
BetriebsspannungsquelleOperating voltage source
IL I L
LaststromLoad current
Ig I g
gespiegelter Laststrommirrored load current

Claims (1)

Schaltungsanordnung zur Strombegrenzung veränderlicher Lastströme in Schaltungen mit einer Stromeinspeisung für eine Reihenschaltung bestehend aus einem Laststrom-Steuer-FET und einem Verbraucher, wobei die Reihenschaltung zwischen Stromeinspeisung und Masse geschaltet wird, mit einem Differenzverstärker, der mit einem ersten und einem zweiten Eingang sowie einem Ausgang versehen ist, wobei an dem zweiten Eingang eine Referenzspannungsquelle angeschlossen ist und der Ausgang mit dem Gate des Laststrom-Steuer-FET verbunden ist, und einer Betriebsspannungsquelle dadurch gekennzeichnet, daß ein Stromspiegel angeordnet ist, der aus einem Stromspiegel-Steuer-FET (4) und dem Laststrom-Steuer-FET (1) besteht, daß der Sourceanschluss des Laststrom-Steuer-FET (1) und der Sourceanschluss des Stromspiegel-Steuer-FET (4) mit der Betriebsspannungsquelle (9) verbunden ist und daß dem Stromspiegel ein Stromspiegel-Steuerpfad zugeordnet ist, bestehend aus einem Stromspiegel-Koppel-FET (5), dessen Sourceanschluss mit dem Drainanschluss des Stromspiegel-Steuer-FET (4) verbunden ist und dessen Drainanschluss mit dem ersten Eingang des Differenzverstärkers (3) verbunden ist, und einem Strombegrenzungswiderstand (6), wobei der Drainanschluss des Stromspiegel-Koppel-FET (5) zusätzlich mit dem Strombegrenzungswiderstand (6) in Reihe nach Masse geschaltet ist, daß der Ausgang des Differenzverstärker (3) mit dem Gate des Stromspiegel-Steuer-FET (4) verbunden ist, daß ein zweiter Differenzverstärker(7) mit einem ersten und zweiten Eingang und einem Ausgang angeordnet ist, wobei der erste Eingang des zweiten Differenzverstärkers (7) mit dem Sourceanschluss des Stromspiegel-Koppel-FET (5), der zweite Eingang des zweiten Differenzverstärkers (7) mit dem Verbraucher (2) und dem Drainanschluss des Laststrom-Steuer-FET (1) verbunden ist und der Ausgang an das Gate des Stromspiegel-Koppel-FET (5) angeschlossen ist.Circuit arrangement for current limitation of variable load currents in circuits with a current feed for a series circuit consisting of a load current control FET and a consumer, the series circuit being switched between current feed and ground, with a differential amplifier which has a first and a second input and an output is provided, a reference voltage source being connected to the second input and the output being connected to the gate of the load current control FET, and an operating voltage source characterized in that a current mirror is arranged which consists of a current mirror control FET (4) and the load current control FET (1) is that the source of the load current control FET (1) and the source of the current mirror control FET (4) is connected to the operating voltage source (9) and that the current mirror is a current mirror Control path is assigned, consisting of a current mirror coupling FET (5), the en source connection is connected to the drain connection of the current mirror control FET (4) and its drain connection is connected to the first input of the differential amplifier (3), and a current limiting resistor (6), the drain connection of the current mirror coupling FET (5) additionally connected to the current limiting resistor (6) in series to ground, that the output of the differential amplifier (3) is connected to the gate of the current mirror control FET (4), that a second differential amplifier (7) with a first and second input and an output is arranged, the first input of the second differential amplifier (7) with the source connection of the current mirror coupling FET (5), the second input of the second differential amplifier (7) with the consumer (2) and the drain connection of the load current Control FET (1) is connected and the output is connected to the gate of the current mirror coupling FET (5).
EP01109666A 2000-05-31 2001-04-19 Current limiting circuit Expired - Lifetime EP1160642B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10026793 2000-05-31
DE10026793A DE10026793A1 (en) 2000-05-31 2000-05-31 Current limiting circuit

Publications (2)

Publication Number Publication Date
EP1160642A1 true EP1160642A1 (en) 2001-12-05
EP1160642B1 EP1160642B1 (en) 2011-05-25

Family

ID=7644102

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01109666A Expired - Lifetime EP1160642B1 (en) 2000-05-31 2001-04-19 Current limiting circuit

Country Status (3)

Country Link
EP (1) EP1160642B1 (en)
AT (1) ATE511133T1 (en)
DE (1) DE10026793A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009076304A1 (en) * 2007-12-12 2009-06-18 Sandisk Corporation Current mirror device and method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7679876B2 (en) * 2006-05-22 2010-03-16 Mediatek Singapore Pte Ltd. Current limiter system, circuit and method for limiting current
DE102020209371A1 (en) 2020-07-24 2022-01-27 Robert Bosch Gesellschaft mit beschränkter Haftung Current control with at least one field effect transistor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0356570A1 (en) * 1988-09-02 1990-03-07 Siemens Aktiengesellschaft Current mirror
US5519310A (en) * 1993-09-23 1996-05-21 At&T Global Information Solutions Company Voltage-to-current converter without series sensing resistor
US5847556A (en) * 1997-12-18 1998-12-08 Lucent Technologies Inc. Precision current source
EP0994402A1 (en) * 1998-10-15 2000-04-19 Lucent Technologies Inc. Current mirror
US6064267A (en) * 1998-10-05 2000-05-16 Globespan, Inc. Current mirror utilizing amplifier to match operating voltages of input and output transconductance devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0356570A1 (en) * 1988-09-02 1990-03-07 Siemens Aktiengesellschaft Current mirror
US5519310A (en) * 1993-09-23 1996-05-21 At&T Global Information Solutions Company Voltage-to-current converter without series sensing resistor
US5847556A (en) * 1997-12-18 1998-12-08 Lucent Technologies Inc. Precision current source
US6064267A (en) * 1998-10-05 2000-05-16 Globespan, Inc. Current mirror utilizing amplifier to match operating voltages of input and output transconductance devices
EP0994402A1 (en) * 1998-10-15 2000-04-19 Lucent Technologies Inc. Current mirror

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SERRANO T ET AL: "THE ACTIVE-IMPUT REGULATED-CASCODE CURRENT MIRROR", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS, IEEE INC. NEW YORK, US, vol. 41, no. 6, 1 June 1994 (1994-06-01), pages 464 - 467, XP000460535, ISSN: 1057-7122 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009076304A1 (en) * 2007-12-12 2009-06-18 Sandisk Corporation Current mirror device and method
US8786359B2 (en) 2007-12-12 2014-07-22 Sandisk Technologies Inc. Current mirror device and method

Also Published As

Publication number Publication date
DE10026793A1 (en) 2002-01-03
ATE511133T1 (en) 2011-06-15
EP1160642B1 (en) 2011-05-25

Similar Documents

Publication Publication Date Title
DE69833635T2 (en) Amplification arrangement with voltage amplification and reduced power consumption
EP0509113B1 (en) Output buffer amplifier with high signal amplitude
DE3028614A1 (en) Field effect transconductance amplifiers
DE102005054216B4 (en) Output stage, amplifier control loop and use of the output stage
DE3835499A1 (en) CIRCUIT ARRANGEMENT FOR ADJUSTING THE AMPLITUDE OF A SIGNAL
DE3828546A1 (en) HIGH-SPEED POWER AMPLIFIER CIRCUIT
DE4444623A1 (en) Power MOSFET load current control circuit
DE10149585A1 (en) Integrated, controllable delay circuit, has multiplexers connected together in series, with delay time set by number of multiplexers through which clock signal passes
EP0262480B1 (en) Current mirror circuit arrangement
DE19533768C1 (en) Current sourcing circuit with cross current regulation esp. for CMOS circuit
DE102005030565B3 (en) Class D power output stage for driving xDSL signals has switching transistors whose voltage potential is lower than that of delimitation transistors
EP0685782B1 (en) Voltage regulator
EP1160642B1 (en) Current limiting circuit
DE4138661C1 (en)
DE102004019345B4 (en) Output stage system
DE102004060212A1 (en) Level converter for signal processing circuits has amplifier which generates difference signal after comparing potential at output with reference potential on which control signal is dependent
EP1163724B1 (en) Compensation circuit for driver circuits
EP0869614B1 (en) Input amplifier for input signals with steep edges
DE19713833C1 (en) Input amplifier for input signals with steep edges, in particular high-low edges
DE102004042354B4 (en) Current mirror arrangement
EP0277377A1 (en) Current limiting circuit
EP1844382B1 (en) Filter circuit
DE4431466C1 (en) Voltage regulator e.g. for Hall element supply, motor vehicle applications etc.
DE2933847C2 (en) Circuit arrangement for receiving direct current signals in teleprinter and data transmission systems
EP0779702B1 (en) Electric circuit for converting an input voltage

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

17P Request for examination filed

Effective date: 20020504

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: ZENTRUM MIKROELEKTRONIK DRESDEN AG

AKX Designation fees paid

Free format text: AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

17Q First examination report despatched

Effective date: 20040423

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: GERMAN

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 50115890

Country of ref document: DE

Effective date: 20110707

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20110525

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110525

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110926

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110525

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110905

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110525

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110826

REG Reference to a national code

Ref country code: IE

Ref legal event code: FD4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110525

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110525

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110525

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20120228

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110525

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 50115890

Country of ref document: DE

Effective date: 20120228

BERE Be: lapsed

Owner name: ZENTRUM MIKROELEKTRONIK DRESDEN A.G.

Effective date: 20120430

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120430

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20120419

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20121228

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120430

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120419

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120430

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120430

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120430

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110525

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120419

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20170427

Year of fee payment: 17

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: AT

Payment date: 20170403

Year of fee payment: 17

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 50115890

Country of ref document: DE

REG Reference to a national code

Ref country code: AT

Ref legal event code: MM01

Ref document number: 511133

Country of ref document: AT

Kind code of ref document: T

Effective date: 20180419

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180419

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20181101