EP1163596A4 - Methods and apparatus for facilitating direct memory access - Google Patents

Methods and apparatus for facilitating direct memory access

Info

Publication number
EP1163596A4
EP1163596A4 EP00911873A EP00911873A EP1163596A4 EP 1163596 A4 EP1163596 A4 EP 1163596A4 EP 00911873 A EP00911873 A EP 00911873A EP 00911873 A EP00911873 A EP 00911873A EP 1163596 A4 EP1163596 A4 EP 1163596A4
Authority
EP
European Patent Office
Prior art keywords
methods
memory access
direct memory
facilitating direct
facilitating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00911873A
Other languages
German (de)
French (fr)
Other versions
EP1163596A1 (en
Inventor
Henry Stracovsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1163596A1 publication Critical patent/EP1163596A1/en
Publication of EP1163596A4 publication Critical patent/EP1163596A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
EP00911873A 1999-02-22 2000-02-18 Methods and apparatus for facilitating direct memory access Withdrawn EP1163596A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12102299P 1999-02-22 1999-02-22
PCT/US2000/004247 WO2000051004A1 (en) 1999-02-22 2000-02-18 Methods and apparatus for facilitating direct memory access
US121022P 2008-12-09

Publications (2)

Publication Number Publication Date
EP1163596A1 EP1163596A1 (en) 2001-12-19
EP1163596A4 true EP1163596A4 (en) 2004-12-01

Family

ID=22393995

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00911873A Withdrawn EP1163596A4 (en) 1999-02-22 2000-02-18 Methods and apparatus for facilitating direct memory access

Country Status (6)

Country Link
EP (1) EP1163596A4 (en)
JP (1) JP2002538522A (en)
KR (1) KR20010102285A (en)
CN (1) CN1153153C (en)
AU (1) AU3369700A (en)
WO (1) WO2000051004A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8634415B2 (en) 2011-02-16 2014-01-21 Oracle International Corporation Method and system for routing network traffic for a blade server
CN105706058B (en) * 2013-11-05 2019-09-20 甲骨文国际公司 For supporting the buffer area of efficient packet transaction model and the optimization for packet transaction utilizes in network environment system and method
US9489327B2 (en) 2013-11-05 2016-11-08 Oracle International Corporation System and method for supporting an efficient packet processing model in a network environment
KR20190123984A (en) * 2018-04-25 2019-11-04 에스케이하이닉스 주식회사 Memory system and operating method thereof
CN114691562A (en) * 2020-12-29 2022-07-01 中科寒武纪科技股份有限公司 Method, device and equipment for DMA operation, integrated circuit chip and board card

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481578A (en) * 1982-05-21 1984-11-06 Pitney Bowes Inc. Direct memory access data transfer system for use with plural processors
US5175841A (en) * 1987-03-13 1992-12-29 Texas Instruments Incorporated Data processing device with multiple on-chip memory buses
US5524265A (en) * 1994-03-08 1996-06-04 Texas Instruments Incorporated Architecture of transfer processor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4608631A (en) * 1982-09-03 1986-08-26 Sequoia Systems, Inc. Modular computer system
US5003465A (en) * 1988-06-27 1991-03-26 International Business Machines Corp. Method and apparatus for increasing system throughput via an input/output bus and enhancing address capability of a computer system during DMA read/write operations between a common memory and an input/output device
US5359723A (en) * 1991-12-16 1994-10-25 Intel Corporation Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only
US5603050A (en) * 1995-03-03 1997-02-11 Compaq Computer Corporation Direct memory access controller having programmable timing
US5987590A (en) * 1996-04-02 1999-11-16 Texas Instruments Incorporated PC circuits, systems and methods
US5893153A (en) * 1996-08-02 1999-04-06 Sun Microsystems, Inc. Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481578A (en) * 1982-05-21 1984-11-06 Pitney Bowes Inc. Direct memory access data transfer system for use with plural processors
US5175841A (en) * 1987-03-13 1992-12-29 Texas Instruments Incorporated Data processing device with multiple on-chip memory buses
US5524265A (en) * 1994-03-08 1996-06-04 Texas Instruments Incorporated Architecture of transfer processor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO0051004A1 *

Also Published As

Publication number Publication date
EP1163596A1 (en) 2001-12-19
AU3369700A (en) 2000-09-14
CN1153153C (en) 2004-06-09
WO2000051004A1 (en) 2000-08-31
CN1352773A (en) 2002-06-05
KR20010102285A (en) 2001-11-15
JP2002538522A (en) 2002-11-12

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