EP1271866A2 - A fault tolerant shared transceiver apparatus and associated system - Google Patents
A fault tolerant shared transceiver apparatus and associated system Download PDFInfo
- Publication number
- EP1271866A2 EP1271866A2 EP02004104A EP02004104A EP1271866A2 EP 1271866 A2 EP1271866 A2 EP 1271866A2 EP 02004104 A EP02004104 A EP 02004104A EP 02004104 A EP02004104 A EP 02004104A EP 1271866 A2 EP1271866 A2 EP 1271866A2
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- EP
- European Patent Office
- Prior art keywords
- microcontroller
- additional
- fault tolerant
- transceiver apparatus
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000872 buffer Substances 0.000 claims description 6
- 230000015654 memory Effects 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/437—Ring fault isolation or reconfiguration
Definitions
- the present invention relates generally to a fault tolerant shared transceiver apparatus and system. More specifically, the invention relates to, for example, sharing a single duplex link transceiver of a microcontroller in a fault tolerant distributed microcontroller or computing system.
- Braking systems are an example of an automotive electronic application that may utilize distributed microcontroller systems.
- distributed microcontroller systems are increasingly being used in braking systems known as "brake-by-wire", in place of mechanical and/or traditional hydraulic based braking systems.
- fault tolerant distributed computing or microcontroller networks typically require a microcontroller at each node.
- Some distributed microcontroller networks comprise multiple nodes that are connected together via bi-directional buses or links.
- microcontrollers having two transceiver links that are capable of receiving two or more inputs and transmitting two or more outputs are implemented.
- these multiple transceiver microcontrollers are relatively substantially more expensive then less expensive single transceiver microcontrollers.
- microcontrollers having one transceiver have less power dissipation, and have a higher reliability due to a much simpler design than microcontrollers with two transceivers.
- a type of fault tolerant distributed microcontroller network is designed without implementing the multiple transceiver microcontrollers.
- this network requires a separate router that is connected to each node microcontroller, which increases complexity to the system.
- the router itself requires at least one microcontroller, and this also increases to the complexity of the entire system. Due to this complexity, the network with the router is not very practical for fault tolerant systems having multiple nodes.
- a fault tolerant distributed microcontroller or computing system having a shared transducer apparatus 1 is shown.
- the system 1 is a triplex system or dual ring network that may be used, for example, in a brake control system.
- the system 1 includes nodes N1-N3, which are connected together via three bi-directional buses or links 2-4,12,13,21,23,31,32.
- the bi-directional links may be, for example, FIFOs, dual port memories, fast serial links, or the like.
- the nodes and buses are arranged as a ring or loop.
- each node is synchronised in time with each other node via time synchronisation links 48, as shown in FIG. 2.
- time synchronisation methods used in distributed computing and/or microcontroller systems that may be used in this application, for example, the internet network time protocol (NTP), scalar, vector or matrix causality approaches, and the like.
- a node is located at each brake actuator near the wheels of the vehicle, with one node located at a foot pedal. While the example shown in FIG. 1 have used three nodes in a ring configuration, it will be appreciated that a system embodying the invention may be expanded to contain more than three nodes, and/or the nodes may be connected in configurations other than ring, such as cross-link configurations, starred configurations, and the like, as discussed in more detail below with reference to FIG. 2.
- the links 2-4, and nodes N1-N3 are arranged to send data from each module node in clockwise and anti-clockwise directions around the ring, for example, from N1 to N3 via N2 and from N1 to N2 via N3, etc.
- the bi-directional links 2-4 may be, for example, FIFOs, dual port memories, fast serial links, or the like.
- the nodes and buses are arranged as a ring or loop. In such a configuration as this embodiment, each node microcontroller must have several inputs and outputs.
- a shared transceiver apparatus 44 of a microcontroller 42 having a single duplex link transceiver in a fault tolerant shared transceiver system 1 of FIG. 1 is shown according to an embodiment of the invention.
- the bi-directional links to N1 are shown in FIG. 2.
- each node N1-N3 has the fault tolerant shared transceiver apparatus and single link microcontroller system 40.
- the microcontroller 42 is time synchronised with the other microcontrollers in the network via link 48 as discussed above, and has input link 54 and output link 55.
- a memory 50 for example RAM and/or ROM and the like, is provided for the microcontroller 42, which may provide instructions and stored data for the microcontroller.
- the fault tolerant shared transceiver apparatus 44 comprises an input section 61, connected to microcontroller input link 54, and an output section 62, connected to microcontroller output link 55.
- the output section may comprise a number of buffers 58,59 in parallel including buffer 60 indicated in broken lines.
- the buffers 58,59 provide an output for signals from microcontroller 42 transmitted and bound, for example N2 via link 12, and N3 via link 13.
- the additional buffer 60 and output link 57 is shown to illustrate that the apparatus and system of the invention may be embodied by an apparatus having more than two output links, and/or a system having more than three nodes.
- the input section may comprise a switch 46 that is connected to microcontroller input link 54, and controlled by the microcontroller 42.
- the switch 46 may be selectively switched from incoming signals from, for example, N3 via link 31, or N2 via link 21.
- the additional input link 56 is shown to illustrate that the apparatus and system of the invention may be embodied by an apparatus having more than two input links, and/or a system having more than three nodes.
- the microcontroller 42 in each node N1-N3 is time synchronised together via link 48.
- Each microcontroller 42 is also configured and preset with the same data in memory 50, where each node is given particular time slots to transmit data signals to other nodes. Based on the predetermined time slots, to receive the transmitted signal at each time slot, the microcontroller 42 in each node N1-N3 switches switch 46 to the respective link that corresponds to the appropriate node that is scheduled in the time slot to transmit.
- the shared transceiver apparatus may be implemented on any type of microcontroller, including microcontrollers with two transceivers, to provide additional fault tolerant input and output links for the microcontroller.
Abstract
A shared transceiver apparatus (44) of a
microcontroller (42), and fault tolerant distributed
microcontroller system (1) having a shared transceiver
apparatus is disclosed for sharing a single duplex link
transceiver of a microcontroller in a fault tolerant
distributed microcontroller or computing system. The
shared transceiver apparatus (44) provides at least one
additional output (12,13,57) for the microcontroller output (56),
and at least one additional input (21,31,56) for the
microcontroller input (54).
Description
The present invention relates generally to a fault
tolerant shared transceiver apparatus and system. More
specifically, the invention relates to, for example,
sharing a single duplex link transceiver of a
microcontroller in a fault tolerant distributed
microcontroller or computing system.
Distributed computing or microcontroller systems are
used widely in many fields for high precision and safety
critical uses, for example, in automotive electronics
applications. Braking systems are an example of an
automotive electronic application that may utilize
distributed microcontroller systems. Currently,
distributed microcontroller systems are increasingly being
used in braking systems known as "brake-by-wire", in place
of mechanical and/or traditional hydraulic based braking
systems.
In such high precision and safety critical
applications, like the brake-by-wire system, it is
important that the systems are tolerant to faults in the
system due to, for example, faulty microcontrollers, and/or
faulty buses or links connecting the microcontrollers in
the system.
There are a number of systems and methods used. For
example, fault tolerant distributed computing or
microcontroller networks typically require a
microcontroller at each node. Some distributed
microcontroller networks comprise multiple nodes that are
connected together via bi-directional buses or links. In
such fault tolerant systems, microcontrollers having two
transceiver links that are capable of receiving two or more
inputs and transmitting two or more outputs are
implemented. However, these multiple transceiver
microcontrollers are relatively substantially more
expensive then less expensive single transceiver
microcontrollers. Additionally, microcontrollers having
one transceiver have less power dissipation, and have a
higher reliability due to a much simpler design than
microcontrollers with two transceivers.
A type of fault tolerant distributed microcontroller
network is designed without implementing the multiple
transceiver microcontrollers. However, this network
requires a separate router that is connected to each node
microcontroller, which increases complexity to the system.
The router itself requires at least one microcontroller,
and this also increases to the complexity of the entire
system. Due to this complexity, the network with the
router is not very practical for fault tolerant systems
having multiple nodes.
Therefore, there is a need in the art for a fault
tolerant distributed microcontroller or computing system
that shares a single duplex link transceiver of a
microcontroller.
In accordance with the present invention there is
provided a shared transceiver apparatus as claimed in claim 1,
and a fault tolerant distributed microcontroller system as
claimed in claim 5.
Embodiments of the invention will now be more fully
described, by way of example, with reference to the
drawings, of which:
Referring to FIG. 1, in an embodiment of the
invention, a fault tolerant distributed microcontroller or
computing system having a shared transducer apparatus 1 is
shown. In this embodiment, the system 1 is a triplex
system or dual ring network that may be used, for example,
in a brake control system. The system 1 includes nodes N1-N3,
which are connected together via three bi-directional
buses or links 2-4,12,13,21,23,31,32. The bi-directional
links may be, for example, FIFOs, dual port memories, fast serial
links, or the like. The nodes and buses are arranged as a ring
or loop. Additionally, each node is synchronised in time with
each other node via time synchronisation links 48, as shown in
FIG. 2. There are a wide variety of known time synchronisation
methods used in distributed computing and/or microcontroller
systems that may be used in this application, for example, the
internet network time protocol (NTP), scalar, vector or matrix
causality approaches, and the like.
In an example of a brake control system, a node is located
at each brake actuator near the wheels of the vehicle, with one
node located at a foot pedal. While the example shown in FIG. 1
have used three nodes in a ring configuration, it will be
appreciated that a system embodying the invention may be expanded
to contain more than three nodes, and/or the nodes may be
connected in configurations other than ring, such as cross-link
configurations, starred configurations, and the like, as
discussed in more detail below with reference to FIG. 2.
In operation the links 2-4, and nodes N1-N3 are arranged to
send data from each module node in clockwise and anti-clockwise
directions around the ring, for example, from N1 to N3 via N2 and
from N1 to N2 via N3, etc. The bi-directional links 2-4 may be,
for example, FIFOs, dual port memories, fast serial links, or the
like. The nodes and buses are arranged as a ring or loop. In
such a configuration as this embodiment, each node
microcontroller must have several inputs and outputs.
With reference to FIG. 2, a shared transceiver apparatus
44 of a microcontroller 42 having a single duplex link
transceiver in a fault tolerant shared transceiver system 1
of FIG. 1 is shown according to an embodiment of the
invention. For discussion purposes, the bi-directional
links to N1 are shown in FIG. 2. In the embodiment shown
in FIG. 1, each node N1-N3 has the fault tolerant shared
transceiver apparatus and single link microcontroller
system 40. The microcontroller 42 is time synchronised
with the other microcontrollers in the network via link 48
as discussed above, and has input link 54 and output link
55. A memory 50, for example RAM and/or ROM and the like,
is provided for the microcontroller 42, which may provide
instructions and stored data for the microcontroller.
The fault tolerant shared transceiver apparatus 44
comprises an input section 61, connected to microcontroller input
link 54, and an output section 62, connected to microcontroller
output link 55. The output section may comprise a number of
buffers 58,59 in parallel including buffer 60 indicated in broken
lines. The buffers 58,59 provide an output for signals from
microcontroller 42 transmitted and bound, for example N2 via link
12, and N3 via link 13. The additional buffer 60 and output link
57 is shown to illustrate that the apparatus and system of the
invention may be embodied by an apparatus having more than two
output links, and/or a system having more than three nodes.
The input section may comprise a switch 46 that is
connected to microcontroller input link 54, and controlled by the
microcontroller 42. The switch 46 may be selectively switched
from incoming signals from, for example, N3 via link 31, or N2
via link 21. The additional input link 56 is shown to illustrate
that the apparatus and system of the invention may be embodied by
an apparatus having more than two input links, and/or a system
having more than three nodes.
In operation, the microcontroller 42 in each node N1-N3 is
time synchronised together via link 48. Each microcontroller 42
is also configured and preset with the same data in memory 50,
where each node is given particular time slots to transmit data
signals to other nodes. Based on the predetermined time slots,
to receive the transmitted signal at each time slot, the
microcontroller 42 in each node N1-N3 switches switch 46 to the
respective link that corresponds to the appropriate node that is
scheduled in the time slot to transmit.
It will be appreciated that although the particular
embodiments of the invention have been described above,
various other modifications and improvements may be made by
a person skilled in the art without departing from the
scope of the present invention. For example, the shared
transceiver apparatus may be implemented on any type of
microcontroller, including microcontrollers with two
transceivers, to provide additional fault tolerant input
and output links for the microcontroller.
Claims (9)
- A shared transceiver apparatus for use in a fault tolerant distributed microcontroller system, comprising:an input section to provide at least one additional input to the microcontroller, the input section having a switch that switchably connects the microcontroller input to one of the at least one additional inputs, the switch being controlled by the microcontroller to selectively switch between the additional inputs to receive incoming signals.
- A shared transceiver apparatus as claimed in claim 1 further comprising an output section to provide at least one additional output to the microcontroller, the output section having a buffer for each additional output.
- A shared transceiver apparatus as claimed in claim 2 wherein the switch is controlled by the microcontroller in accordance to predetermined time slots preset in memory of the microcontroller.
- A shared transceiver apparatus as claimed in claim 2 or 3 wherein the additional inputs and additional outputs are configured to arranged to respectively transmit and receive signals from the microcontroller to at least two other microcontroller inputs and outputs respectively.
- A fault tolerant distributed microcontroller system comprising a plurality of distributed microcontroller nodes that are time synchronised, and a bi-directional link coupled to each of the plurality of nodes, each node is arranged to transmit signals to the link in a first and second direction, and to receive signals from the link in the first and second directions, wherein each node having a microcontroller with at least one input and output, and a shared transceiver apparatus comprising an input section to provide at least one additional input to the microcontroller, and an output section to provide at least one additional output to the microcontroller, and the input section having a switch that switchably connects the microcontroller input to one of the at least one additional inputs, the switch being controlled by the microcontroller to selectively switch between the additional inputs to receive incoming signals.
- A fault tolerant distributed microcontroller system as claimed in claim 4 wherein the switch in each shared transceiver apparatus at each node is controlled by the respective microcontroller at each node in accordance to predetermined time slots preset in memory of each microcontroller.
- A fault tolerant distributed microcontroller system as claimed in claim 5 or 6 wherein the output section having a buffer for each additional output
- A shared transceiver apparatus substantially as hereinbefore described and with reference to the drawings.
- A fault tolerant distributed microcontroller system substantially as hereinbefore described and with reference to the drawings.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0116042 | 2001-06-29 | ||
| GB0116042A GB2377035B (en) | 2001-06-29 | 2001-06-29 | A fault tolerant shared transceiver apparatus and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP1271866A2 true EP1271866A2 (en) | 2003-01-02 |
| EP1271866A3 EP1271866A3 (en) | 2004-05-19 |
Family
ID=9917694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP02004104A Withdrawn EP1271866A3 (en) | 2001-06-29 | 2002-02-25 | A fault tolerant shared transceiver apparatus and associated system |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20030002435A1 (en) |
| EP (1) | EP1271866A3 (en) |
| GB (1) | GB2377035B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006057112A1 (en) | 2006-12-05 | 2008-06-19 | Borg Warner Inc., Auburn Hills | Friction ring for clutch or synchromesh clutches has integral oil groove patterns with largest grooves in centre of ring |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8046835B2 (en) * | 2002-10-23 | 2011-10-25 | Frederick S. M. Herz | Distributed computer network security activity model SDI-SCAM |
| EP1692823A1 (en) * | 2003-11-19 | 2006-08-23 | Honeywell International Inc. | High integrity data propagation in a braided ring |
| US7668084B2 (en) * | 2006-09-29 | 2010-02-23 | Honeywell International Inc. | Systems and methods for fault-tolerant high integrity data propagation using a half-duplex braided ring network |
| US7889683B2 (en) * | 2006-11-03 | 2011-02-15 | Honeywell International Inc. | Non-destructive media access resolution for asynchronous traffic in a half-duplex braided-ring |
| US7912094B2 (en) * | 2006-12-13 | 2011-03-22 | Honeywell International Inc. | Self-checking pair-based master/follower clock synchronization |
| US7778159B2 (en) * | 2007-09-27 | 2010-08-17 | Honeywell International Inc. | High-integrity self-test in a network having a braided-ring topology |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4627070A (en) * | 1981-09-16 | 1986-12-02 | Fmc Corporation | Asynchronous data bus system |
| US4654846A (en) * | 1983-12-20 | 1987-03-31 | Rca Corporation | Spacecraft autonomous redundancy control |
| WO2000069117A2 (en) * | 1999-05-12 | 2000-11-16 | Infineon Technologies Ag | Communication system with a ring-shaped communication bus |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4654849B1 (en) * | 1984-08-31 | 1999-06-22 | Texas Instruments Inc | High speed concurrent testing of dynamic read/write memory array |
| US5862312A (en) * | 1995-10-24 | 1999-01-19 | Seachange Technology, Inc. | Loosely coupled mass storage computer cluster |
| US6330236B1 (en) * | 1998-06-11 | 2001-12-11 | Synchrodyne Networks, Inc. | Packet switching method with time-based routing |
| US6760328B1 (en) * | 1999-10-14 | 2004-07-06 | Synchrodyne Networks, Inc. | Scheduling with different time intervals |
| US6581121B1 (en) * | 2000-02-25 | 2003-06-17 | Telica, Inc. | Maintenance link system and method |
| US20020176359A1 (en) * | 2001-05-08 | 2002-11-28 | Sanja Durinovic-Johri | Apparatus for load balancing in routers of a network using overflow paths |
-
2001
- 2001-06-29 GB GB0116042A patent/GB2377035B/en not_active Expired - Fee Related
-
2002
- 2002-02-25 EP EP02004104A patent/EP1271866A3/en not_active Withdrawn
- 2002-05-13 US US10/144,364 patent/US20030002435A1/en not_active Abandoned
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4627070A (en) * | 1981-09-16 | 1986-12-02 | Fmc Corporation | Asynchronous data bus system |
| US4654846A (en) * | 1983-12-20 | 1987-03-31 | Rca Corporation | Spacecraft autonomous redundancy control |
| WO2000069117A2 (en) * | 1999-05-12 | 2000-11-16 | Infineon Technologies Ag | Communication system with a ring-shaped communication bus |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006057112A1 (en) | 2006-12-05 | 2008-06-19 | Borg Warner Inc., Auburn Hills | Friction ring for clutch or synchromesh clutches has integral oil groove patterns with largest grooves in centre of ring |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0116042D0 (en) | 2001-08-22 |
| US20030002435A1 (en) | 2003-01-02 |
| GB2377035B (en) | 2005-05-04 |
| EP1271866A3 (en) | 2004-05-19 |
| GB2377035A (en) | 2002-12-31 |
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