EP1412765A2

EP1412765A2 - Surface capacitance sensor system using buried stimulus electrode

Info

Publication number: EP1412765A2
Application number: EP02737174A
Authority: EP
Inventors: Thomas L. Andrade
Original assignee: Atrua Technologies Inc
Current assignee: Atrua Technologies Inc
Priority date: 2001-05-22
Filing date: 2002-05-22
Publication date: 2004-04-28
Also published as: JP2004528572A; JP4102672B2; TWI225932B; WO2002095439A2; WO2002095439A3; EP1412765A4; AU2002310124A1

Abstract

A surface capacitance sensor system is implemented as an array of sensor electrodes (21-23, 31-33, 41-43) near the surface of the integrated circuit and an array of stimulus electrodes below the sensor electrodes. Rows of stimulus electrodes are driven by sources (12, 13) while the voltages at the respective sensor electrodes are measured. Voltage measurements (16) at each sensor electrode allow the surface capacitance at each sensor electrode location to be determined. The capacitance data is used to determine the positions of target electrodes above the array surface as required in the location fingerprint artifacts.

Description

SURFACE CAPACITANCE SENSOR SYSTEM USING BURIED STIMULUS ELECTRODE

Inventor:

Thomas Lester Andrade

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to U.S. Provisional Patent Application Serial Number 60/292,858 filed on 5/22/2001, which is hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to improvements in capacitance sensor systems as are suitable to be fabricated with integrated circuit technology for use in sensors and sensing arrays that measure the position of fingerprint artifacts or other structures near the sensor surface.

BACKGROUND

Depending on the physical structure, the capacitance between a target electrode and a sense electrode varies inversely proportional to their relative distance, inversely proportional to their relative distance squared, or some functional dependence between inverse and inverse quadratic depending on the nature of the physical structure. The maximum distance at which a capacitance sensor system can detect target conductors in the vicinity of its sensor area is dependent on the minimum capacitance the system can resolve. If the capacitance of the sensor electrode relative to its ambient environment, its reference capacitance, is large compared to the capacitance between the target electrode and the sensor electrode, the capacitance sensor system sensitivity is significantly degraded. The size of the sensor electrode is dictated by the size of fingerprint artifacts, which is typically about the size of a 100 micrometer square. Being part of an integrated circuit whose vertical dimensions are small compared to 100 micrometers, the sensor electrode itself has significant capacitance to the substrate on which it mechanically rests.

For use in measuring the positions of fingerprint artifacts, a sensor array composed of an array of sensor electrodes was disclosed by Knapp in U.S. Patent No. 5,325,442. Each sense electrode is connected through a passive switch to array wiring that is the length of the array. The array wiring is connected to a charge sensing circuit to determine the capacitance. The capacitance sensitivity is degraded by the array wiring as the effective reference capacitance on each sensor electrode increased. Additionally, semiconductor switches are introduced into the sensor area where they may be damaged by mechanical contact with the target electrode, or may leak due to photocurrent when the sensor is operated in a high-light-level environment.

Additional coatings may be applied to the sensor surface to reduce the sensor's susceptibility to damage, but at an increase in the sensor to target electrode distance.

In U.S. Patent. No. 6,049,620, Dickinson et al. disclose a technique to measure the capacitance at each sensor electrode using a low value current source and additional active circuitry. A signal proportional to the total sensor capacitance is switched onto the array wiring after being passed through a source follower thereby isolating the wiring capacitance from the sensor electrode. With this technique the reference capacitance value is dominated by the sensor electrode capacitance and the capacitance of the circuitry connected to the sensor electrode itself.

In U.S. Patent No. 6,097,195, Ackland et al. disclose a method to reduce the sensor electrode capacitance by introducing a shield electrode between the sensor electrode and the grounded physical support structure. This reference capacitance cancellation technique is applied individually to each sensor electrode, resulting in a significant reduction in the reference capacitance and a proportional increase in the sensor capacitance sensitivity. A unity gain amplifier is connected between the sensor electrode and the shield electrode with one amplifier used per sensor electrode. The increase in sensor complexity increases the sensor cost and the risk of damage from the target structures.

Other capacitive sensor systems have been described which add circuitry to the sensor array as well as additional sensor electrodes. In U.S. Patent 6,114,862, Tartagni et al. disclose a capacitance sensor with active circuitry and special electrode configurations designed to improve the capacitive sensor sensitivity. The capacitance sensor use two electrodes at the sensor surface connected to opposite ends of an amplifier. Target structures such as fingers near either electrode modify the capacitance between electrodes. Both electrodes occupy the sensor surface, which increases the sensor cell size and cost.

RELEVANT LITERATURE

U.S. Patent Documents

Patent No. Date Inventor U.S. Class

4,210,899 7/1980 Swonger, et al. 340/146.3 E

4,435,056 10/1982 Tsikos 340/146.3 E

4,429,413 1/1984 Edwards 382/4

4,526,043 7/1985 Boie, et al. 73/862.04

5,195145 3/1993 Backus, et al. 382/4

5,325,442 6/1994 Knapp 382/4

5,434,446 7/1995 Hilton, et al. 257/503

5,778,089 7/1998 Borza 382/124

5,828,773 10/1998 Setlak, et al. 382/126

5,978,496 11/1999 Harkin 382/124

6,049,620 11/2000 Dickinson, et al. 382/124

6,055,324 4/2000 Fujieda 382/124

6,061,464 5/2000 Leger 382/124

6,097,195 8/2000 Ackland, et al. 324/719

6,114,862 9/2000 Tartagni, et al. 324/662

6,289,114 9/2001 Mainguet 324/124

6,317,508 11/2001 Kramer, et al. 382/124

6,365,888 4/2002 Von Basse, et al. 250/208.1 SUMMARY

The present invention provides a capacitance sensor system that overcomes the shortcomings of known technology as described above. The present invention eliminates the need for reference capacitance cancellation circuitry while reducing the sensor's power consumption and increasing its mechanical robustness.

In this invention each sensor cell has one electrode at or near the surface of the integrated circuit. Physically below the surface electrode is a buried stimulus electrode. The drive capacitance is the capacitance between the stimulus electrode and the sensor electrode. The capacitance from the sensor electrode to ground is the sensed capacitance. For an input time-varying voltage applied to the sense electrode, a measurement of the time-varying output voltage at the sense electrode is used to determine the sensed capacitance relative to the drive capacitance. This series arrangement of capacitors forms a capacitive voltage divider. If there are no structures proximate to the sensor electrode, the sense capacitance value is the reference value. Target structures, such as fingerprint artifacts, that are proximate to the sense electrode increase the sense capacitance by adding a target capacitance to the reference capacitance. The increased capacitance reduces the time- varying output voltage at the sense electrode, which in turn identifies the target structure's proximity.

An array of sensors cells is able to identify the location of target structures above each element of the array as required for the location of fingerprint artifacts. To implement an n x m dimensional array, the number of sources and voltmeters is reduced from one pair per cell using an appropriate switching matrix. An arrangement of n rows with n sources and m columns with m voltmeters provides a suitable tradeoff in circuit power, circuit complexity, and overall capacitance measurement rate. The array of electrodes, switches, time-varying sources, time- varying voltmeters and ancillary circuits are combined in the same integrated circuit to form the capacitance sensor system. In a sensor array, the time-varying voltmeter is shared by all sensor elements in the same column and the time-varying voltage source is shared by all sensor elements in the same row. The tim.e-varying input voltage source and time-varying voltmeter are implemented in CMOS technology. Cost reductions result from reductions in sensor circuit size as well as the use of CMOS technology that has not been modified for sensor applications. Mechanical robustness and resistance to optically induced currents are increased in the invention by removing all MOS transistor components from the sensor electrode area.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more thorough understanding of the features and advantages of the capacitive sensor, reference is now made to the detailed description of the invention in which: FIG. 1 illustrates an embodiment of the capacitive divider elements;

FIG. 2 is an embodiment of a single sensor cell showing the stimulus, sense, reference and target electrodes;

FIG. 3 is a schematic representation of an embodiment of the capacitive sensor illustrating a representative portion of the capacitive sensor system; FIG. 4 is an embodiment of a portion of a capacitive sensor system using individual row-stimulus, time-varying sources; and shared-column, time-varying voltmeters corresponding to the schematic representation of FIG. 3; and

FIG. 5 is another embodiment of a portion of a capacitive sensor system using individual row-stimulus, time-varying sources; and shared-column, time-varying voltmeters corresponding to the schematic representation of FIG. 3 in which the column switch matrix is external to the sensor array.

The figures are merely schematic and have not been drawn to any consistent scale. The same reference numbers are used throughout to represent the same or similar elements.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

FIG. 1 illustrates an embodiment of an elementary method for measuring the value of an unknown capacitance (1). For convenience of illustration, the sense capacitance (1) is shown with one connection to the reference potential (5). The connection (5) represents the reference potential for the time-varying voltage source (3) and for the time-varying voltmeter (4). The capacitance value, cl, of sense capacitor (1) may be determined relative to the drive capacitance value, c2 of drive capacitor (2) by connecting the capacitors as shown. Node (6) is a common node between the voltmeter (4) and the two capacitors, (1) and (2). For a known time- varying voltage v3 from the time-varying voltage source (3), the unknown capacitance (1) is determined by the simple formula cl equals the product of c2 and the calculated quantity (v3 - v4) / v4, in which v4 is the voltage measured by the time- varying voltmeter (4).

A physical implementation of the capacitive divider of FIG. 1 is illustrated in FIG. 2. The reference capacitance of value c3 is the capacitance between the sense electrode (10) and the reference electrode (8). The target capacitance of value c4 is the electrical capacitance between the sense electrode (10) and the target electrode (11). Sense capacitance value c2 is the sum of c3 and c4. The drive capacitor (2) of value c2 is the capacitance between the stimulus electrode (9) and the sense electrode (10). The time-varying voltage source (3) is connected between the drive electrode (9) and the reference electrode (8), which is shown connected to ground potential (5) without loss of generality. The target electrode (11) is also at the ground potential. The physical arrangement shown in FIG 2. is implemented as an integrated circuit capacitance sensor system with all electrodes except the target electrode (11) being planar and stacked nearly one on the other. The target electrode (11) is the unknown shaped electrode above the sense electrode (10). The sense electrode (10), node (6) of FIG. 1, serves as part of both drive and sense capacitors, (1) and (2). Both the time-varying voltage source (3) and the time-varying voltmeter (4) may be shared between multiple capacitance measuring sensor cells.

FIG. 3 shows a portion of the electrical schematic of embodiment of the invention. Nine identical sense electrodes in a 3 x 3 array are shown, (21), (22), (23), (31), (32), (33), (41), (42), and (43). Of course other and different sized arrays (larger and smaller) may be used. These sense electrodes are part of both the drive and the sense capacitors. The other terminal of the drive capacitor is the stimulus electrode. While the stimulus electrodes beneath the sensor electrodes are physically unique, all stimulus electrodes in the same row are electrically connected. Common nodes (14) and (17) are driven by sources, (13) and (12) respectively. To save power, only one source is active during capacitance measurement of a particular row of sensor cells. In FIG. 3 source (12) is active, driving node (17) with a time-varying voltage, while sources (13) are inactive or otherwise statically driven. FIG. 3 shows nine switches, (15) and (18), added to the portion of the sensor array. Each switch, (15) and (18), is connected to a wire oriented perpendicular to the direction of the commonly driven stimulus electrodes, (14) and (17). When node (17) is driven by a source (13), the switches (18) connected to sense electrodes (22), (32), and (42) are closed. All other switches (15) are open. The voltmeters (16) are connected to only one sensor electrode each. This perpendicular arrangement of drive nodes and voltmeter connections allows for a simultaneous measurement of the sensor capacitance along a row of sensor electrodes.

For the case of a common node (17) driven by source (12) and the sources (13) with fixed potential, three switches are closed (18) and six switches (15) are open. Sense electrodes (22), (32), and (42) are connected to their respective voltmeters (16). For the case of one target electrode (11) over sense electrode (32), the voltage on the voltmeter (16) connected to electrode (32) is lower than the voltage on the other voltmeters (16) connected to either sense electrodes (22) or (42). In this way both the presence of a target electrode at sense electrode (32) is detectable as well as a measurement of the capacitance between electrodes (11) and (32), and hence information about the distance between electrodes (11) and (32).

FIG. 4 shows the embodiment of the invention corresponding to the schematic of FIG. 3. The switches (15) and (18) are shown physically within the sensor electrode array area. Each switch is shown physically adjacent to a corresponding sensor electrode. All switches in the same column are connected to one voltmeter (16). Multiple target electrodes (11) or the complex shape of a single target electrode (11) are deduced by sequentially measuring all the sense capacitance values.

FIG. 5 shows another embodiment of the invention. All the switches, and hence all transistor devices, are located external to the sensor electrode array area.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best use the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims

W at is claimed is:

1. A capacitance sensor device comprising: a semiconductor integrated circuit; a sensor electrode array arranged in a two dimensional array of n rows and m columns; a stimulus electrode array arranged in a one dimensional array of n rows; a quantity of n time-varying voltage sources connected to n rows of stimulus electrodes; a quantity of m time-varying voltmeters; and a quantity of m blocks of n switches that allows the connection of one of the n sensor electrodes along a column to one time-varying voltmeter.

2. The sensor in claim 1, wherein no MOS devices within the integrated circuit are beneath or between any sensor or stimulus electrodes.

3. A capacitance sensor device comprising: an integrated circuit; a two-dimensional sensor electrode array having n rows x m columns of electrodes; a stimulus electrode array arranged in a one dimensional array of n rows; a plurality of n time-varying voltage sources connected to n rows of stimulus electrodes; a plurality of m time-varying voltmeters; and a plurality of m blocks of n switches that allows the connection of one of the n sensor electrodes along a column to one time-varying voltmeter.

4. The sensor in claim 3, wherein the device includes MOS devices within the integrated circuit and no MOS devices within the integrated circuit are beneath or between any sensor or stimulus electrodes.

5. A capacitive sensor device of the type having MOS circuit devices, sensor electrodes and stimulus electrodes, said capacitive sensor device characterized in that there are no MOS circuit devices beneath or between any sensor or stimulus electrode.