EP1459360A1 - Active matrix thin film transistor array backplane - Google Patents
Active matrix thin film transistor array backplaneInfo
- Publication number
- EP1459360A1 EP1459360A1 EP02786784A EP02786784A EP1459360A1 EP 1459360 A1 EP1459360 A1 EP 1459360A1 EP 02786784 A EP02786784 A EP 02786784A EP 02786784 A EP02786784 A EP 02786784A EP 1459360 A1 EP1459360 A1 EP 1459360A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- gate
- source
- drain
- backplane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133305—Flexible substrates, e.g. plastics, organic film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1334—Constructional arrangements; Manufacturing methods based on polymer dispersed liquid crystals, e.g. microencapsulated liquid crystals
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Definitions
- a method of fabricating a thin film transistor active matrix backplane comprises the steps of providing a polyimide substrate in a plasma enhanced chemical vapor deposition chamber; depositing a first passivation layer to passivate the substrate using plasma enhanced chemical vapor deposition; applying a gate material to the first passivation layer by e-beam evaporation; patterning the gate material using photolithographie techniques to form an array of gate electrodes; depositing a gate insulating layer over the gate electrodes and first passivation layer; depositing a semiconducting channel layer comprising amorphous silicon over the gate insulating layer using plasma enhanced chemical vapor deposition; depositing a contact layer comprising phosphorus doped amorphous silicon on the semiconducting channel layer using plasma enhanced chemical vapor deposition; depositing a source-drain layer on the contact layer; patterning an array of source electrodes, drain electrodes, lines and pads in the source-drain layer using photolithography, patterning an array of transistor islands on
- a method of making a polymer dispersed electronic display comprises the steps of providing an active matrix thin film transistor array backplane formed on a polyimide substrate; depositing a display medium on the active matrix thin film transistor array backplane; depositing a protective layer comprising indium tin oxide coated polyester over the display medium; and curing the display medium between the backplane and the protective layer.
- FIGURE 1 illustrates an electronic label suitable for implementing an illustrative embodiment of the present invention.
- FIGURES 2a and 2b illustrate an electronic label including a backplane of the present invention.
- FIGURE 2c shows an electronic label including an RFID layer and employing the backplane of the present invention according to another embodiment.
- FIGURE 6 is an overhead view of a single pixel region of a thin film transistor array backplane of the present invention.
- FIGURE 7 illustrates the sample after coating of the substrate with the passivation layers.
- FIGURE 8 illustrates the sample in a single pixel region after deposition of the gate material.
- FIGURE 16 is a detailed view of a portion of a second mask used to pattern the source and drain electrodes, lines and pads in the thin film transistor array backplane of the present invention.
- FIGURE 1 is a broad illustration of an electronic label suitable for implementing the thin-film transistor active matrix backplane of an illustrative embodiment of the invention.
- the electronic label may be employed in connection with an item, person, animal or location in accordance with the teachings of the present invention.
- the illustrated electronic label 16 is specifically employed in connection with an item 12.
- the electronic label 16 displays information, generally as human or machine readable indicia 14, in order to display information related to the item 12 or any other predefined or selected information.
- the electronic label 16 can be temporarily or permanently affixed, attached, secured or coupled to the item 12 according to known methods and techniques.
- a suitable conventional mechanical fastening system such as fasteners, loop and hook-type arrangements, stitches, adhesives, and molding, as well as other known fixation techniques, can be employed to permanently or temporarily attach the electronic label 16 to the item 12.
- the label can also be integrally formed with the item, or can be used as a stand alone label.
- the term label is intended to include a label, strip, tag or general display device that is sufficiently sized and configured for attachment to an animal, person, item, or location for displaying indicia.
- the label 16 is generally shown and described as being attached to an item, although those of ordinary skill will readily recognize that the label can also be attached to an animal, person or location.
- the label may also be a stand alone display that is not mounted to anything, such as business cards or trading cards.
- the label may comprise electronic paper writing for drawing, printing, copying or faxing.
- the substrate 32 may comprise plastic, PET, PEN, polyester, high temperature polymers or other suitable flexible material.
- the gate insulation layer is deposited at a temperature of between about 100° Celsius and about 250° Celsius and preferably about 150 ° Celsius, a pressure of between about 0.1 and about 1.0 Torr and preferably 0.5 Torr, and an rf power density of between about 0.01 and about 1.0 and preferably about 0.067 watts per centimeter squared.
- the argon plasma treatment step is 2 minutes at between 0.07 to 0.3, and preferably 0.022, watts per centimeter squared.
- the channel layer 50 may comprise p- Si:H or other suitable material.
- the source-drain electrodes 62, 63 may be developed for about sixty seconds in a 1 :1 AZ312 developer, rinsed in deionized water and then baked at about 1 15 °C for about twenty minutes.
- the unwanted source-drain material i.e., the aluminum and/or chromium
- the unwanted aluminum material is removed with a mixture of about 85% phosphoric acid, 5% deionized water, 5% acetic acid and 5% nitric acid.
- the sample may then be washed, for example, using deionized water, and subsequently hard-baked at 1 15 °C for about twenty minutes.
- the gases and flow rates for depositing the protective layer are SiH at about between 2 to 10 standard cubic centimeters/minute and preferably about 5 standard cubic centimeters/ minute, H 2 at about between 100 to 400 standard cubic centimeters/minute and preferably about 220 standard cubic centimeters/ minute , and NH 3 at about between 20 to 80 standard cubic centimeters/minute and preferably about 50 standard cubic centimeters/ minute.
- the protective layer is etched to remove unwanted material over the drain pads 84 of the thin-film transistor 30 to expose the active pixel areas, thus forming the final structure shown in Figure 5.
- the top surface is spin coated with an adhesive promoter, such as HMDS, followed by application of a photoresist layer, such as AZ5214 and spin coating at about 4000 revolutions per minute for about forty seconds.
- the sample may then be soft-baked in an oven at about 90 °C for about twenty minutes.
- Figure 29 illustrates a PDA 290 with a convex display that allows any information displayed to be more easily read.
- the backplane is a compliant, flexible structure that is not damaged when bent, allowing a display formed using the backplane to be conformable to a variety of surfaces and items.
- the flexible substrate makes possible efficient manufacturing methods, such as roll to roll processing and photoresist-free fabrication techniques that can lower overall manufacturing costs.
- the backplane is lightweight and stronger than prior thin-film transistors formed on glass substrates.
- the backplane provides high-resolution displays that are easily controlled and updated.
- the backplane and displays using the backplanes of the invention are rugged, conformable, robust resistant to failure, lightweight and non- breakable.
- the backplane is resistant to strain and performs substantially the same under compressive strain and when lying flat.
- the device is also stable to elevated temperature and humidity.
- the backplane fabricated on polyimide according to the present invention performs substantially identically to backplanes formed on glass substrates, while reducing cost, and providing a more lightweight and robust product.
- Flexible active matrix matrix TFT array backplanes were fabricated on 51 ⁇ m thick polyimide foil (Kapton® E) substrates, as described in the article by C. E. Forbes, A. Gelbman, C. Turner, H. Gleskova, and S. Wagner entitled “A Rugged Conformable Backplane Fabricated with an a-Si:H Array on a Polyimide Substrate,” SID '02 Digest, 33, 2000 (2002). This article is incorporated herein by reference.
- SiNx layers were processed as a free-standing substrate.
- the glass substrate was coated with SiNx (500nm) on the device side only using the same recipe.
- PECVD which the gasses SiH4, H2 and NH3 at 150 ° C, was used for the deposition. Recipes were optimized to minimize stresses in the substrate with the goal of achieving a flat and stress-balanced film after both SiNx depositions were complete. After the SiNx passivation steps, the glass and Kapton backplanes were processed identically.
- the completed backplane of Kapton was nearly flat with only a minor outward curvature of radius ⁇ 18cm.
- untreated virgin Kapton had an inward radius of curvature of ⁇ 14cm due to roll-to-roll processing by the manufacturer.
- the final curvature of the fabricated device is controlled by processing conditions that have been optimized for stress balance between the many layers of the device.
- a 3 in. x 3 in. piece of Kapton Polyimide from DuPont was carefully cleaned with Dl water in a Branson 3510 Ultrasonic Bath prior to being placed in a multi- chamber S900 PECVD manufactured by System Innovative Systems Engineering.
- the gate electrodes, lines and pads were made from a deposited bilayer of aluminum (1000 angstroms) and an overcoat of chromium (100 angstroms). These metals were deposited on the top surface of SiNx using a Denton E-beam Evaporator under high vacuum. After metal deposition, photolithography was used to pattern these structures. The top surface was first spin coated with HMDS, followed by AZ5214 photoresist and spin coating at 4000 rpm for 40 seconds. The sample was then soft- baked at 90 ° C for 20 minutes.
- the sampled was then moved to a chamber reserved for (n+)a-Si:H depositions, the reactor chamber was pumped out and the (n+)a-Si:H layer was deposited at a pressure of 0.5 Torr for 400 seconds using 0.018 W/cm , resulting in a film approximately 500 angstroms thick.
- the gasses and flow rates were SiH4 (44 sscm) and PH3 (6sscm).
- the exposure time was 71.5 seconds and the light fluence was 2.0 mW/cm.
- the electrodes were developed for 60 seconds in 1 :1 AZ512 develope ⁇ DI water, rinsed in Dl water and baked at 115° C for 20 minutes.
- the unwanted source-drain material was removed with a mixture of 85 ml phosphoric acid: 5ml Dl water: 5 ml acetic acid: 5 ml nitric acid.
- the sample was washed thoroughly with Dl water and hard baked at 115° C for 20 minutes.
- Etching conditions were 150 mbar, l ⁇ sccm CF4 and 0.12 w/cm 2 for a total 7 minutes in one minute intervals.
- the mask photoresist layer was removed using acetone in an ultrasonic cleaning bath.
- Etching conditions were 150 mbar, 16 seem CF4, and 0.12 w/cm for a total 42 minutes in two minute intervals.
- the remaining photoresist layer was removed using acetone in an ultrasonic cleaning bath.
- the electrical characteristics were measured using a HP 4155 A Semiconductor Analyzer with the substrates on a probe station inside a metal box to exclude light.
- the electrical characteristics were compared to the characteristics of a backplane having a glass substrate and formed under identical conditions. As shown in Table 1 , the thin-film transistor array formed on the Kapton substrate has substantially identical characteristics as the glass substrate. Table 1. Comparison of TFT characteristics between Kapton and glass substrates
Abstract
Description
Claims
Applications Claiming Priority (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US35058401P | 2001-11-21 | 2001-11-21 | |
US350584P | 2001-11-21 | ||
US33383801P | 2001-11-28 | 2001-11-28 | |
US333838P | 2001-11-28 | ||
US37413102P | 2002-04-19 | 2002-04-19 | |
US374131P | 2002-04-19 | ||
US38231402P | 2002-05-21 | 2002-05-21 | |
US382314P | 2002-05-21 | ||
US300514 | 2002-11-20 | ||
US10/300,514 US6885032B2 (en) | 2001-11-21 | 2002-11-20 | Display assembly having flexible transistors on a flexible substrate |
PCT/US2002/037737 WO2003046964A1 (en) | 2001-11-21 | 2002-11-21 | Active matrix thin film transistor array backplane |
Publications (2)
Publication Number | Publication Date |
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EP1459360A1 true EP1459360A1 (en) | 2004-09-22 |
EP1459360A4 EP1459360A4 (en) | 2005-09-14 |
Family
ID=27540858
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02786784A Withdrawn EP1459360A4 (en) | 2001-11-21 | 2002-11-21 | Active matrix thin film transistor array backplane |
Country Status (3)
Country | Link |
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EP (1) | EP1459360A4 (en) |
AU (1) | AU2002350253A1 (en) |
WO (1) | WO2003046964A1 (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0545640A (en) * | 1991-08-09 | 1993-02-26 | Ricoh Co Ltd | Liquid crystal display |
US5695594A (en) * | 1996-01-05 | 1997-12-09 | Raychem Corporation | Method of making a liquid crystal light valve |
US5729242A (en) * | 1996-05-08 | 1998-03-17 | Hughes Electronics | Dual PDLC-projection head-up display |
US5776803A (en) * | 1995-10-25 | 1998-07-07 | U.S. Philips Corporation | Manufacture of electronic devices comprising thin-film circuitry on a polymer substrate |
US5796121A (en) * | 1997-03-25 | 1998-08-18 | International Business Machines Corporation | Thin film transistors fabricated on plastic substrates |
DE10011433A1 (en) * | 1999-03-17 | 2000-10-19 | Motorola Inc | Display with aligned optical shutter cell and background light cell, which can be used with a touchscreen |
WO2000067110A1 (en) * | 1999-05-03 | 2000-11-09 | E Ink Corporation | Display unit for electronic shelf price label system |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5680185A (en) * | 1990-11-26 | 1997-10-21 | Seiko Epson Corporation | Polymer dispersed liquid crystal (PDLC) display apparatus |
US5641974A (en) * | 1995-06-06 | 1997-06-24 | Ois Optical Imaging Systems, Inc. | LCD with bus lines overlapped by pixel electrodes and photo-imageable insulating layer therebetween |
US5856858A (en) * | 1997-12-01 | 1999-01-05 | The Regents Of The University Of California | Plastic substrates for active matrix liquid crystal display incapable of withstanding processing temperature of over 200° C and method of fabrication |
-
2002
- 2002-11-21 WO PCT/US2002/037737 patent/WO2003046964A1/en not_active Application Discontinuation
- 2002-11-21 AU AU2002350253A patent/AU2002350253A1/en not_active Abandoned
- 2002-11-21 EP EP02786784A patent/EP1459360A4/en not_active Withdrawn
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0545640A (en) * | 1991-08-09 | 1993-02-26 | Ricoh Co Ltd | Liquid crystal display |
US5776803A (en) * | 1995-10-25 | 1998-07-07 | U.S. Philips Corporation | Manufacture of electronic devices comprising thin-film circuitry on a polymer substrate |
US5695594A (en) * | 1996-01-05 | 1997-12-09 | Raychem Corporation | Method of making a liquid crystal light valve |
US5729242A (en) * | 1996-05-08 | 1998-03-17 | Hughes Electronics | Dual PDLC-projection head-up display |
US5796121A (en) * | 1997-03-25 | 1998-08-18 | International Business Machines Corporation | Thin film transistors fabricated on plastic substrates |
DE10011433A1 (en) * | 1999-03-17 | 2000-10-19 | Motorola Inc | Display with aligned optical shutter cell and background light cell, which can be used with a touchscreen |
WO2000067110A1 (en) * | 1999-05-03 | 2000-11-09 | E Ink Corporation | Display unit for electronic shelf price label system |
Non-Patent Citations (2)
Title |
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PATENT ABSTRACTS OF JAPAN vol. 017, no. 338 (P-1564), 25 June 1993 (1993-06-25) -& JP 05 045640 A (RICOH CO LTD), 26 February 1993 (1993-02-26) * |
See also references of WO03046964A1 * |
Also Published As
Publication number | Publication date |
---|---|
AU2002350253A1 (en) | 2003-06-10 |
EP1459360A4 (en) | 2005-09-14 |
WO2003046964A1 (en) | 2003-06-05 |
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