EP1468362A2 - Procede et systeme pour enregistrer des donnees dans des memoires nv dans une architecture de controleur et produit programme informatique et support d'enregistrement lisible par un ordinateur correspondants - Google Patents

Procede et systeme pour enregistrer des donnees dans des memoires nv dans une architecture de controleur et produit programme informatique et support d'enregistrement lisible par un ordinateur correspondants

Info

Publication number
EP1468362A2
EP1468362A2 EP02790592A EP02790592A EP1468362A2 EP 1468362 A2 EP1468362 A2 EP 1468362A2 EP 02790592 A EP02790592 A EP 02790592A EP 02790592 A EP02790592 A EP 02790592A EP 1468362 A2 EP1468362 A2 EP 1468362A2
Authority
EP
European Patent Office
Prior art keywords
memory
address
controller
written
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02790592A
Other languages
German (de)
English (en)
Inventor
Wolfgang Buhr
Detlef Mueller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP1468362A2 publication Critical patent/EP1468362A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/355—Personalisation of cards for use
    • G06Q20/3552—Downloading or loading of personalisation data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/357—Cards having a plurality of specified features
    • G06Q20/3576—Multiple memory zones on card
    • G06Q20/35765—Access rights to memory zones

Definitions

  • the invention relates to a method and an arrangement for writing NV memories in a controller architecture as well as a corresponding computer program product and a corresponding computer-readable storage medium, which can be used in particular to write or program processes in NV code memories of microcontrollers. such as smart card controllers.
  • Smart cards In a smart card, data storage and arithmetic-logic units are integrated in a single chip with a size of a few square millimeters. Smart cards are used in particular as telephone cards, GSM SIM cards, in the banking sector and in healthcare. The smart card has thus become the ubiquitous computing platform. Smart cards are currently viewed primarily as a safe place for storing secret data and as a safe execution platform for cryptographic algorithms. The assumption of a relatively high level of security of the data and algorithms on the card is due to the hardware structure of the card and the external interfaces.
  • the card From the outside, the card presents itself as a "black box", the functionality of which can only be used via a well-defined hardware and software interface, and which can enforce certain security policies.
  • access to data can be linked to certain conditions.
  • Critical data such as secret keys from a public key procedure, can even be completely removed from outside access.
  • a smart card is able to execute algorithms without the execution of the individual operations being observed from the outside. The algorithms themselves can be protected on the card against changes and reading.
  • the smart card can be understood as an abstract data type that has a well-defined interface, a specified behavior and is able to ensure compliance with certain integrity conditions with regard to its condition.
  • the manufacturing and delivery process for chip cards is divided into the following phases:
  • each phase is carried out by a company that specializes in the respective job.
  • the complete memory must be freely accessible so that the manufacturer can carry out a correct final test.
  • the chip is only secured by a transport code after the final test. After that, access to the card memory is only possible for authorized parties who know the transport code. Theft of brand new semiconductors is therefore without consequences.
  • Authorized bodies can be personalizers or card issuers. No further security functions are required for embedding and printing. The companies concerned do not need to know the transport code.
  • the issuing body e.g. bank, telephone company, health insurance company, etc.
  • This process is called personalization.
  • Knowledge of the transport code is necessary for them.
  • Writing requires several write accesses to the memory interface register: writing the address register for page address and byte address, writing the data register and the control register.
  • the previous method for writing NV memories is very slow compared to code fetch / read, since depending on the type of access it requires two to five register accesses per written data word, while code fetch and MOVC reading in the fast code fetch cycle of the Processor expire.
  • the memory management unit which controls the mapping and the access rights of the code memory as a whole, has no influence when writing to the NV memory.
  • the memory can therefore only be written under the control of the operating system of the controller and is only possible for application software using special calls to system routines.
  • the invention is therefore based on the object of specifying a method, an arrangement and a corresponding computer program product and a corresponding computer-readable storage medium of the generic type, by means of which the disadvantages of the conventional procedures are avoided and by which it is possible to combine data in the shortest possible time Write NV memory without having to make any major changes to previously used procedures and ensure greater protection against programming errors.
  • a particular advantage of the method for writing NV memories in a controller architecture is that (a) defined data value (s) or (a) defined data word (s) at (a) defined destination address ( n) are written within the NV memory by writing the data value (s) or the data word (s) to the specified position of the cache page register of the NV memory and the page address pointer registers of the NV memory are updated.
  • An arrangement for writing to NV memories in a controller architecture is advantageously set up in such a way that it comprises a processor which is set up in such a way that writing to NV memories in a controller architecture can be carried out, with (a) defined ( r) Data value (s) or (a) defined data word (s) are (will) be written to (a) defined target address (s) within the NV memory by the data value (s) or the (The) data word (s) are (will) be written to the specified position of the cache page register of the NV memory and the page address pointer registers of the NV memory are updated.
  • a computer program product for describing NV memories in a controller architecture comprises a computer-readable storage medium on which a program is stored which enables a computer or smart card controller to be loaded after it has been loaded into the memory of the computer or the smart card controller to perform a description of NV memories in a controller architecture, with (a) defined data value (s) or (a) defined data word (s) at (a) defined destination address (es) within the NV -Memories are (will be) written by the data value (s) or data word (s) to the specified position of the cache- Page registers of the NV memory are (will) be written and the page address pointer registers of the NV memory are updated.
  • a computer-readable storage medium is advantageously used, on which a program is stored which enables a computer or smart card controller to enter the memory of the computer or the smart card controller has been loaded to write NV memories in a controller architecture, with (a) defined data value (s) or (a) defined data word (s) at (a) defined destination address (es) are written within the NV memory by writing the data value (s) or the data word (s) to the specified position of the cache page register of the NV memory and the page -Address- pointer register of the NV memory are updated.
  • the command set of the controller core is advantageously expanded by additional move code write instructions (MOVCWR instructions) to write to the NV memory.
  • MOVCWR instructions additional move code write instructions
  • the additional instructions of the controller core transfer the parameters for the address pointer and for the data value to be written or the data word to be written and corresponding control signals for a so-called memory management unit ( MMU) and activate NV memory interfaces. It proves to be advantageous that in the presence of a memory
  • MMU Management unit
  • the address processing for the MOVCWR instructions takes place in the same way as the processing of code fetches or MOVC instructions.
  • a preferred embodiment of the method according to the invention provides that if a memory management unit (MMU) of the controller is present, this MMU is expanded by a control signal path.
  • MMU memory management unit
  • the cache page register of the NV memory is deleted when changing to a new page address in a MOVCWR instruction.
  • Another advantage of the method according to the invention is that an unwanted programming of old page register contents under the wrong address is prevented.
  • the processor is part of a smart card controller and the arrangement is a smart card.
  • the method according to the invention offers several advantages over the writing of the cache page register, which was previously supported solely by the register interface of the NV memory.
  • Writing the NV memory with MOVCWR only requires one MOVCWR instruction per data word (byte) with transfer of the two parameters for the address pointer and the data word.
  • an "autoincrement" of the address pointer can be used as with MOVC reading.
  • This command call significantly accelerates the writing process compared to writing via the address / data register set of the NV memory.
  • the invention is explained in more detail below in an exemplary embodiment.
  • the method presented consists of expanding the command set of the controller with so-called MOVCWR (move code write) instructions which make it possible to write a defined data word (byte) to a defined destination address within an NV code memory.
  • MOVCWR move code write
  • the data word (byte) is written to the correct position of the cache page register of the respective NV memory and the page address pointer register of the memory is updated with the associated page address.
  • this MOVCWR writing to the cache page register takes place under full control of this MMU, so that it only addresses areas of the memory that are generally approved for this by the MMU. Special mapping of the code memory within the address area of the controller is taken into account.
  • Every change to a new page address for a MOVCWR instruction results in an immediate deletion of the cache page register of the NV memory in order to enable programming of data under the new page address and to prevent unwanted programming of old page register contents under the wrong address ,
  • the instruction set of the controller core is expanded by additional MOVCWR instructions in order to carry out the writing of NV memories in the manner according to the invention.
  • the additional MOVCWR instructions ensure that the parameters for the address pointer and the data value to be written are transferred and activate the corresponding control signals for MMU and memory interfaces.
  • a possibly existing MMU (memory management unit) of the controller is expanded by a corresponding control signal path, which generates the corresponding chip select signals for the memory interfaces when the MOVCWR instruction is executed.
  • the address processing for the MOVCWR instructions does not differ from the processing of code fetches or MOVC instructions.
  • the memory interfaces of the NV memories support this function with a corresponding write mode for the cache page registers and one Update function of the address register after every MOVCWR process.
  • a reset logic performs an address comparison between the old and new page address before each MOVCWR process and, if the address changes before the cache page register is written, triggers deletion of the old register content.

Abstract

L'invention concerne un procédé et un système pour enregistrer des données dans des mémoires NV dans une architecture de contrôleur, ainsi qu'un produit programme informatique et un support d'enregistrement lisible par un ordinateur correspondants, pouvant être utilisés en particulier pour accélérer des opérations d'écriture ou de programmation dans des mémoires à code NV de microcontrôleurs, comme par exemple des contrôleurs de cartes à puce. Le procédé selon l'invention consiste à étendre le jeu d'instructions du contrôleur à l'aide d'instructions MOVCWR (move code write) qui permettent d'enregistrer un élément de donnée défini (multiplet) à une adresse cible définie à l'intérieur des mémoires à code NV. Cet élément de donnée (multiplet) est enregistré à la position correcte du registre de pages cache de la mémoire NV respective et le registre de pointeur d'adresses de pages de la mémoire est mis à jour avec l'adresse de page appropriée. En présence d'une MMU (Memory Management Unit), cet enregistrement MOVCWR se fait dans le registre de pages cache, de même que la lecture MOVC ou la récupération de codes, sous le contrôle de cette MMU.
EP02790592A 2001-12-29 2002-12-12 Procede et systeme pour enregistrer des donnees dans des memoires nv dans une architecture de controleur et produit programme informatique et support d'enregistrement lisible par un ordinateur correspondants Withdrawn EP1468362A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10164422A DE10164422A1 (de) 2001-12-29 2001-12-29 Verfahren und Anordnung zum Beschreiben von NV-Memories in einer Controller-Architektur sowie ein entsprechendes Computerprogrammprodukt und ein entsprechendes computerlesbares Speichermedium
DE10164422 2001-12-29
PCT/IB2002/005481 WO2003060721A2 (fr) 2001-12-29 2002-12-12 Procede et systeme pour enregistrer des donnees dans des memoires nv dans une architecture de controleur et produit programme informatique et support d'enregistrement lisible par un ordinateur correspondants

Publications (1)

Publication Number Publication Date
EP1468362A2 true EP1468362A2 (fr) 2004-10-20

Family

ID=7711113

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02790592A Withdrawn EP1468362A2 (fr) 2001-12-29 2002-12-12 Procede et systeme pour enregistrer des donnees dans des memoires nv dans une architecture de controleur et produit programme informatique et support d'enregistrement lisible par un ordinateur correspondants

Country Status (7)

Country Link
US (1) US7409251B2 (fr)
EP (1) EP1468362A2 (fr)
JP (1) JP2005515542A (fr)
CN (1) CN1288566C (fr)
AU (1) AU2002367042A1 (fr)
DE (1) DE10164422A1 (fr)
WO (1) WO2003060721A2 (fr)

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US20070168292A1 (en) * 2004-12-21 2007-07-19 Fabrice Jogand-Coulomb Memory system with versatile content control
US20060242067A1 (en) * 2004-12-21 2006-10-26 Fabrice Jogand-Coulomb System for creating control structure for versatile content control
US8601283B2 (en) * 2004-12-21 2013-12-03 Sandisk Technologies Inc. Method for versatile content control with partitioning
US8051052B2 (en) * 2004-12-21 2011-11-01 Sandisk Technologies Inc. Method for creating control structure for versatile content control
US8504849B2 (en) 2004-12-21 2013-08-06 Sandisk Technologies Inc. Method for versatile content control
US20060242151A1 (en) * 2004-12-21 2006-10-26 Fabrice Jogand-Coulomb Control structure for versatile content control
US20060242066A1 (en) * 2004-12-21 2006-10-26 Fabrice Jogand-Coulomb Versatile content control with partitioning
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Also Published As

Publication number Publication date
CN1288566C (zh) 2006-12-06
US7409251B2 (en) 2008-08-05
AU2002367042A1 (en) 2003-07-30
WO2003060721A3 (fr) 2004-05-13
CN1610885A (zh) 2005-04-27
DE10164422A1 (de) 2003-07-17
WO2003060721A2 (fr) 2003-07-24
WO2003060721A8 (fr) 2004-09-10
JP2005515542A (ja) 2005-05-26
AU2002367042A8 (en) 2003-07-30
US20050209716A1 (en) 2005-09-22

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