EP1620880A1 - Semiconductor substrate and manufacturing method therefor - Google Patents

Semiconductor substrate and manufacturing method therefor

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Publication number
EP1620880A1
EP1620880A1 EP04730068A EP04730068A EP1620880A1 EP 1620880 A1 EP1620880 A1 EP 1620880A1 EP 04730068 A EP04730068 A EP 04730068A EP 04730068 A EP04730068 A EP 04730068A EP 1620880 A1 EP1620880 A1 EP 1620880A1
Authority
EP
European Patent Office
Prior art keywords
substrate
manufacturing
layer
ion
gallium arsenide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04730068A
Other languages
German (de)
French (fr)
Other versions
EP1620880A4 (en
Inventor
Takao Yonehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of EP1620880A1 publication Critical patent/EP1620880A1/en
Publication of EP1620880A4 publication Critical patent/EP1620880A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Definitions

  • the present invention relates to a semiconductor substrate and a manufacturing method therefor and, more particularly, to a semiconductor substrate which has a gallium arsenide layer and a manufacturing method therefor.
  • a device on a compound semiconductor substrate made of gallium arsenide and other materials has for example high performance, high speed and good light-emitting properties.
  • the compound semiconductor substrate is expensive and has low mechanical strength, and is difficult to manufacture a large-area substrate. Under these circumstances, attempts have been made to heteroepitaxially grow a compound semiconductor on a silicon substrate which is inexpensive, has a high mechanical strength, and can form a large-area substrate.
  • 3,257,624 discloses a method of obtaining a large-area semiconductor substrate by heteroepitaxially growing a compound semiconductor layer on a silicon substrate, implanting ions in the silicon substrate, bonding the silicon substrate to another substrate, heating the ion-implanted layer and causing it to collapse, and dividing the bonded substrate stack.
  • Such a method needs to relax mismatch between the lattice constant of silicon and that of the compound semiconductor to obtain good crystallinity, depending on the specifications of a required compound semiconductor substrate.
  • 2,877,800 discloses a method of obtaining a compound semiconductor substrate by growing a compound semiconductor layer on a porous silicon layer formed on a silicon substrate, bonding the silicon substrate to another substrate, cutting the porous silicon layer with a jet of a fluid, and dividing the bonded substrate stack.
  • the porous silicon layer between the silicon and the compound semiconductor relaxes mismatch between the lattice constant of silicon and that of the compound semiconductor to some degree to form a heteroepitaxial layer. It is difficult to eliminate the mismatch between the lattice constant of the porous silicon and that of the compound semiconductor, and thus the resultant compound semiconductor may have poor crystallinity.
  • the specifications of some required compound semiconductor devices may limit the range of applications of a compound semiconductor substrate formed by such a manu acturing method, and the compound semiconductor devices may not sufficiently exhibit their superiority.
  • the present invention has been made on the basis of the above-mentioned consideration, and has as its object to provide a method of manufacturing a semiconductor substrate which sufficiently exhibits its superiority as a compound semiconductor device and can ensure good economy.
  • a semiconductor substrate manufacturing method characterized by comprising a first step of implanting ions in a first substrate which has a gallium arsenide layer on a germanium member and forming an ion-implanted layer in the first substrate, a second step of bonding the first substrate to a second substrate to form a bonded substrate stack, and a third step of dividing the bonded substrate stack at the io -implanted layer.
  • the gallium arsenide layer is preferably formed by epitaxial growth.
  • the first step may comprise a step of forming a compound semiconductor layer on the gallium arsenide layer.
  • the ions preferably include one of hydrogen ions and ions of a rare gas.
  • the third step preferably comprises a step of dividing the bonded substrate stack at the ion-implanted layer by annealing the bonded substrate stack.
  • the third step preferably comprises a step of dividing the bonded substrate stack at the ion-implanted layer by a jet of a fluid or a static pressure.
  • the third step preferably comprises a step of dividing the bonded substrate stack at the ion-implanted layer by inserting a member in the ion-implanted layer.
  • the manufacturing method preferably further comprises a step of removing a part of the ion-implanted layer left on a part of the gallium arsenide layer, which has been transferred to the second substrate after the third step.
  • the manufacturing method preferably further comprises a step of planarizing a surface of the germanium member obtained by division in the division step and reusing the germanium member in the first step.
  • Fig. 1 is a view for explaining a semiconductor substrate manufacturing method according to a preferred embodiment of the present invention
  • Fig. 2 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention.
  • Fig. 3 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention
  • Fig. 4 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention
  • Fig. 5 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention
  • Fig. 6 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention.
  • Fig. 7 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention.
  • Figs. 1 to 7 are views for explaining a substrate manufacturing method according to the preferred embodiment of the present invention.
  • a germanium member 11 is prepared.
  • a gallium arsenide layer 12 is formed on the surface of the germanium member 11 by epitaxial growth. Since mismatch between the lattice constant of germanium and that of gallium arsenide is small, a gallium arsenide layer with good crystallinity can be formed on the germanium member 11. Epitaxial growth allows the gallium arsenide layer to have a uniform thickness.
  • hydrogen ions are implanted in the surface of the gallium arsenide layer 12 shown in Fig. 2.
  • An ion-implanted layer 13 is formed in the gallium arsenide layer 12, thereby forming a first substrate 10.
  • ions of a rare gas such as helium, neon, argon, krypton, xenon, or the like may be used alone or in combination in the implantation.
  • an insulating layer is formed on the surface of the gallium arsenide layer 12, prior to the ion implantation.
  • the ion-implanted layer 13 can be formed in at least one of the germanium member 11 and the gallium arsenide layer 12.
  • a second substrate 20 is bonded to the surface of the first substrate 10 to form a bonded substrate stack 30.
  • a silicon substrate or a substrate obtained by forming an insulating layer such as an Si0 2 layer on its surface can be adopted as the second substrate 20.
  • any other substrate such as an insulating substrate (e.g., a glass substrate) may be used as the second substrate 20.
  • the bonded substrate stack 30 is divided at the ion-implanted layer 13 into two substrates.
  • the ion-implanted layer 13 has highly concentrated microcavities , microbubbles , distortions, or defects, and is more fragile than the remaining portion of the bonded substrate stack 30.
  • This division can be performed by, for example, annealing the bonded substrate stack 30.
  • the division can be performed by, for example, a method of using a fluid.
  • a method of forming a jet of a fluid (liquid or gas) and injecting the jet to the separation layer 12, a method which utilizes the static pressure of a fluid, or the like may preferably be used.
  • a method using water as the fluid is called a water jet method.
  • the division can be performed by inserting a solid member such as a wedge into the separation layer 12.
  • an ion-implanted layer 13b left on a gallium arsenide layer 12b of the second substrate 20 is removed using an etchant or the like.
  • the gallium arsenide layer 12b is preferably be used as an etching stopper layer.
  • a hydrogen annealing step, polishing step, or the like may be performed as needed to planarize the second substrate.
  • a semiconductor substrate 40 shown in Fig. 7 is obtained.
  • the semiconductor substrate 40 shown in Fig. 7 has the thin gallium arsenide layer 12b on its surface.
  • the expression "thin gallium arsenide layer” is intended to mean a layer thinner than a general semiconductor substrate.
  • the thickness of the gallium arsenide layer 12b preferably falls within a range of 5 nm to 5 Aim.
  • Another compound semiconductor layer of AlGaAs, GaP, InP, InAs , or the like can be formed on the gallium arsenide layer 12b, depending on the specifications of the semiconductor device.
  • an ion-implanted layer 13a or the like left on the germanium member 11 is removed using an etchant or the like. Then, the hydrogen annealing step, polishing step, or the like may be performed to planarize the surface of the germanium member.
  • the planarized substrate can be reused as the germanium member 11 to be used in the step shown in Fig. 1. Repeated reuse of the germanium member 11 can greatly reduce the manufacturing cost of a semiconductor substrate.
  • the manufacturing method according to the present invention makes it possible to obtain a semiconductor substrate which has a gallium arsenide layer with a uniform thickness and good crystallinity. Also, the manufacturing method according to the present invention can greatly reduce the manufacturing cost of a semiconductor substrate with a gallium arsenide layer. Therefore, according to the present invention, there can be provided a method of manufacturing a semiconductor substrate which sufficiently exhibits its superiority as a compound semiconductor device and can ensure good economy.

Abstract

The first step of implanting ions in the first substrate which has a gallium arsenide layer on a germanium member and forming an ion-implanted layer in the first substrate, the second step of bonding the first substrate to the second substrate to form a bonded substrate stack, and the third step of dividing the bonded substrate stack at the ion-implanted layer are performed, thereby manufacturing a semiconductor substrate.

Description

DESCRIPTION SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD
THEREFOR
TECHNICAL FIELD
The present invention relates to a semiconductor substrate and a manufacturing method therefor and, more particularly, to a semiconductor substrate which has a gallium arsenide layer and a manufacturing method therefor.
BACKGROUND ART
A device on a compound semiconductor substrate made of gallium arsenide and other materials has for example high performance, high speed and good light-emitting properties. The compound semiconductor substrate, however, is expensive and has low mechanical strength, and is difficult to manufacture a large-area substrate. Under these circumstances, attempts have been made to heteroepitaxially grow a compound semiconductor on a silicon substrate which is inexpensive, has a high mechanical strength, and can form a large-area substrate. For example, Japanese Patent No. 3,257,624 discloses a method of obtaining a large-area semiconductor substrate by heteroepitaxially growing a compound semiconductor layer on a silicon substrate, implanting ions in the silicon substrate, bonding the silicon substrate to another substrate, heating the ion-implanted layer and causing it to collapse, and dividing the bonded substrate stack. Such a method needs to relax mismatch between the lattice constant of silicon and that of the compound semiconductor to obtain good crystallinity, depending on the specifications of a required compound semiconductor substrate. Japanese Patent No. 2,877,800 discloses a method of obtaining a compound semiconductor substrate by growing a compound semiconductor layer on a porous silicon layer formed on a silicon substrate, bonding the silicon substrate to another substrate, cutting the porous silicon layer with a jet of a fluid, and dividing the bonded substrate stack.
In the manufacturing method disclosed in Japanese Patent No. 2,877,800, the porous silicon layer between the silicon and the compound semiconductor relaxes mismatch between the lattice constant of silicon and that of the compound semiconductor to some degree to form a heteroepitaxial layer. It is difficult to eliminate the mismatch between the lattice constant of the porous silicon and that of the compound semiconductor, and thus the resultant compound semiconductor may have poor crystallinity. The specifications of some required compound semiconductor devices may limit the range of applications of a compound semiconductor substrate formed by such a manu acturing method, and the compound semiconductor devices may not sufficiently exhibit their superiority.
DISCLOSURE OF INVENTION The present invention has been made on the basis of the above-mentioned consideration, and has as its object to provide a method of manufacturing a semiconductor substrate which sufficiently exhibits its superiority as a compound semiconductor device and can ensure good economy.
According to the present invention, there is provided a semiconductor substrate manufacturing method, characterized by comprising a first step of implanting ions in a first substrate which has a gallium arsenide layer on a germanium member and forming an ion-implanted layer in the first substrate, a second step of bonding the first substrate to a second substrate to form a bonded substrate stack, and a third step of dividing the bonded substrate stack at the io -implanted layer.
According to a preferred embodiment of the present invention, the gallium arsenide layer is preferably formed by epitaxial growth. Also, the first step may comprise a step of forming a compound semiconductor layer on the gallium arsenide layer. According to a preferred embodiment of the present invention, the ions preferably include one of hydrogen ions and ions of a rare gas.
According to a preferred embodiment of the present invention, the third step preferably comprises a step of dividing the bonded substrate stack at the ion-implanted layer by annealing the bonded substrate stack.
According to a preferred embodiment of the present invention, the third step preferably comprises a step of dividing the bonded substrate stack at the ion-implanted layer by a jet of a fluid or a static pressure.
According to a preferred embodiment of the present invention, the third step preferably comprises a step of dividing the bonded substrate stack at the ion-implanted layer by inserting a member in the ion-implanted layer.
According to a preferred embodiment of the present invention, the manufacturing method preferably further comprises a step of removing a part of the ion-implanted layer left on a part of the gallium arsenide layer, which has been transferred to the second substrate after the third step. According to a preferred embodiment of the present invention, the manufacturing method preferably further comprises a step of planarizing a surface of the germanium member obtained by division in the division step and reusing the germanium member in the first step.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings , in which like reference characters designate the same or similar parts throughout the figures thereof . BRIEF DESCRIPTION OF DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Fig. 1 is a view for explaining a semiconductor substrate manufacturing method according to a preferred embodiment of the present invention;
Fig. 2 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention;
Fig. 3 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention; Fig. 4 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention; Fig. 5 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention;
Fig. 6 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention; and
Fig. 7 is a view for explaining the semiconductor substrate manufacturing method according to the preferred embodiment of the present invention;
BEST MODE FOR CARRYING OUT THE INVENTION A preferred embodiment of the present invention will be described with reference to the accompanying drawings . Figs. 1 to 7 are views for explaining a substrate manufacturing method according to the preferred embodiment of the present invention. In the step shown in Fig. 1, a germanium member 11 is prepared. Then, in the step shown in Fig. 2, a gallium arsenide layer 12 is formed on the surface of the germanium member 11 by epitaxial growth. Since mismatch between the lattice constant of germanium and that of gallium arsenide is small, a gallium arsenide layer with good crystallinity can be formed on the germanium member 11. Epitaxial growth allows the gallium arsenide layer to have a uniform thickness.
In the step shown in Fig. 3, hydrogen ions are implanted in the surface of the gallium arsenide layer 12 shown in Fig. 2. An ion-implanted layer 13 is formed in the gallium arsenide layer 12, thereby forming a first substrate 10. In addition to hydrogen ions, ions of a rare gas such as helium, neon, argon, krypton, xenon, or the like may be used alone or in combination in the implantation. Though not shown, an insulating layer is formed on the surface of the gallium arsenide layer 12, prior to the ion implantation. The ion-implanted layer 13 can be formed in at least one of the germanium member 11 and the gallium arsenide layer 12.
In the step shown in Fig. 4, a second substrate 20 is bonded to the surface of the first substrate 10 to form a bonded substrate stack 30. Typically, a silicon substrate or a substrate obtained by forming an insulating layer such as an Si02 layer on its surface can be adopted as the second substrate 20. Also any other substrate such as an insulating substrate (e.g., a glass substrate) may be used as the second substrate 20.
In the step shown in Fig. 5, the bonded substrate stack 30 is divided at the ion-implanted layer 13 into two substrates. The ion-implanted layer 13 has highly concentrated microcavities , microbubbles , distortions, or defects, and is more fragile than the remaining portion of the bonded substrate stack 30. This division can be performed by, for example, annealing the bonded substrate stack 30. Alternatively, the division can be performed by, for example, a method of using a fluid. As the method, a method of forming a jet of a fluid (liquid or gas) and injecting the jet to the separation layer 12, a method which utilizes the static pressure of a fluid, or the like may preferably be used. Out of jet injection methods, a method using water as the fluid is called a water jet method. Alternatively, the division can be performed by inserting a solid member such as a wedge into the separation layer 12.
In the step shown in Fig. 6, an ion-implanted layer 13b left on a gallium arsenide layer 12b of the second substrate 20 is removed using an etchant or the like. At this time, the gallium arsenide layer 12b is preferably be used as an etching stopper layer. Then, a hydrogen annealing step, polishing step, or the like may be performed as needed to planarize the second substrate.
With the above-mentioned operation, a semiconductor substrate 40 shown in Fig. 7 is obtained. The semiconductor substrate 40 shown in Fig. 7 has the thin gallium arsenide layer 12b on its surface. The expression "thin gallium arsenide layer" is intended to mean a layer thinner than a general semiconductor substrate. To exhibit the superiority as a semiconductor device, the thickness of the gallium arsenide layer 12b preferably falls within a range of 5 nm to 5 Aim. Another compound semiconductor layer of AlGaAs, GaP, InP, InAs , or the like can be formed on the gallium arsenide layer 12b, depending on the specifications of the semiconductor device.
After the division in the step shown in Fig. 5, an ion-implanted layer 13a or the like left on the germanium member 11 is removed using an etchant or the like. Then, the hydrogen annealing step, polishing step, or the like may be performed to planarize the surface of the germanium member. The planarized substrate can be reused as the germanium member 11 to be used in the step shown in Fig. 1. Repeated reuse of the germanium member 11 can greatly reduce the manufacturing cost of a semiconductor substrate.
As has been described above, the manufacturing method according to the present invention makes it possible to obtain a semiconductor substrate which has a gallium arsenide layer with a uniform thickness and good crystallinity. Also, the manufacturing method according to the present invention can greatly reduce the manufacturing cost of a semiconductor substrate with a gallium arsenide layer. Therefore, according to the present invention, there can be provided a method of manufacturing a semiconductor substrate which sufficiently exhibits its superiority as a compound semiconductor device and can ensure good economy.
As many apparently widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the claims .

Claims

1. A semiconductor substrate manufacturing method, comprising: a first step of implanting ions in a first substrate which has a gallium arsenide layer on a germanium member and forming an ion-implanted layer in the first substrate; a second step of bonding the first substrate to a second substrate to form a bonded substrate stack; and a third step of dividing the bonded substrate stack at the ion-implanted layer.
2. The manufacturing method according to claim 1 , wherein the gallium arsenide layer is formed by epitaxial growth.
3. The manufacturing method according to claim
1, wherein the first step comprises a step of forming a compound semiconductor layer on the gallium arsenide layer.
4. The manufacturing method according to claim 1, wherein the ions include one of hydrogen ions and ions of a rare gas .
5. The manufacturing method according to claim 1, wherein the third step comprises a step of dividing the bonded substrate stack at the ion-implanted layer by annealing the bonded substrate stack.
6. The manufacturing method according to claim 1, wherein the third step comprises a step of dividing the bonded substrate stack at the ion-implanted layer by a jet of a fluid or a static pressure.
7. The manufacturing method according to claim 1, wherein the third step comprises a step of dividing the bonded substrate stack at the ion-implanted layer by inserting a member in the ion-implanted layer.
8. The manufacturing method according to claim 1, further comprising a step of removing a part of the ion-implanted layer left on a part of the gallium arsenide layer, which has been transferred to the second substrate after the third step.
9. The manufacturing method according to claim 1, further comprising a step of planarizing a surface of the germanium member obtained by division in the division step and reusing the germanium member in the first step.
10. A semiconductor substrate which is manufactured by a manufacturing method as defined in claim 1.
EP04730068A 2003-05-07 2004-04-28 Semiconductor substrate and manufacturing method therefor Withdrawn EP1620880A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003128917A JP4532846B2 (en) 2003-05-07 2003-05-07 Manufacturing method of semiconductor substrate
PCT/JP2004/006178 WO2004100233A1 (en) 2003-05-07 2004-04-28 Semiconductor substrate and manufacturing method therefor

Publications (2)

Publication Number Publication Date
EP1620880A1 true EP1620880A1 (en) 2006-02-01
EP1620880A4 EP1620880A4 (en) 2008-08-06

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EP04730068A Withdrawn EP1620880A4 (en) 2003-05-07 2004-04-28 Semiconductor substrate and manufacturing method therefor

Country Status (6)

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EP (1) EP1620880A4 (en)
JP (1) JP4532846B2 (en)
KR (1) KR100725141B1 (en)
CN (2) CN101145509A (en)
TW (1) TWI259514B (en)
WO (1) WO2004100233A1 (en)

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Publication number Priority date Publication date Assignee Title
JP5128781B2 (en) * 2006-03-13 2013-01-23 信越化学工業株式会社 Manufacturing method of substrate for photoelectric conversion element
CN108231695A (en) * 2016-12-15 2018-06-29 上海新微技术研发中心有限公司 Composite substrate and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961312A2 (en) * 1998-05-15 1999-12-01 Canon Kabushiki Kaisha SOI Substrate formed by bonding
EP0994503A1 (en) * 1998-10-16 2000-04-19 Commissariat A L'energie Atomique Structure comprising a thin layer composed of material containing conductive and isolation regions and method for manufacturing the structure
US20020072130A1 (en) * 2000-08-16 2002-06-13 Zhi-Yuan Cheng Process for producing semiconductor article using graded expital growth

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794409A (en) * 1993-09-20 1995-04-07 Fujitsu Ltd Formation of iii-v compound semiconductor thin film
JP3879173B2 (en) * 1996-03-25 2007-02-07 住友電気工業株式会社 Compound semiconductor vapor deposition method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961312A2 (en) * 1998-05-15 1999-12-01 Canon Kabushiki Kaisha SOI Substrate formed by bonding
EP0994503A1 (en) * 1998-10-16 2000-04-19 Commissariat A L'energie Atomique Structure comprising a thin layer composed of material containing conductive and isolation regions and method for manufacturing the structure
US20020072130A1 (en) * 2000-08-16 2002-06-13 Zhi-Yuan Cheng Process for producing semiconductor article using graded expital growth

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of WO2004100233A1 *
VENKATASUBRAMANIAN R: "HIGH-QUALITY EUTECTIC-METAL-BONDED ALGAAS-GAAS THIN FILMS ON SI SUBSTRATES" APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, vol. 60, no. 7, 17 February 1992 (1992-02-17), pages 886-888, XP000290448 ISSN: 0003-6951 *

Also Published As

Publication number Publication date
JP2004335693A (en) 2004-11-25
KR20060005406A (en) 2006-01-17
WO2004100233A1 (en) 2004-11-18
CN100358104C (en) 2007-12-26
CN1698180A (en) 2005-11-16
JP4532846B2 (en) 2010-08-25
TW200425261A (en) 2004-11-16
CN101145509A (en) 2008-03-19
TWI259514B (en) 2006-08-01
KR100725141B1 (en) 2007-06-07
EP1620880A4 (en) 2008-08-06

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