EP1620880A4 - Semiconductor substrate and manufacturing method therefor - Google Patents

Semiconductor substrate and manufacturing method therefor

Info

Publication number
EP1620880A4
EP1620880A4 EP04730068A EP04730068A EP1620880A4 EP 1620880 A4 EP1620880 A4 EP 1620880A4 EP 04730068 A EP04730068 A EP 04730068A EP 04730068 A EP04730068 A EP 04730068A EP 1620880 A4 EP1620880 A4 EP 1620880A4
Authority
EP
European Patent Office
Prior art keywords
manufacturing
semiconductor substrate
method therefor
therefor
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04730068A
Other languages
German (de)
French (fr)
Other versions
EP1620880A1 (en
Inventor
Takao Yonehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of EP1620880A1 publication Critical patent/EP1620880A1/en
Publication of EP1620880A4 publication Critical patent/EP1620880A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
EP04730068A 2003-05-07 2004-04-28 Semiconductor substrate and manufacturing method therefor Withdrawn EP1620880A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003128917A JP4532846B2 (en) 2003-05-07 2003-05-07 Manufacturing method of semiconductor substrate
PCT/JP2004/006178 WO2004100233A1 (en) 2003-05-07 2004-04-28 Semiconductor substrate and manufacturing method therefor

Publications (2)

Publication Number Publication Date
EP1620880A1 EP1620880A1 (en) 2006-02-01
EP1620880A4 true EP1620880A4 (en) 2008-08-06

Family

ID=33432059

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04730068A Withdrawn EP1620880A4 (en) 2003-05-07 2004-04-28 Semiconductor substrate and manufacturing method therefor

Country Status (6)

Country Link
EP (1) EP1620880A4 (en)
JP (1) JP4532846B2 (en)
KR (1) KR100725141B1 (en)
CN (2) CN101145509A (en)
TW (1) TWI259514B (en)
WO (1) WO2004100233A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5128781B2 (en) * 2006-03-13 2013-01-23 信越化学工業株式会社 Manufacturing method of substrate for photoelectric conversion element
CN108231695A (en) * 2016-12-15 2018-06-29 上海新微技术研发中心有限公司 Composite substrate and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961312A2 (en) * 1998-05-15 1999-12-01 Canon Kabushiki Kaisha SOI Substrate formed by bonding
EP0994503A1 (en) * 1998-10-16 2000-04-19 Commissariat A L'energie Atomique Structure comprising a thin layer composed of material containing conductive and isolation regions and method for manufacturing the structure
US20020072130A1 (en) * 2000-08-16 2002-06-13 Zhi-Yuan Cheng Process for producing semiconductor article using graded expital growth

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794409A (en) * 1993-09-20 1995-04-07 Fujitsu Ltd Formation of iii-v compound semiconductor thin film
JP3879173B2 (en) * 1996-03-25 2007-02-07 住友電気工業株式会社 Compound semiconductor vapor deposition method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961312A2 (en) * 1998-05-15 1999-12-01 Canon Kabushiki Kaisha SOI Substrate formed by bonding
EP0994503A1 (en) * 1998-10-16 2000-04-19 Commissariat A L'energie Atomique Structure comprising a thin layer composed of material containing conductive and isolation regions and method for manufacturing the structure
US20020072130A1 (en) * 2000-08-16 2002-06-13 Zhi-Yuan Cheng Process for producing semiconductor article using graded expital growth

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of WO2004100233A1 *
VENKATASUBRAMANIAN R: "HIGH-QUALITY EUTECTIC-METAL-BONDED ALGAAS-GAAS THIN FILMS ON SI SUBSTRATES", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, vol. 60, no. 7, 17 February 1992 (1992-02-17), pages 886 - 888, XP000290448, ISSN: 0003-6951 *

Also Published As

Publication number Publication date
JP2004335693A (en) 2004-11-25
KR20060005406A (en) 2006-01-17
WO2004100233A1 (en) 2004-11-18
CN100358104C (en) 2007-12-26
CN1698180A (en) 2005-11-16
JP4532846B2 (en) 2010-08-25
TW200425261A (en) 2004-11-16
CN101145509A (en) 2008-03-19
TWI259514B (en) 2006-08-01
KR100725141B1 (en) 2007-06-07
EP1620880A1 (en) 2006-02-01

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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Effective date: 20050119

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DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): BE DE FR GB IT NL

A4 Supplementary search report drawn up and despatched

Effective date: 20080703

17Q First examination report despatched

Effective date: 20091218

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18W Application withdrawn

Effective date: 20100413