EP1625680A2 - Method for optimizing high frequency performance of via structures - Google Patents
Method for optimizing high frequency performance of via structuresInfo
- Publication number
- EP1625680A2 EP1625680A2 EP03816274A EP03816274A EP1625680A2 EP 1625680 A2 EP1625680 A2 EP 1625680A2 EP 03816274 A EP03816274 A EP 03816274A EP 03816274 A EP03816274 A EP 03816274A EP 1625680 A2 EP1625680 A2 EP 1625680A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- transmission line
- sections
- via structure
- uniform
- optimization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/20—Frequency-selective devices, e.g. filters
- H01P1/201—Filters for transverse electromagnetic waves
- H01P1/203—Strip line filters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/163—Monitoring a manufacturing process
Definitions
- This invention generally relates to a method for assuring enhanced signal integrity in various electronic components operating at higher frequencies, hi particular, the present invention relates to a method for optimizing via structures in such components. More particularly, the present invention relates to a method for optimizing via structures for the enhanced high frequency performance of printed circuit boards and backplanes.
- an interactive method of optimization for manipulating the physical characteristics ofa single or multiple vias within a PCB or backplane to enhance their high frequency performance involves subdividing the via into one or more of the following three different kinds of sections: a transmission line bend section, a non-uniform transmission line thru section, and a loaded non-uniform transmission line stub section.
- a transmission line bend section a transmission line bend section
- a non-uniform transmission line thru section a loaded non-uniform transmission line stub section.
- the PCB stackup should be designed so the stub section lengths (if any are present) are minimized.
- the transmission line bend sections may be converted into lumped element series impedances and shunt element admittances.
- the physical dimensions of the bend section components maybe adjusted until several second-level characteristics of the section's electrically equivalent sub-circuits are optimized. In the case ofa single via, such optimization of a transmission line bend section is generally equivalent to minimizing the magnitude of the lumped element series impedances and shunt element admittances.
- non-uniform stub transmission line sections may be converted into a series of discretized RLGC sub-circuits.
- the physical dimensions of the stub section components associated with each sub-circuit may be manipulated until the values of R, L, G, and C are optimized.
- optimization of a non-uniform stub transmission line section is generally equivalent to making the magnitudes of series R and series L as large as possible and the magnitudes of shunt G and shunt C as small as possible.
- the S-parameters of the via structure after optimization may be calculated to verify the optimization results.
- the present invention allows for constraints on the continued manipulation of the physical characteristics of the vias to avoid minute improvements in performance at exponentially greater and greater monetary costs.
- FIG. 1 is a pair of cross-sectional views ofa standard printed circuit board showing the individual internal layers and a corresponding view showing the internal connections between the layers including a plurality of vias;
- FIG. 2 is a pair of cross-sectional views of a printed circuit board as in Fig. 1 with prior art modifications to the via structures for the enhancement of signal integrity performance;
- FIG. 3 is a baseline cross-sectional view of a printed circuit board indicating the individual internal layers and a corresponding partial cross-sectional view showing microstrip and stripline transmission line cross sections for the upper three layers of such printed circuit board;
- FIG. 4 is a partial cross-sectional view of a printed circuit board showing the views of the single-ended stripline of Figure 3, as well as, the division of such stripline into identical length segments and its equivalent electrical circuit;
- FIG. 5 is a pair of cross-sectional views of a printed circuit board showing the individual internal layers and a corresponding view showing the internal connections between the layers including a via thru section with an adjacent return via, and the equivalent circuit for the plurality of vias;
- FIG. 6 is a pair of cross-sectional views as in Fig. 5 for a via thru section without an adjacent return via and it's equivalent circuit;
- FIG. 7 is a flowchart outlining the basic methodology of the present invention.
- the present invention is particularly concerned with a method for optimizing via structures for the enhanced high frequency performance of printed circuit boards and backplanes 10.
- Vias 12 degrade the signal integrity performance of printed circuit board interconnects because they attenuate and distort analog, radio frequency, and digital signals that propagate through them.
- the present invention may be used to optimize individual component structures that make up a via 12, a collection of vias 12, and even higher level interconnects such as printed circuit boards and backplane assemblies 10 containing vias 12, interconnected traces, and connectors.
- Fig. 1 shows a cross-section of a typical multi-layer printed circuit board 10 (PCB) with a plurality of vias 12.
- a multi-layer PCB 10 is a printed board that consists of two or more planar conductive layers (LI, L2, L3, etc.) separated by one or more rigid or flexible planar insulating dielectric layers bonded together and electrically interconnected. An electrical connection between two or more patterns on different conductive layers is known as a via 12.
- a buried via 14 is one that does not extend to the outer layers ofa PCB 10.
- a blind via 16 extends only to one outer layer. Blind and buried vias 14 and 16 are also known as interstitial vias.
- a plated through hole 18 (PTH) via extends through the entire PCB 10 (from the top outer layer to the bottom outer layer) and is capable of making electrical connection between conductive patterns on internal layers, external layers, or both.
- a via 12 regardless of its location, includes a number of components. At the least a via 12 includes a barrel 20 and one or more functional 22 or non-functional 24 pads. Where applicable, a via 12 may include a clearance region 26 (also called an anti-pad region) on those layers where the via 12 intersects that layer but must be electrically isolated from any conductive patterns located on such layer.
- a pad 22 or 24 is a localized conductive pattern that is electrically attached to the via 12. If the pad 22 is also electrically connected to a conductive pattern (i.e., a signal trace, a ground or voltage plane, or a passive device, etc.) then it is a functional pad 22.
- Fig. 2 shows two methods currently in use to improve the signal integrity performance ofa via 12. It is common practice to remove non-functional pads 24 as a way to enhance the signal integrity performance of the via 12. It is also common practice to remove the unused "stub" sections 28 of PTH vias 18 by backdrilling out the conductive portion of the via 12 that makes up the stub section 28.
- the method of the present invention involves subdividing the via 12 into one or more of the following three different kinds of sections: a transmission line bend section, a non-uniform transmission line thru section, and a loaded non-uniform transmission line stub section.
- a transmission line bend section may be converted into lumped element series impedances and shunt element admittances, which are monotonically related to the scalable S-parameters of the circuitry including the non-optimized via 12.
- the iterative steps used in the process may be based on a straightforward sequential convergence algorithm.
- the physical dimensions of the bend section components may be adjusted until several second-level characteristics of the section's electrically equivalent sub-circuit are optimized.
- Non-uniform transmission line thru sections and non-uniform stub transmission line sections may be converted into a series of discretized RLGC sub-circuits (see Figs. 4-6).
- the physical dimensions of the thru section components associated with each sub-circuit may be manipulated until the values of R, L, G, and C are optimized.
- a planar transmission line is a wave-guiding structure whose fundamental mode of propagation along the transmission line is essentially a transverse electromagnetic wave.
- Planar transmission lines suitable for transmission of high frequency or narrow pulse electrical signals have defined conductor and dielectric material dimensions and shapes that are uniform along their length. Transmission lines can be described by an equivalent electrical circuit composed of distributed resistance, inductance, conductance, and capacitance elements (i.e., an RLGC sub-circuit).
- a microstrip transmission line 32 configuration consists ofa conductor that is positioned over and parallel to a conductive plane with a dielectric therebetween.
- a stripline transmission line 34 configuration consists of a conductor that is positioned between and parallel to two conductive planes with a dielectric among them.
- a balanced transmission line 36 is a two- conductor transmission line that has distributed resistance, inductance, conductance, and capacitance elements equally distributed between its conductors.
- An unbalanced transmission line 38 is a transmission line that has distributed resistance, inductance, conductance, and capacitance elements not equally distributed between its conductors. Non-equal trace widths are one way to create an unbalanced transmission line 38. It is common practice to denote the signal trace layer as the reference layer for microstrip 32 and stripline 34 transmission line structures.
- the single ended microstrip, the balanced differential microstrip, and the unbalanced differential microstrip are located on layer LI, even though the conductive plane on L2 forms part of the transmission line structure.
- the single-ended stripline, balanced differential stripline, and unbalanced differential stripline are located on L3, even though the conductive planes on layers L2 and L4 also form part of the transmission line structure.
- rnicrostrips 32 and striplines 34 are uniform guided wave structures (e.g., their cross-sections do not change with distance along the line), they can be used to model the impact of signals propagating down the line through a series of identical lumped-element RLGC circuits 40.
- a transmission line is first divided into infinitesimally small increments, ⁇ Z.
- An electrically equivalent circuit 40 may be created based on the four physical phenomena all transverse electromagnetic wave mode transmission lines have in common.
- the series resistance, R is used to quantify the conversion of signal power into heat inside the conductive regions of the transmission line.
- the shunt conductance, G is used to quantify the conversion of signal power into heat inside the dielectric regions of the transmission line. Because transmission lines are guided wave structures, the bulk of the power contained in the propagating signal is in the electric and magnetic fields that exist in the dielectric regions surrounding the conductive portions of the transmission line.
- the capacitance, C is used to quantify the impact the transmission line has on the electric field. A similar relationship exists between inductance, L, and the magnetic field. Altering the size and shapes of the conductors and dielectric materials used to create the transmission line will alter the values of R, L, G, and C.
- the via 12 and its localized surroundings maybe divided into three different vertical regions: one or more bend regions, one or more stub regions, and one or more thru regions.
- the top and bottom surfaces that comprise these regions depend on the PCB stackup 10 and which layers incoming and outgoing planar transmission lines are routed on.
- a via bend section is that region ofa via 12 connected to a planar transmission line.
- a bend signifies that the direction of the currents associated with the signal must change directions. In other words, the signal currents flowing horizontally along the interconnect traces must now flow vertically through the via 12.
- the bend section consists of the vertical section of the via 12 located on the same layers used to create the signal trace transmission line structures. Because microstrip transmission lines 32 need two layers, a bend associated with a microstrip 32 encompasses at least two layers.
- a via stub section 28 is that portion of a via 12 which has one end that is not terminated.
- a via thru section or a via bend section cannot be part of a via stub section 28.
- a via thru section is that portion of the via 12 which is required in order to complete an electrical circuit between an incoming and outgoing signal transmission line but is not part of a bend section.
- the electric and magnetic fields associated with the signal passing through the via 12 often extend into the regions between the conductive layers beyond the anti-pad boundary 26.
- When optimizing a via 12 one must include these regions 26 if the electric and magnetic fields contain a significant percentage of the energy contained in the signal.
- the penetration distance is dependent on a number of factors including the size and shape of the pad 22 and 24 and anti- pad 26 regions and thickness of both the conductive and dielectric layers in the region of interest.
- the electric and magnetic fields generated by adjacent vias 12 can and do co- mingle. In those cases, the optimization ofa given via 12 may also require the optimization of adjacent vias 12.
- Fig. 5 depicts an example of the conversion of a two via structure 52 into discrete segments for optimization.
- two microstrip transmission lines 32 are connected to a plated thru hole (PTH) via 18.
- a buried via 14 is used to provide a direct current return path for the two microstrip lines 32.
- the buried via 14 is positioned very close to the PTH via 18 so the electromagnetic fields generated by the currents in the two vias 14 and 18 are coupled.
- the vertical distance between layers LI and L2 form a bend region.
- the vertical distance between layers Lll and L12 form a bend region.
- the remaining portion of the via 18, layers L2 through Lll, form the thru section.
- One can define an equivalent circuit 40 for the thru section by dividing up the total height into a chain of series RL segments 54 and shunt GC segments 56.
- the series R value can be computed from the resistance losses associated with the via segments defined in the region.
- the series inductance can be computed from the magnetic field generated by the propagating signal between layers L2 and L3.
- the shunt capacitance can be computed from the electric field generated by the propagating signal surrounding layer L3.
- the series impedance increases with the increasing separation between layers.
- the shunt admittance is dependent on how close the ground plane is to any non-functional pads.
- the shunt admittance of layer L6 is greater than the shunt admittance of layer L7.
- the thickness of the conductive planes also impacts the shunt admittance. A thicker conductive layer has a lower admittance. Moving the conductive planes away from non-functional pads 24, or removing a non-functional pad 24 increases the shunt admittance.
- the pad 22 and 24 and anti-pad 26 diameters must be adjusted as needed to compensate for differences in dielectric material thickness, conductor thickness, etc. If adjustments of the pad/anti-pad diameters do not provide sufficient degrees of freedom, then the dielectric layer heights may require adjustment.
- a given transmission line structure is not limited to the four RLGC values noted herein.
- the lumped element characteristic impedance of the transmission line structure can be calculated.
- the equivalent circuit 40 includes a series capacitance, C pp , that provides a return path for an AC displacement current.
- Fig. 7 provides a flowchart 70 of the present invention's methodology for optimizing the high frequency performance of via structures 12.
- the first step of the process 72 is to choose a parameter that may be calculated to evidence improvement in the printed circuit board's signal integrity by manipulating the physical characteristics of the vias 12.
- One such parameter is the S-parameter. Due to their inherent difficulty to calculate in an iterative process where equivalent electrical representations of physical parameters are being evaluated, the S- parameters are best represented in terms of series impedances, shunt element admittances, and series discretized RLGC sub-circuits, where the values of R, L, G, C and the admittances and impedances may be quickly calculated. These may be chosen as the second level parameters 74 to determine optimization.
- the via hi order to calculate the second level parameters, the via must be subdivided into one of several types of transmission line segments 76. These include transmission line bend sections, non-uniform transmission line thru sections, and loaded non-uniform transmission line stub sections, as necessary, to generate an electrical circuit equivalent to said at least one via structure. To ease the calculations and reduce reflective signal effects the stub section lengths of the vias should be minimized where possible 78.
- the transmission line segments may then be converted 80 into equivalent series impedances, shunt element admittances, and a series of discretized RLGC sub-circuits comprised of one or more resistors, R, inductors, L, conductors, G, and capacitors, C.
- the second level parameters for these equivalent circuits may be calculated as a baseline 82.
- the physical characteristics of the vias 12 are then manipulated in a first direction 84 (i.e., increase or decrease the size of the hole or change its shape).
- the second level parameters are then recalculated 86 to determine if their values are moving in a direction desired by the user.
Abstract
Description
Claims
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2003/006836 WO2004082180A2 (en) | 2003-03-06 | 2003-03-06 | Method for optimizing high frequency performance of via structures |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1625680A2 true EP1625680A2 (en) | 2006-02-15 |
EP1625680A4 EP1625680A4 (en) | 2009-04-08 |
Family
ID=32986322
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03816274A Withdrawn EP1625680A4 (en) | 2003-03-06 | 2003-03-06 | Method for optimizing high frequency performance of via structures |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1625680A4 (en) |
JP (1) | JP2006526883A (en) |
KR (1) | KR101041555B1 (en) |
CN (1) | CN1989503B (en) |
AU (1) | AU2003225687A1 (en) |
WO (1) | WO2004082180A2 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1916915A (en) | 2005-08-19 | 2007-02-21 | 鸿富锦精密工业(深圳)有限公司 | Method for improving resistance of via hole |
JP4834385B2 (en) * | 2005-11-22 | 2011-12-14 | 株式会社日立製作所 | Printed circuit board and electronic device |
CN101236078B (en) | 2007-02-02 | 2011-01-05 | 鸿富锦精密工业(深圳)有限公司 | Capacitance to via hole guide wire length checking system and method |
CN101373488B (en) * | 2007-08-21 | 2011-06-15 | 京元电子股份有限公司 | Stack designing system and method for printed circuit board |
JP4585587B2 (en) * | 2008-08-20 | 2010-11-24 | 株式会社東芝 | High frequency multilayer substrate and method for manufacturing high frequency multilayer substrate |
JP5582248B2 (en) | 2011-03-30 | 2014-09-03 | 日本電気株式会社 | Transmission system and backplane system construction method |
US9397418B2 (en) | 2011-03-30 | 2016-07-19 | Nec Corporation | Transmission system and method for constructing backplane system |
US9560742B2 (en) * | 2014-11-11 | 2017-01-31 | Alcatel Lucent | Backdrill reliability anchors |
CN107072056B (en) * | 2017-05-31 | 2019-09-27 | 郑州云海信息技术有限公司 | A kind of design method optimizing PCIE connector area signal quality |
CN112770482B (en) * | 2020-12-04 | 2023-11-28 | 深圳国人无线通信有限公司 | Printed board assembly and shielding structure |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020130737A1 (en) * | 1999-02-25 | 2002-09-19 | Hreish Emad B. | High frequency printed circuit board via |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0944549A (en) * | 1995-07-31 | 1997-02-14 | Mitsubishi Electric Corp | Circuit designing method and layout designing method |
JPH09274623A (en) * | 1996-04-08 | 1997-10-21 | Oki Electric Ind Co Ltd | Transmission line simulation system and transmission line simulation method using the same |
JPH1049568A (en) * | 1996-05-31 | 1998-02-20 | Sharp Corp | Circuit board designing method and recording medium |
JP4204150B2 (en) * | 1998-10-16 | 2009-01-07 | パナソニック株式会社 | Multilayer circuit board |
JP2000252716A (en) * | 1999-03-03 | 2000-09-14 | Sony Corp | Distributed constant filter, its manufacture and distributed constant filter printed circuit board |
JP3285010B2 (en) * | 1999-06-22 | 2002-05-27 | 日本電気株式会社 | Stub circuit, method of adjusting stub circuit, and oscillator |
JP3482958B2 (en) * | 2000-02-16 | 2004-01-06 | 株式会社村田製作所 | High frequency circuit device and communication device |
JP2001308547A (en) * | 2000-04-27 | 2001-11-02 | Sharp Corp | High-frequency multilayer circuit board |
JP4184590B2 (en) * | 2000-12-04 | 2008-11-19 | 松下電器産業株式会社 | Circuit board mounting cost evaluation method and apparatus |
JP4734723B2 (en) * | 2001-01-31 | 2011-07-27 | 凸版印刷株式会社 | Manufacturing method of multilayer wiring board using coaxial via hole |
US20020147575A1 (en) * | 2001-02-12 | 2002-10-10 | Bois Karl J. | Method and system for modeling dielectric losses in a transmission line |
US6512377B1 (en) * | 2001-06-29 | 2003-01-28 | Nortel Networks Limited | Method and apparatus for extraction of via parasitics |
US6891266B2 (en) * | 2002-02-14 | 2005-05-10 | Mia-Com | RF transition for an area array package |
-
2003
- 2003-03-06 EP EP03816274A patent/EP1625680A4/en not_active Withdrawn
- 2003-03-06 AU AU2003225687A patent/AU2003225687A1/en not_active Abandoned
- 2003-03-06 JP JP2004569398A patent/JP2006526883A/en active Pending
- 2003-03-06 KR KR1020057016653A patent/KR101041555B1/en active IP Right Grant
- 2003-03-06 WO PCT/US2003/006836 patent/WO2004082180A2/en active Search and Examination
- 2003-03-06 CN CN038260905A patent/CN1989503B/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020130737A1 (en) * | 1999-02-25 | 2002-09-19 | Hreish Emad B. | High frequency printed circuit board via |
Non-Patent Citations (2)
Title |
---|
PILLAI E ET AL: "DERIVATION OF EQUIVALENT CIRCUITS FOR VIA HOLES FROM FULL WAVE MODELS" ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 29, no. 11, 27 May 1993 (1993-05-27), pages 1026-1028, XP000372937 ISSN: 0013-5194 * |
See also references of WO2004082180A2 * |
Also Published As
Publication number | Publication date |
---|---|
AU2003225687A1 (en) | 2004-09-30 |
KR101041555B1 (en) | 2011-06-15 |
WO2004082180A3 (en) | 2006-12-28 |
EP1625680A4 (en) | 2009-04-08 |
WO2004082180A2 (en) | 2004-09-23 |
KR20060006776A (en) | 2006-01-19 |
JP2006526883A (en) | 2006-11-24 |
AU2003225687A8 (en) | 2004-09-30 |
CN1989503A (en) | 2007-06-27 |
CN1989503B (en) | 2010-08-04 |
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