EP2026209A3 - System and method for using a memory mapping function to map memory defects - Google Patents

System and method for using a memory mapping function to map memory defects Download PDF

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Publication number
EP2026209A3
EP2026209A3 EP08014500A EP08014500A EP2026209A3 EP 2026209 A3 EP2026209 A3 EP 2026209A3 EP 08014500 A EP08014500 A EP 08014500A EP 08014500 A EP08014500 A EP 08014500A EP 2026209 A3 EP2026209 A3 EP 2026209A3
Authority
EP
European Patent Office
Prior art keywords
memory
map
usable
defects
defective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP08014500A
Other languages
German (de)
French (fr)
Other versions
EP2026209B1 (en
EP2026209A2 (en
Inventor
Mukund P. Khatri
Forrest E. Norrod
Jimmy D. Pike
Michael Shepherd
Paul D. Stultz
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Dell Products LP
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Dell Products LP
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Filing date
Publication date
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Publication of EP2026209A2 publication Critical patent/EP2026209A2/en
Publication of EP2026209A3 publication Critical patent/EP2026209A3/en
Application granted granted Critical
Publication of EP2026209B1 publication Critical patent/EP2026209B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1417—Boot up procedures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7207—Details relating to flash memory management management of metadata or control data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0407—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals on power on
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

In accordance with the present disclosure, a system and method are herein disclosed for managing memory defects in an information handling system. More particularly, the present disclosure comprises a system and method for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which comprises information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective.
EP08014500.6A 2007-08-14 2008-08-14 System and method for using a memory mapping function to map memory defects Active EP2026209B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/838,687 US7694195B2 (en) 2007-08-14 2007-08-14 System and method for using a memory mapping function to map memory defects

Publications (3)

Publication Number Publication Date
EP2026209A2 EP2026209A2 (en) 2009-02-18
EP2026209A3 true EP2026209A3 (en) 2009-04-01
EP2026209B1 EP2026209B1 (en) 2016-07-20

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP08014500.6A Active EP2026209B1 (en) 2007-08-14 2008-08-14 System and method for using a memory mapping function to map memory defects

Country Status (5)

Country Link
US (2) US7694195B2 (en)
EP (1) EP2026209B1 (en)
CN (1) CN101369246B (en)
SG (1) SG150446A1 (en)
TW (1) TWI356303B (en)

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