EP2082478A2

EP2082478A2 - System and method for on-chip im3 reduction over a broad range of operating powers

Info

Publication number: EP2082478A2
Application number: EP07843972A
Authority: EP
Inventors: Vikram Bidare Krishnamurthy; Tanveer Kaur Khanijoun; Kyle Mark Hershberger
Original assignee: Hershberger Kyle Mark; Khanijoun Tanveer Kaur; Krishnamurthy Vikram Bidare
Current assignee: VT Silicon Inc
Priority date: 2006-10-06
Filing date: 2007-10-08
Publication date: 2009-07-29
Also published as: JP2010506514A; CN101589547A; WO2008043098A2; WO2008043098A3; EP2082478A4; KR20090084843A

Abstract

Sets of power amplifier branches are power combined within each amplifier stage and each set of branches are biased in different classes of operation by bias circuits possessing different impedance characteristics such that the fundamental frequency components present at the output are in-phase with one another and the IMD3 components are anti-phase over a range of power levels. The RF input signal is provided by the output of the previous stage, each stage being formed by power combining sets of power amplifier branches each separately biased so the fundamental components are additive, while the IM3 components cancel partially or completely. Using a feed forward control loop to monitor the input power and appropriately adjusting the bias currents and impedance characteristics of the bias circuits feeding the individual branches can provide additional IM3 reduction or cancellation over a large range of output powers.

Description

TITLE

System and Method for On-Chip IM3 Reduction Over a Broad Range of Operating Powers

CLAIM OF PRIORITY

[0001] This application claims priority to U.S. Provisional Application No. 60/850,146, filed on October 6, 2006, the entire disclosure of which is incorporated by reference herein.

FIELD OF THE INVENTION

[0002] This invention generally relates to radio frequency/microwave amplifiers for communication devices, and in particular, to a system and method for automatically reducing third order intermodulation product levels to reduce signal distortion and

maintain high data rates for communication systems over a wide range of frequencies.

BACKGROUND OF THE INVENTION

[0003] Amplifiers are used in all cell phones to amplify a modulated signal from a transceiver prior to passing the signal through the front end of the cell phone, which typically consists of passive components and a switch into an antenna where the signal is transmitted to a base station. Fig. 1 illustrates a high level topography of the circuits

contained in a prior art cell phone. Generally, a baseband integrated chip 1 provides a signal to a transceiver 2. The transceiver transmits an RF signal to a power amplifier 3, which outputs an RF signal to a front end module 4 and out into the atmosphere by an

antenna 5. AU of these components are housed within a typical cell phone 6.

[0004] Two important factors driving the design of RF/microwave power amplifier 3 are linearity and efficiency. As used herein, linearity refers to the device's ability to amplify without distortion, and efficiency refers to the device's ability to convert DC power to RF/microwave power with as little wasted energy as possible. In conventional power amplifier designs, improvement in one area typically causes degradation in the other. An RF/microwave amplifier has two regions of operation: linear and nonlinear. In the linear region, the input signal envelope is amplified and no distortion is present at the output. For large peak to peak input signal levels, the amplifier enters the non-linear region and the output signal becomes distorted.

[0005] Distortion in RF/microwave amplifiers is generally caused by amplitude clipping, phase variations as a function of signal amplitude, and intermodulation products. Amplitude clipping occurs when the peak to peak input signal envelope amplitude extends beyond the linear region of the amplifier. Phase variations with signal amplitude also result when the peak to peak input signal envelope amplitude extends beyond the linear region of the amplifier. Intermodulation distortion (IMD) occurs as a result of nonlinearities in the amplifier transfer function resulting in mixing products being generated at the sum and difference frequencies of the input signals.

[0006] The third order intermodulation product (IMD3) is of great interest since this product is very close to the carrier signal on the frequency spectrum. Being located so close to the carrier signal, IMD3 is very difficult to eliminate or even reduce and is often the limiting factor in the linearity of the RF/microwave amplifier. The output third-order intercept point (OIP3), also known as OTOI (Output Third Order Intercept), is defined as the intersection point between the extrapolated 1:1 slope of the fundamental output power and the extrapolated 3:1 slope of the third-order intermodulation products. If the extrapolations are done well within the linear region, the OIP3 (OTOI) becomes a useful specification for predicting the linearity of the power amplifier. Thus, the higher the OIP3 (OTOI) point, the more linear the power amplifier. As mentioned above, reducing the IMD of the power amplifier improves its linearity and thus improves the OIP3 (OTOI).

[0007] Referring to Figure 2, power amplifier 3 comprises one or more stages 7a, 7b . . .

7n connected in series by matching networks 8a, 8b, 8c . . . 8n that consist of a circuit topology of zero or more resistors, capacitors, and inductors. Each stage 7a, 7b . . . 7n consists of a number of branches 18a, 18b . . . 18n connected in parallel. Each branch 18 has of one or more unit cells 20 connected in parallel. A unit cell is composed of one or more transistors in a circuit topology of zero or more resistors, capacitors, and inductors.

[0008] Each power amplifier stage 7 is typically biased with a bias circuit (not shown) that provides the appropriate current or voltage for the branches to operate in a single class of operation. As used herein, a class of operation is determined by the percentage of an input sinusoidal signal during which the unit cells in each branch is on and conducting current. For example, in Class A operation, the branches are all biased such that they are on and conducting current for 360 degrees of the input sinusoid signal. In Class B, the branches are on and conducting for 180 degrees of the input signal. The near-Class B biasing condition is for the case where the branches are on and the conduction angle is close to but above 180 degrees. In Class AB, the branches are on and conducting typically at or around 270 degrees but may vary between 180 degrees and 360 degrees. The limits for each class of operation are not rigorously set and are used herein for purposes of general understanding of the operating condition of an amplifier. [0009] Several methods have been tried to improve the response of power amplifiers.

One method is to operate the RF/microwave amplifier at lower power levels to ensure that the device remains in the linear region. A drawback to this method is that when the device is operated at a lower power level it is operating less efficiently than it does at higher power levels.

[0010] The present invention seeks to improve the output response of RF/microwave power amplifiers by reducing IM3 levels and improving the OIP3 (OTOI) of the power amplifier. One solution to this problem is to reduce the distortion present in the linear and nonlinear region so that the operation of the amplifier can be extended into the nonlinear region where higher power levels are possible.

SUMMARY OF THE INVENTION

[0011] The present invention recognizes and addresses the foregoing considerations, and others, of prior art constructions and methods.

[0012] These and/or other objects are achieved in one preferred embodiment of a discrete amplifier for canceling at least one distortion component at the output of the discrete amplifier comprising a first stage having at least a first branch and a second branch in parallel with one another, wherein each of the first and second branches is formed of one or more transistor legs having one or more unit cells in parallel with one another and a second stage having at least a third branch and a fourth branch in parallel with one another, wherein each of the third and fourth branches is formed of one or more transistor legs having one or more unit cells in parallel with one another. The discrete amplifier further comprises a first biasing circuit having a first impedance and a first biasing level, the first biasing circuit being operatively connected to the first stage first branch for biasing the first branch into a first mode of operation, a second biasing circuit having a second impedance and a second biasing level, the second biasing circuit being operatively connected to the first stage second branch for biasing the second branch into a second mode of operation, a third biasing circuit having a third impedance and a third biasing level, the third biasing circuit being operatively connected to the second stage third branch for biasing the third branch into a third mode of operation, and a fourth biasing circuit having a fourth impedance and a fourth biasing level, the fourth biasing circuit being operatively connected to the second stage fourth branch for biasing the fourth branch into a fourth mode of operation. At least one of the first mode of operation and the second mode of operation, and the third mode of operation and the fourth mode of operation are chosen so that at least one distortion component is substantially canceled at a respective output of at least one of the first stage and the second stage.

[0013] In another embodiment, the first biasing circuit first impedance and first biasing level differs from the second biasing circuit second impedance and second biasing level. In other embodiments, the impedance of the first and second biasing circuits and a biasing level of the first and second branches are different, and the impedance of the third and fourth biasing circuits and a biasing level of the third and fourth branches is different and are chosen so as to maximize the cancellation of the at least one distortion component at the output of at least one of the first stage and the second stage of the discrete amplifier.

[0014] In yet other embodiments, the first, the second, the third and the fourth braches are formed on a single integrated circuit chip and the first biasing circuit, the second biasing circuit, the third biasing circuit and the fourth biasing circuit are physically located on the same single integrated circuit chip to minimize electrical parasitics so as to maximize the cancellation of the at least one distortion component. Other embodiments further comprise a sensing circuit that senses the input power to the discrete amplifier and causes at least one of the first, the second, the third and the fourth biasing circuits to adjust the operating mode of its respective branch by adjusting at least one of the bias circuit current and impedance so as to maximize the cancellation of the at least one distortion component.

[0015] In some embodiments the first mode, the second mode, the third mode and the fourth mode are chosen from one of Class A, Class B, Class C, and Class AB modes of operation, and the first, the second, the third and the fourth biasing circuits are adjusted to change the impedance of the respective biasing circuits to maximize the cancellation of the at least one distortion component.

[0016] In another embodiment, a circuit for canceling at least one distortion component at the output of the circuit comprises a power splitter having a first input port, a first output port, and a second output port, wherein a first signal is input on the power splitter first input port and is split into a second signal at the power splitter first output port and a third signal at the power splitter second output port, and a power combiner having a first input port, a second input port, and a first output port. A first amplifier has an input port coupled to the power splitter first output port, and an output port coupled to the power combiner first input port. A second amplifier is in parallel with the first amplifier, the second amplifier has an input port coupled to the power splitter second output port, and an output port coupled to the power combiner second input port. At least one biasing circuit is operatively connected with one of the first and the second amplifiers for biasing the one of the first and the second amplifiers in a different class of operation than the other of the first and the second amplifiers, and at least one control logic circuit senses the first signal and causes at least one of a size of the one of the first and the second amplifiers to change based on the first signal, and a magnitude of a biasing level of the one of the first and the second amplifiers to change based on the first signal. A fourth signal is output from the power combiner first output port having at least one distortion component reduced.

[0017] In other embodiments, a second biasing circuit is operatively connected to the other of the first and the second amplifiers for biasing the other of the first and the second amplifiers into a class of operation different than the one of the first and the second amplifiers so that the at least one distortion component is reduced in the fourth signal. In some embodiments, the at least one distortion component is a third harmonic of the first signal. In yet other embodiments the modes of operation are chosen from one of Class A, Class B, Class C, and Class AB modes of operation. In other embodiments the power splitter and the power combiner are quadrature hybrids.

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of the invention and, together with the description, serve to explain the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] A full and enabling disclosure of the present invention, including the best mode thereof directed to one of ordinary skill in the art, is set forth in the specification, which makes reference to the appended figures, in which:

[0020] FIG. 1 illustrates a schematic of a typical RF system in a prior art cell phone; [0021] FIG. 2 illustrates a schematic of a prior art multi-stage RF/microwave power amplifier for use in the system of FIG. 1;

[0022] FIG. 3 illustrates a schematic of power combined amplifiers in accordance with an embodiment of the present invention;

[0023] FIG. 4 illustrates the large-signal K3 curve versus bias level for the amplifiers in

FIG. 3.

[0024] FIG. 5 illustrates the dependence of OIP3 on the bias point of the amplifiers of

FIG. 3.

[0025] FIG. 6 illustrates the improvement in OIP3 seen when the bias point of the two amplifiers of FIG. 3 is chosen such that K3 is equal to -K3'.

[0026] FIG. 7 illustrates a schematic for a balanced amplifier with control loop in accordance with an embodiment of the present invention.

[0027] FIG. 8 shows the flowchart for control logic of FIG. 7.

[0028] FIG. 9 illustrates a schematic of power combined branches in one stage of a power amplifier in accordance with an embodiment of the present invention;

[0029] FIG. 10 illustrates a schematic of power combined branches in one stage of a power amplifier with control logic in accordance with an embodiment of the present invention; and

[0030] FIG. 11 illustrates a flowchart for the control logic of Fig. 10.

[0031] Repeat use of reference characters in the present specification and drawings is intended to represent same or analogous features or elements of the invention. DETAILED DESCRIPTION OF THE INVENTION

[0032] Reference will now be made in detail to presently preferred embodiments of the invention, one or more examples of which are illustrated in the accompanying drawings. Each example is provided by way of explanation of the invention, not limitation of the invention, hi fact, it will be apparent to those skilled in the art that modifications and variations can be made in the present invention without departing from the scope and spirit thereof. For instance, features illustrated or described as part of one embodiment may be used on another embodiment to yield a still further embodiment. Thus, it is intended that the present invention covers such modifications and variations as come within the scope of the appended claims and their equivalents.

[0033] The present invention seeks to reduce or significantly cancel the EVB levels in power amplifiers at one or both of the component level and the sub-component level of the amplifier. In a first embodiment shown in FIG. 3, a component level quadrature balanced amplifier topology generally consists of a pre- amplifier quadrature hybrid 110, an amplifier stage consisting of two amplifiers 114 and 116 in parallel and biased in different classes of operation, and a post-amplifier quadrature hybrid 112. The input, V_1n, consists of a sum of sinusoids at two different frequencies expressed as:

Vin = A Sm(W₁1) + Bs\n(w₂t)

[0034] The input signal V_1n is passed to quadrature hybrid 110 positioned before the amplifier stage. One example of a suitable quadrature hybrid is the SHY550 90 degree hybrid coupler manufactured by Mid- Atlantic RF Systems, Inc. The input is divided into two signals with the same frequency components, but with a fraction of the power of the input and where one, Vj, is shifted by π radians and the other signal, V_Q, is shifted by - π/2 radians resulting in a relative phase difference of 90 degrees:

Vi = sin(w₂/ - π)

-._r A . . . π, B . , . π.

VQ = — γ= * sin(vf/ ) + -η= * sin(w₂t )

V2 2 V2 2

[0035] These signals are then passed to amplifiers 114 and 116, respectively. One example of suitable amplifiers are Model EIC5359-8 10- Volt internally matched power FET manufactured by Excelics Semiconductor, Inc. The signal amplification performed by each amplifier can be modeled respectively using the following approximate equations:

VAX = K₁ * Vi + Ki * Vi² + Ki * Vi'

VΛ2 = Ki * VQ + KI * VQ² + Ki * VQ³

where K₁ represents the coefficients of the third-order voltage transfer function of amplifier 114, and K₁' represents the coefficients of the third-order voltage transfer function of amplifier 116. One important feature of this amplifier design is that the K₃ term in amplifier 114 and the K₃' term in amplifier 116 are equal and opposite. In addition to this condition, the phase of the fundamental frequency components are substantially equal resulting in maximum power combining of the fundamental components.

[0036] The following equations examine one set of IMD3 terms. The other IMD3 terms are similar in form and follow the same mathematical operations. - 3A²B r . ,

One IMS term from 114: Ki [sin²(w/) * sin(w₂?j

2_Λ/2

1

Using the identity: sin a = — (1 - cos(2«))

K, cos(2w/) * sin(w₂/)]

Using the identity cos(α) * sin(/?) = — sin(α + β) — sin(αr - β)

K, — sin(2w,t - w₂t)

One IM 3 term from 116: {w_xt) * cos(w₂/)j

1 cos² a = — (1 + cos(2α)) Using the identity 2

cos(αr) * cos(^) = — cos(α - β) + — cos(a + β) Using the identity 2 2

-3A²B

K₃' cos(w₂t) + — cos(2w,t - w₂t) + — cos(2w>_j/ + w₂t)

4_Λ/2

The outputs of the amplifiers are then passed to second hybrid 112, which is the same type as the first hybrid and is used to combine the RF signals present at the output of the two amplifiers into one RP output signal. One suitable example of a hybrid is the Model SHY550 90 degree hybrid coupler from Midatlantic RF Systems, Inc. Hybrid 112 has two inputs (ports 1 and 4) and two outputs (ports 2 and 3). The "top" output port, port 2, consists of the addition of a signal from port 1 with a fraction of the power and shifted by π radians and a signal from port 4 with a fraction of the power and shifted by π/2 radians. The "bottom" output port, port 3, consists of the addition of a signal from

port 4 with half the power and shifted by π radians and a signal from port 1 with half the

power and shifted by π/2 radians. The bottom output port is taken to be the output of the device and, under ideal conditions, the IMD3 products will be substantially removed from the frequency spectrum and the fundamentals still remain. The following equations show what happens to the EV1D3 terms present at the "bottom" output port, VO2.

[0038] For the one set of IMD3 terms that was derived above, we obtain the following:

Vθ2 = K, )

3A²B

+ K₃' cos(w₂t) + — COs(Iw₁U - w₂t) +— cos(2w_jt + w₂t)

8

π , sin(α ) = - cos a

Using the identity, 2

cos(2w_jt + w₂t) cos(2w_xt — w₂t)

cos(2w>/ + w₂t)

As can be seen above, when K₃ = -K₃' this set of IMD3 terms will cancel. [0039] Similarly all of the other IMD3 terms will cancel as well which leads to an

improvement in OIP3. hi particular, the reduction in IMD3 levels will move the intersection point between the extrapolated 1 : 1 slope of the fundamental output power

and the extrapolated 3:1 slope of the third-order intermodulation products to a higher power resulting in a higher 0EP3 value. Looking at the first order terms present in the amplifiers,

1st order term from amplifier 114:

- A . . B . .

Kx

1st order term from amplifier 116: V2 V 2

it can be seen that the output of quadrature hybrid 112 due to these terms is as follows:

This term reduces to:

If the magnitude and sign of K₁ are substantially equal to those of K₁', then the fundamental term will be present at the output of quadrature hybrid 112. Having the magnitude and sign of K₁ substantially equal to those of Ki' also ensures that the phases of the fundamental components for both amplifiers are equal.

[0040] Figure 4 shows the dependence of K₃ on the bias level of the amplifier. For

example, in the class AB mode of operation an amplifier has a K₃ equal to -α. hi order for the second amplifier in the parallel configuration to achieve a K₃' equal to α, the bias level for this amplifier must be changed. As the bias level is dropped, the K₃' term crosses the zero axis and becomes positive and reaches α as the amplifier approaches the class B mode of operation. By choosing bias points from this graph where K₃ is substantially equal to -K₃', the IMD3 components present at the output will be greatly reduced if not cancelled completely.

[0041] In yet another embodiment, the phase of K₃ can be changed by operating the amplifier in either the gain compression mode or the gain expansion mode. In the gain compression mode, the gain of the amplifier decreases with increasing input power whereas in the gain expansion mode, the amplifier gain increases with increasing input power. The output power at the fundamental frequency can be modeled using the following terms: Ki * A + K₃ * A³ + K₅ * A⁵ where A is the amplitude of the input voltage signal and the K terms represent the Taylor series expansion coefficients that describe the amplifier's output voltage to input voltage transfer characteristics. The even order K terms do not contribute to the IMD3 components and hence have not been included in the equations. For gain expansion, the K₃ and K₅ terms are positive provided Ki is positive and for gain compression, the K₃ and K₅ terms are negative. The third order IMD3 components for a two tone excitation also contain the K₃ and K₅ terms. This implies that the IMD3 components are in phase during gain expansion and 180 degrees out of phase with respect to the fundamental for gain compression. In RF amplifiers, this can be achieved by adjusting the biasing of the amplifier by varying the bias levels and/or using a biasing circuit block with specific input impedance values.

[0042] To ensure that the magnitudes of the K₃ terms are substantially equal in amplifiers

114 and 116, the correct size must be chosen for each amplifier. The size of the amplifier is directly related to how much power the amplifier can produce. The amplifier itself is made of many single transistors connected in parallel. Each individual transistor has a standard size depending on the fabrication process. Each transistor also contributes a portion of the total output power when the transistors are connected in parallel. As the number of transistors connected in parallel increases, so does the total output power provided by the amplifier. Therefore, size, in this case, refers to the number of transistors multiplied by the amount of active area for each transistor.

When designing an amplifier for use in the present invention it is important to know how much output power is needed so that the appropriate number of parallel transistors can be used. This total number of transistors then sets the size of the amplifier. However, two amplifiers of the same size biased at different points will generate different IMD3 levels. For example, an amplifier of a certain size biased in the class AB mode of operation will generate significantly less IMD3 terms than an amplifier of the same size biased in the near-class B mode of operation at the same input power level. Thus the near-class B mode amplifier must be sized so that its IMD3 magnitudes are substantially equal to the IMD3 magnitudes of the class AB mode amplifier at the same input power levels. One method for determining the size is by testing a number of near-class B mode amplifiers of differing sizes for the appropriate input power levels to determine the appropriate IMD3 magnitudes. That is, as the IMD3 magnitudes of the two parallel amplifiers diverge, the improvement in OIP3 seen at the output of the output quadrature hybrid 112 will not be as great had the IMD3 levels been substantially equal in magnitude and opposite in phase. Moreover, the IMD3 magnitudes of amplifiers 114 and 116 may be substantially equal at one power level, but unequal at another. [0044] As shown in Figure 7, one method of overcoming this problem is by using a correction signal that is generated by monitoring the RF input signal at hybrid 110 to control the size and biasing level of amplifier 116. That is, the RF input signal Vj_n is sampled and fed into a control logic block 118 that generates a digital word or correction signal by comparing input power level Vj_n with levels stored in a look-up table, which are associated with the appropriate size and bias level for near-class B amplifier 116. The correction signal controls the size of near-class B amplifier 116 by controlling the number of parallel transistors that are active in the near-class B amplifier by turning on and off certain portions of the near-class B amplifier.

[0045] More specifically, if control logic 118 determines that certain portions of the near- class B amplifier should be turned off, then some of the transistors in the near-class B amplifier are shut off by reducing their bias level to zero. If, on the other hand, control logic 118 determines that certain portions of the near-class B amplifier should be turned on, then some transistors that had their bias level at zero will be raised to the near-class B level. Bias control logic 118 is located in the bias circuitry for near-class B amplifier 116. As the near-class B amplifier decreases in size, so does its IMD3 components. Likewise, as the near-class B amplifier increases in size, its resultant IMD3 components increase as well. As a result of the size adjustment capability, it possible to see OIP3 improvement across a wide range of input power levels.

[0046] Figure 8 illustrates the steps for the control logic to handle changes made to the near-class B amplifier. The input power level is first sensed at step 120, and the information is used to decide what changes should be made to the near-class B amplifier at step 124. At step 126 and 128, a decision will be made whether to increase or decrease the size of the amplifier and to increase or decrease the bias of the amplifier, respectively, to enhance IMD3 cancellation. Once a decision is made at steps 126 and 128, the appropriate changes are made at step 130 to the near-class B amplifier to make the magnitudes of the IMD3 components of the two amplifiers substantially equal, the phases of the IMD3 components 180 degrees out of phase with respect to one another, and the phases of the fundamentals equal.

[0047] One example of the effect of biasing in the proposed topology will next be described by the experimental results obtained using commercial off the shelf components at 5.7 GHz. Figure 5 shows the dependence of OIP3 on biasing. Figure 6 shows the improvement in OIP3 seen when the bias point is chosen such that K3 is substantially equal to -K3'. Two experiments were run both using the proposed topology and amplifiers of the same size, the EIC5359-8 10- Volt internally matched power FET from Excelics Semiconductor, Inc. The SHY550 90 degree hybrid coupler from Midatlantic RF Systems, Inc. was chosen for both the input hybrid and the output hybrid. In one case both amplifiers were biased at the same level in the class AB mode of operation and are denoted by Class A&A in Figure 5. At this bias point, the magnitudes of the IMD3 components are substantially equal, but the IMD3 components are in-phase with one another so no cancellation or reduction of IMD3 components occurs.

[0048] In the second case, one amplifier was biased in the class AB mode of operation as above while the other was biased in the near-class B mode of operation. With each amplifier in a different mode of operation, the IMD3 components are 180 degrees out of phase with respect to one another, but their magnitudes are substantially equal over a short input power range. This experiment is denoted by Class A&B in Figure 5. Thus, with the two amplifiers biased at different classes there is an improvement in 0IP3 over a small range of input power levels. In relation to the mathematical derivations, this experimental observation is a result of the dependence of the K3 terms with input power.

[0049] Figure 6 further illustrates the improvement shown in Figure 5 by illustrating that for a small range of input power levels there is improvement in OIP3 of up to 4dB. The OIP3 improvement would be over a wider power range had the experiment incorporated control loop 118 shown in Figure 7. Therefore, while an improvement can be obtained by choosing amplifiers of similar size, variable sizing and biasing of the near-class B amplifier will result in 0EP3 improvement over a broad power range. Thus, by adjusting the size and/or bias level of the near-class B amplifier, its IMD3 magnitudes could be adjusted to better match the IMD3 magnitudes of the class AB amplifier over a wide range of input powers resulting in an improvement in 0EP3 over a wider input power range.

[0050] In yet another embodiment of the present invention, EVI3 levels can be significantly reduced or canceled at the sub-component level. More particularly, the IM3 levels at each stage 7_a, 7_b . . . 7_n of power amplifier 3 may be significantly reduced or canceled by biasing two sets of branches in a power amplifier stage in different conduction angles of operation as described by class of operation (i.e. Class A, Class B, Class AB) with two separates bias circuits. Each biasing circuit would have distinct output impedances, with the impedance at baseband frequencies being of particular interest. Baseband frequencies are defined as the range of modulation frequencies for the input signal of interest, which typically ranges from the kHz to tens of MHz. Biasing parallel branches allows the phase difference between the IM3 components of each set of branches to approach 180 degrees. Additionally, the difference in the output impedance at baseband frequencies for the bias circuits allows for additional phase shift for the IM3 components, enabling a 180 degree difference between the IM3 components to be achieved. The number of branches in each set is adjusted such that the magnitudes of the IM3 components are substantially equal. That is, because the amplification of the sets of branches must be substantially equal to maximize performance, the number of branches in each set is adjusted to compensate for amplification differences.

[0051] The conduction angle of operation (i.e. Class A, Class AB, Class B, near-Class B) of the power amplifier branches is adjusted by varying the dc operating current in the branches with the bias circuit. Typically, control voltages and/or control currents are varied in the bias circuit to change the dc operating current and hence the conduction angle of operation. The impedance of the bias circuit can be modified, in one implementation, by using a resistor in series with the bias circuit. The value of the resistor can be varied to obtain different impedance values.

[0052] Referring to Figure 9, one stage of a power amplifier 7a consists of three components: an on-chip power divider 10, two sets of branches 12 and 14 belonging to one stage of an amplifier with separate bias circuits (not shown) biasing each set of branches, followed by an on-chip power combiner 16. Each set of branches 12 and 14 comprises one or more branches 18_a, 18_b . . . 18_n of cells 20. Cells 20 can consist of one or more transistors and other passive circuit elements. The input, V₁, consists of a sum of sinusoids at two different frequencies:

V_x = A Sm(W₁/) + B sin(w₂/) [0053] The input signal V₁ is passed to on-chip power divider 10. One example of a suitable on-chip power divider is a microstrip line with a characteristic impedance of Z₀ split into two quarter wave length lines with a characteristic impedance of Z₀*sqrt(2).

The input is divided into two signals with the same frequency components, but with a fraction of the power of the input and where one, V₂, and the other signal, V₃, have no

phase difference.

V₇ = -₇=sin(w_l/)+-₇=_^sin(vv,t)

V2 V2

[0054] These signals are then passed to branch sets 12 and 14, respectively. The signal received by each amplifier is amplified according to the amplifier's transfer function which may be approximately modeled using the following respective equations:

V₄ = K_lA x V₆ +K_2A x V₆ ² +K_3A x V₆ ³ V₅ = K_w x V₇ +K_2B x V₇ ² +K_iB x V₇ ³

[0055] where K_1A represents the coefficients of the third-order voltage transfer function of branch set 12, and K,_B represents the coefficients of the third-order voltage transfer function of branch set 14. One important feature of this amplifier stage design is that the K_3A term in branch set 12 and the K_3B term in branch set 14 are substantially equal and opposite. In addition to this condition, the phase of the fundamental frequency

components are substantially equal resulting in maximum power combining of the fundamental components. The following equations examine one set of IMD3 terms. The other IMD3 terms are similar in form and follow the same mathematical operations. One IM 3 term from 12: K 3Λ ² (W₁Z) X Sm(W₂/]

1 sin ² a = — (1 - cos(2α))

Using the identity 2 cos(2w,/) x sin(w₂/)] cos(or) x sin(/?) = — sin(er + β) — sin(α - β) Using the identity 2 2

One IM3 term from 14: [cos² (W_j/) x cos(w₂/) J cos a = — 1 (1 + cos(2or)) Using the identity + cos(2w,/) x cos(w₂/)] cos(or) x cos(yff) = — cos(α - β) + — cos(a + β)

Using the identity + — cos(2w,/ + W₂/)

The outputs of branch sets 12 and 14 are passed to second on-chip power combiner 16 that may or may not be the same type as first on-chip power divider 10 and used to combine the RF signals present at the output of the two branch sets into one RF

output signal. As can be seen above, when K₃A = -K_3B this set of IMD3 terms will cancel. Similarly all of the other IMD3 terms will cancel as well leading to an

improvement in OIP3. To specify, the reduction in IMD3 levels will move the intersection point between the extrapolated 1 : 1 slope of the fundamental output power and the extrapolated 3:1 slope of the third-order intermodulation products to a higher power resulting in a higher 0IP3 value. Looking at the first order terms present in amplifier branches 12 and 14,

1^st order term from 12:

l^sl order term from 14:

[0057] It can be seen that the output of on-chip power combiner 16 due to these terms is as follows:

V_{6 =} (^KIA + KU> ) [_A . _sin(_Wj/)_{+ B} . sin(w₂r)]

If K_1A is substantially equal to K_IB, then the fundamental term will be present at the output of on-chip power combiner 16. Having K_1A substantially equal K_IB also ensures that the phases of the fundamental components for both sets of branches are equal.

[0058] To ensure that the magnitudes of the EMD3 components are substantially equal in parallel sets of branches 12 and 14, the correct size must be chosen for each set of branches. The size of each set of branches is directly related to how much power it can produce. Two branches with the same number of unit cells biased at different points (i.e. different conduction angles of operation for each branch) will generate different IMD3 levels. For example, a branch with a certain number of unit cells 20 biased in the class AB mode of operation will generate significantly less IMD3 terms then a branch of the same size biased in the near-class B mode of operation at the same input power level. Thus, the near-class B mode amplifier must be sized so that its IMD3 magnitudes are substantially equal to the IMD3 magnitudes of the class AB mode amplifier at the same input power levels. One method for determining the size is by testing a number of near- class B mode branch sets to determine the appropriate IMD3 magnitudes. That is, as the IMD3 magnitudes of the two parallel set of branches diverge, then the improvement in OIP3 seen at the output of the output power combiner 16 will not be as great had the IMD3 levels been substantially equal in magnitude and opposite in phase. Moreover, the IMD3 magnitudes for branch sets 12 and 14 may be substantially equal at one power level, but unequal at another.

[0059] In addition to the size of the individual branch sets, the number of branch sets in a particular amplifier stage may also change based on the application of the amplifier. Thus, if a stage in the power amplifier has three branch sets, then on chip power dividers 10 and 16 must be designed to split input Vi three ways and also to combine the output of three branch sets into a single output signal V₆. Thus, it should be understood that the number of branch sets in any one amplifier stage 7 may vary depending on the application of power amplifier 3.

[0060] In yet another embodiment, the phase of K₃ can be changed by operating the amplifier in either the gain compression mode or the gain expansion mode. In the gain compression mode, the gain of the branch or set of branches decreases with increasing input power whereas in the gain expansion mode, the branch gain increases with increasing input power. The output power at the fundamental frequency can be modeled using the following terms: Ki * A + K₃ * A³ + K₅ * A⁵ where A is the amplitude of the input voltage signal and the K terms represent the Taylor series expansion coefficients that describe the branch's output voltage to input voltage transfer characteristics. The even order K terms do not contribute to the IMD3 components and hence have not been included in the equations. [0061] For gain expansion, the K₃ and K₅ terms are positive provided Ki is positive, and for gain compression, the K₃ and K₅ terms are negative. The third order DVID components for a two tone excitation also contain the K₃ and K₅ terms. This implies that the IMD3 components are in phase with respect to the fundamental during gain expansion and anti-phase with respect to the fundamental for gain compression. In RF amplifiers, this can be achieved by adjusting the biasing of one or more branches by varying the bias levels and using biasing circuits with different impedances.

[0062] The range of power levels where improvement is observed may vary as this technique is used in different semiconductor IC processes, and the incorporation of a control loop may assure the improvement over a broad power range. A common problem is that the K₃ term, as related to the mathematical derivations, may vary as a function of RP input power. Thus, a control loop may be used to compensate for the changes in K₃ by adjusting the bias level (i.e. conduction angle) and the impedance of the bias circuit of both power amplifier branch sets. This dynamic compensation for the changes in K₃ as a function of RF power allows the IMD3 magnitudes and phases to be adjusted for optimal IM3 cancellation/reduction over a wide range of input powers.

[0063] Referring to FIG. 10, a control loop 22 is shown connected from input V₁ to the biasing circuit (not shown) for branch sets 12 and 14 of amplifier stage 7a. A correction signal 24 is generated by monitoring the RF input signal Vi to control the biasing level and impedance of the bias circuit (not shown) of branch sets 12 and 14 as a function of power. That is, the RF input signal Vi is sampled and fed into control logic block 22, which generates the appropriate bias levels for the applied RF input power. These bias levels may be generated by any number of means, such as (but not limited to) comparing the input power level Vi with levels stored in a look-up table or by using a circuit block to directly generate the respective bias levels for the specific input power level. Correction signal 24 controls the bias levels and bias circuit impedance of branch sets 12 and 14 by varying the control voltages for the bias circuit (not shown). More specifically, if control logic 22 determines that branch set 14 should be biased more towards a Class AB mode, then the control voltages of the bias circuits will be adjusted accordingly. Bias control logic 22, in one implementation, can be located in the bias circuitry for branch set 14 and also in branch set 12. Also, the impedance of the bias circuit can be adjusted with switches that turn on or off segments of a parallel resistor array (not shown). As a result of the bias/impedance adjustment capability of the bias circuit (not shown), OIP3 improvement across a wide range of power levels can be obtained.

Referring to FIG. 11, a flowchart for control logic 22 is shown. Input power level

Vi is first sensed at step 26, and the information is used to determine the changes that should be made to branch sets 12 and 14 by comparing the sensed signal to, for example, (1) values stored in a look-up table, in step 28 or (2) converting the sensed signal to the respective bias/impedance levels for the bias circuits. The possible changes to the bias circuits are: (1) change the impedance of the bias circuit, step 34 or (2) increase/decrease the bias of the branches, step 32. Once a decision is made in control logic block 22, the appropriate changes are made to branch sets 12 and 14, at step 36, to make the magnitudes of the IMD3 components of branch sets 12 and 14 substantially equal, the phases of the IMD3 components 180 degrees out of phase with respect to one another, and the phases of the fundamentals nearly equal. [0065] The above described amplifier improvements for EVB reduction results in very wide band solutions and can be implemented completely on-chip. The techniques are based on a unique power amplifier topology combined with a novel biasing technique at the amplifier branch level. The techniques are very flexible and can be applied to any IC process (i.e. Si CMOS, SiGe BiCMOS, GaAs HBT, etc..)

[0066] It should be appreciated by those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope and spirit of the invention. It is intended that the present invention cover such modifications and variations as come within the scope and spirit of the appended claims and their equivalents.

Claims

What we claim: 1. A discrete amplifier for canceling at least one distortion component at the output of the discrete amplifier comprising: a. a first stage having at least a first branch and a second branch in parallel with one another, wherein each of said first and second branches is formed of one or more transistor legs having one or more unit cells in parallel with one another; b. a second stage having at least a third branch and a fourth branch in parallel with one another, wherein each of said third and fourth branches is formed of one or more transistor legs having one or more unit cells in parallel with one another; c. a first biasing circuit having a first impedance and a first biasing level, said first biasing circuit being operatively connected to said first stage first branch for biasing said first branch into a first mode of operation; d. a second biasing circuit having a second impedance and a second biasing level, said second biasing circuit being operatively connected to said first stage second branch for biasing said second branch into a second mode of operation; e. a third biasing circuit having a third impedance and a third biasing level, said third biasing circuit being operatively connected to said second stage third branch for biasing said third branch into a third mode of operation; f a fourth biasing circuit having a fourth impedance and a fourth biasing level, said fourth biasing circuit being operatively connected to said second stage fourth branch for biasing said fourth branch into a fourth mode of operation, wherein at least one of a. said first mode of operation and said second mode of operation, and b. said third mode of operation and said fourth mode of operation are chosen so that at least one distortion component is substantially canceled at a respective output of at least one of said first stage and said second stage.

2. The discrete amplifier of claim 1, wherein said first biasing circuit first impedance and first biasing level differs from said second biasing circuit second impedance and second biasing level.

3. The discrete amplifier of claim 1, wherein a. said impedance of said first and second biasing circuits and said biasing level of said first and second branches are different, and b. said impedance of said third and fourth biasing circuits and said biasing level of said third and fourth branches are different, and chosen so as to maximize the cancellation of said at least one distortion component at the output of at least one of said first stage and said second stage of said discrete amplifier.

4. The discrete amplifier of claim 1, wherein said first, said second, said third and said fourth braches are formed on a single integrated circuit chip and said first biasing circuit, said second biasing circuit, said third biasing circuit and said fourth biasing circuit are physically located on said same single integrated circuit chip to minimize electrical parasitics so as to maximize the cancellation of said at least one distortion component.

5. The discrete amplifier of claim 1, further comprising a sensing circuit that senses the input power to said discrete amplifier and causes at least one of said first, said second, said third and said fourth biasing circuits to adjust the operating mode of its respective branch by adjusting at least one of said biasing circuit level and impedance so as to maximize the cancellation of said at least one distortion component.

6. The discrete amplifier of claim 1, wherein said first mode, said second mode, said third mode and said fourth mode are chosen from one of Class A, Class B, Class C, and Class AB modes of operation.

7. The discrete amplifier of claim 6, wherein said first, said second, said third and said fourth biasing circuits are adjusted to change the impedance of said respective biasing circuits to maximize the cancellation of said at least one distortion component.

8. The discrete amplifier of claim 6, wherein said first branch first mode and said second branch second mode cause a substantial cancellation of at least one harmonic.

9. The discrete amplifier of claim 6, wherein said third branch third mode and said fourth branch fourth mode cause a substantial cancellation of a third order inter- modulation distortion component.

10. The discrete amplifier of claim 6, wherein one of said first stage first branch and said first stage second branch have a plurality of transistor legs to increase the output power of said one of said first stage first branch and said first stage second branch.

11. The discrete amplifier of claim 1, wherein said first stage and said second stage are connected in series.

12. A discrete amplifier for canceling at least one distortion component at the output of the discrete amplifier comprising: a. an input port for receiving a first signal; b. an output port for outputting a second signal that is related to said first signal; c. a first branch operatively connected to said input and said output ports and a second branch in parallel with said first branch and operatively connected to said input and said output ports, d. a first biasing circuit operatively connected to said first branch for biasing said first branch into a first mode of operation; e. a second biasing circuit operatively connected to said second branch for biasing said second branch into a second mode of operation; wherein said first mode of operation and said second mode of operation are chosen so that said at least one distortion component in said second signal is substantially reduced, said first branch, said second branch, said first biasing circuit and said second biasing circuit are located on a single integrated circuit chip to minimize electrical parasitics so as to maximize the cancellation of said at least one distortion component.

13. The discrete amplifier of claim 12, wherein said at least one distortion component is a third harmonic of said first signal.

14. The discrete amplifier of claim 12, wherein said at least one distortion component is a third order inter-modulation distortion component of said first signal.

15. The discrete amplifier of claim 12, wherein said mode of operation is chosen from one of Class A, Class B, Class C, and Class AB modes of operation.

16. The discrete amplifier of claim 12, further comprising a sensing circuit that senses said first signal and causes at least one of said first and said second biasing circuits to change the operating mode of its respective branch by adjusting at least one of a biasing circuit level and biasing impedance so as to maximize the cancellation of said at least one distortion component.

17. The discrete amplifier of claim 12, wherein a first impedance and a first current of said first biasing circuit differs from a second impedance and a second current of said second biasing circuit.

18. The discrete amplifier of claim 16, wherein said first and said second biasing circuits are adjusted to change the impedance of said respective biasing circuits to maximize the cancellation of said at least one distortion component.

19. The discrete amplifier of claim 12, wherein one of said first branch and said second branch have a plurality of transistor legs to increase the output power of said one of said first branch and said second branch.