EP2257900A4 - Optimization of integrated circuit design and library - Google Patents

Optimization of integrated circuit design and library

Info

Publication number
EP2257900A4
EP2257900A4 EP09709144A EP09709144A EP2257900A4 EP 2257900 A4 EP2257900 A4 EP 2257900A4 EP 09709144 A EP09709144 A EP 09709144A EP 09709144 A EP09709144 A EP 09709144A EP 2257900 A4 EP2257900 A4 EP 2257900A4
Authority
EP
European Patent Office
Prior art keywords
library
optimization
integrated circuit
circuit design
design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09709144A
Other languages
German (de)
French (fr)
Other versions
EP2257900A2 (en
Inventor
Andre Inacio Reis
Anders Bo Rasmussen
Vinicius Pazutti Correia
Ole Christian Andersen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nangate AS
Original Assignee
Nangate AS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nangate AS filed Critical Nangate AS
Publication of EP2257900A2 publication Critical patent/EP2257900A2/en
Publication of EP2257900A4 publication Critical patent/EP2257900A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
EP09709144A 2008-02-05 2009-02-05 Optimization of integrated circuit design and library Withdrawn EP2257900A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2622208P 2008-02-05 2008-02-05
PCT/US2009/033243 WO2009100237A2 (en) 2008-02-05 2009-02-05 Optimization of integrated circuit design and library

Publications (2)

Publication Number Publication Date
EP2257900A2 EP2257900A2 (en) 2010-12-08
EP2257900A4 true EP2257900A4 (en) 2012-10-17

Family

ID=40952683

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09709144A Withdrawn EP2257900A4 (en) 2008-02-05 2009-02-05 Optimization of integrated circuit design and library

Country Status (4)

Country Link
EP (1) EP2257900A4 (en)
JP (1) JP5127935B2 (en)
CN (1) CN101990671A (en)
WO (1) WO2009100237A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102279899B (en) * 2011-04-01 2013-05-01 无锡中科微电子工业技术研究院有限责任公司 Method for optimizing simplified standard unit library
CN102663175B (en) * 2012-03-27 2013-11-06 苏州芯禾电子科技有限公司 System and method for constructing three-dimensional model of radio-frequency passive device
KR101904417B1 (en) * 2012-03-30 2018-10-08 삼성전자주식회사 Semiconductor integrated circuit and method of designing the same
US10650110B2 (en) 2015-07-08 2020-05-12 Hewlett Packard Enterprise Development Lp Photonic circuit design systems
DE112017001063T5 (en) * 2016-02-29 2018-12-06 Synopsys, Inc. Create and reuse customizable structured links
US10572615B2 (en) * 2017-04-28 2020-02-25 Synopsys, Inc. Placement and routing of cells using cell-level layout-dependent stress effects
CN107610569A (en) * 2017-10-23 2018-01-19 宜宾学院 The determination method of analogous circuit experiment equipment and its required electronic component
CN108846160B (en) * 2018-05-03 2023-03-10 上海华虹宏力半导体制造有限公司 Standard cell library circuit design method
TWI761750B (en) * 2020-01-08 2022-04-21 國立雲林科技大學 Automatic performance analysis system and method thereof for analog circuits

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010010090A1 (en) * 1998-02-11 2001-07-26 Boyle Douglas B. Method for design optimization using logical and physical information
US20010032067A1 (en) * 1999-12-28 2001-10-18 Mahadevamurty Nemani Method and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curves

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05120372A (en) * 1991-10-25 1993-05-18 Nec Corp Designing system for gate array
US5956257A (en) * 1993-03-31 1999-09-21 Vlsi Technology, Inc. Automated optimization of hierarchical netlists
US6539536B1 (en) * 2000-02-02 2003-03-25 Synopsys, Inc. Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics
JP2001265842A (en) * 2000-03-21 2001-09-28 Katsumi Hashimoto Composite gate synthesis device, recording medium with composite gate synthesis program stored thereon, and semiconductor device
DE10025583A1 (en) * 2000-05-24 2001-12-06 Infineon Technologies Ag Integrated circuit cell layout optimisation method has initial cell layout automatically modified after optimisation of component dimensions
JP2003036280A (en) * 2001-07-23 2003-02-07 Hitachi Ltd Design data library, design method and manufacturing method of semiconductor integrated circuit
US7496867B2 (en) * 2007-04-02 2009-02-24 Lsi Corporation Cell library management for power optimization

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010010090A1 (en) * 1998-02-11 2001-07-26 Boyle Douglas B. Method for design optimization using logical and physical information
US20010032067A1 (en) * 1999-12-28 2001-10-18 Mahadevamurty Nemani Method and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curves

Also Published As

Publication number Publication date
CN101990671A (en) 2011-03-23
JP5127935B2 (en) 2013-01-23
JP2011525261A (en) 2011-09-15
EP2257900A2 (en) 2010-12-08
WO2009100237A3 (en) 2009-11-05
WO2009100237A2 (en) 2009-08-13

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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RIN1 Information on inventor provided before grant (corrected)

Inventor name: ANDERSEN, OLE CHRISTIAN

Inventor name: CORREIA, VINICIUS PAZUTTI

Inventor name: RASMUSSEN, ANDERS BO

Inventor name: REIS, ANDRE INACIO

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20120917

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 17/50 20060101AFI20120911BHEP

Ipc: G06F 17/40 20060101ALI20120911BHEP

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