EP2293199A4 - Information processor and its control method - Google Patents

Information processor and its control method

Info

Publication number
EP2293199A4
EP2293199A4 EP08764002A EP08764002A EP2293199A4 EP 2293199 A4 EP2293199 A4 EP 2293199A4 EP 08764002 A EP08764002 A EP 08764002A EP 08764002 A EP08764002 A EP 08764002A EP 2293199 A4 EP2293199 A4 EP 2293199A4
Authority
EP
European Patent Office
Prior art keywords
control method
information processor
processor
information
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08764002A
Other languages
German (de)
French (fr)
Other versions
EP2293199A1 (en
Inventor
Hiroshi Nakayama
Junji Ichimiya
Shintaro Itozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP2293199A1 publication Critical patent/EP2293199A1/en
Publication of EP2293199A4 publication Critical patent/EP2293199A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
EP08764002A 2008-06-03 2008-06-03 Information processor and its control method Withdrawn EP2293199A4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2008/001405 WO2009147697A1 (en) 2008-06-03 2008-06-03 Information processor and its control method

Publications (2)

Publication Number Publication Date
EP2293199A1 EP2293199A1 (en) 2011-03-09
EP2293199A4 true EP2293199A4 (en) 2012-04-25

Family

ID=41397790

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08764002A Withdrawn EP2293199A4 (en) 2008-06-03 2008-06-03 Information processor and its control method

Country Status (4)

Country Link
US (1) US8516291B2 (en)
EP (1) EP2293199A4 (en)
JP (1) JP5201208B2 (en)
WO (1) WO2009147697A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101889402A (en) * 2007-12-06 2010-11-17 拉姆伯斯公司 The loss of signal based on the edge detects

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5794020A (en) * 1995-06-16 1998-08-11 Hitachi, Ltd. Data transfer apparatus fetching reception data at maximum margin of timing
US5867541A (en) * 1994-05-18 1999-02-02 Hitachi, Ltd. Method and system for synchronizing data having skew
WO2000054164A1 (en) * 1999-03-05 2000-09-14 International Business Machines Corporation Dynamic wave-pipelined interface apparatus and methods therefor
US20070176658A1 (en) * 2006-01-30 2007-08-02 Elpida Memory, Inc. Timing adjustment circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05145537A (en) 1991-11-20 1993-06-11 Fujitsu Ltd Interface circuit for correcting phase between bit of information
JPH113135A (en) * 1997-06-11 1999-01-06 Hitachi Ltd Clock delay amount control method
JP3275961B2 (en) * 1997-07-15 2002-04-22 日本電気株式会社 Data and clock phase adjustment circuit
JP3522126B2 (en) * 1998-11-17 2004-04-26 沖電気工業株式会社 Synchronization detection method and apparatus, and phase synchronization method and apparatus
JP3973308B2 (en) 1998-11-27 2007-09-12 富士通株式会社 Integrated circuit device incorporating a self-timing control circuit
JP3449270B2 (en) * 1998-12-22 2003-09-22 日本電気株式会社 Data and clock phase adjustment circuit
JP2000244469A (en) * 1999-02-23 2000-09-08 Nippon Telegr & Teleph Corp <Ntt> Bit synchronization circuit
US7418068B2 (en) 2001-02-24 2008-08-26 International Business Machines Corporation Data capture technique for high speed signaling
JP2004127147A (en) 2002-10-07 2004-04-22 Hitachi Ltd Deskew circuit and disk array controller using same
US7089440B2 (en) * 2003-11-24 2006-08-08 International Business Machines Corporation Skew compensation for a multi-agent shared bus
JP4808414B2 (en) 2005-01-31 2011-11-02 富士通株式会社 Computer system and memory system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5867541A (en) * 1994-05-18 1999-02-02 Hitachi, Ltd. Method and system for synchronizing data having skew
US5794020A (en) * 1995-06-16 1998-08-11 Hitachi, Ltd. Data transfer apparatus fetching reception data at maximum margin of timing
WO2000054164A1 (en) * 1999-03-05 2000-09-14 International Business Machines Corporation Dynamic wave-pipelined interface apparatus and methods therefor
US20070176658A1 (en) * 2006-01-30 2007-08-02 Elpida Memory, Inc. Timing adjustment circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2009147697A1 *

Also Published As

Publication number Publication date
JPWO2009147697A1 (en) 2011-10-20
US8516291B2 (en) 2013-08-20
JP5201208B2 (en) 2013-06-05
WO2009147697A1 (en) 2009-12-10
EP2293199A1 (en) 2011-03-09
US20110072296A1 (en) 2011-03-24

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Legal Events

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Effective date: 20160105