EP2329496A1 - Serial-connected memory system with output delay adjustment - Google Patents
Serial-connected memory system with output delay adjustmentInfo
- Publication number
- EP2329496A1 EP2329496A1 EP09817125A EP09817125A EP2329496A1 EP 2329496 A1 EP2329496 A1 EP 2329496A1 EP 09817125 A EP09817125 A EP 09817125A EP 09817125 A EP09817125 A EP 09817125A EP 2329496 A1 EP2329496 A1 EP 2329496A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- command
- clock signal
- input
- duty cycle
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Definitions
- the invention relates generally to solid state memory systems featuring a set of serial-connected memory devices.
- NAND flash memory systems use a large number of parallel signals for the commanding, addressing, and data transferring operations. This was a very popular way of configuring memory systems and results in very fast system operation. This is particularly true for random access memory devices like DRAM (dynamic random access memory), SRAM (static random access memory), etc.
- DRAM dynamic random access memory
- SRAM static random access memory
- Such parallel interfaces use a large number of pins to read and write data. As the number of input pins and wires increases, so do a number of undesired effects. These effects include inter-symbol interference, signal skew and cross talk.
- serial in/out data pins typically have serial in/out data pins along with two control signals for the enabling and disabling of a serial input port and serial output port respectively in order to provide a memory controller with the maximum flexibility of serial data communication.
- Some of these memory system configurations employ a shared bus topology for the system clock distribution, which is referred to as a 'common clock system' or 'multi-drop clocking system'.
- Some of these architectures use a point-to-point serial- connected clocking architecture featuring a DLL (delay locked loop) or PLL (phase locked loop) in every memory chip in order to synchronize two clock signals in each memory device, one being an input clock received from a preceding device or controller and the other being an output clock transmitted to the next device.
- the invention provides a method in a slave device of a plurality of serial-connected slave devices, the method comprising: receiving a command from a master device specifying an adjustment to a clock duty cycle; 76181-75
- the method further comprises: receiving a command from a master device specifying how the slave device is to adjust a delay to be applied to at least one signal output by the slave device; receiving at least one input signal, the at least one input signal comprising at least the input clock signal; for each of the at least one input signal: generating a delayed version of the input signal in accordance with the command; outputting the delayed version of the input signal, the delayed version of the input clock signal comprising a delayed version of the duty cycle corrected clock signal.
- receiving a command from a master device specifying an adjustment to a clock duty cycle comprises receiving a command containing a command identifier that identifies the command as a duty cycle correction command, the command further containing data indicating how to adjust the duty cycle.
- receiving a command further comprises receiving a device address indicating which device(s) acting as slave devices is to execute the command.
- the method further comprises: performing the step of generating the duty cycle corrected clock signal in accordance with the command if the command has a device address that matches a device address of the slave device; performing the step of generating the duty cycle corrected clock signal in accordance with the command if the command has a device address that is a broadcast device address. 76181-75
- the data indicating how to adjust the duty cycle correction comprises an indication of the selected one of the plurality of delays.
- the invention provides a method in a memory system comprising a master device and a plurality of serial-connected slave devices comprising at least a first slave device and a last slave device, the method comprising: in the master device: a) outputting a first clock signal that functions as an input clock signal of the first slave device; b) receiving a second clock signal that is an output clock signal of the last slave device; c) generating a duty cycle correction command as a function of a duty cycle of the second clock signal and outputting the duty cycle correction command; in the first slave device of the plurality of serial-connected slave devices: a) receiving the first clock signal from the master device as the input clock signal of the first slave device; b) generating an output clock signal from the input signal; in each other slave device of the plurality of serial-connected slave devices: a) receiving the output clock signal of a preceding slave device as an input clock signal of the slave device; b) generating an output clock signal from the input clock signal; in each of at least one of the
- each slave device is a memory device and the master device is a memory controller. 76181-75
- the method further comprises: in the master device: a) outputting at least one output signal, the at least one output signal comprising the first clock signal to function as an input clock signal of the first slave device; b) receiving a second clock signal that is an output clock signal of the last slave device; c) determining an amount of phase offset between the first clock signal and the second clock signal; d) generating an output delay adjustment command as a function of the phase offset between the first clock signal and the second clock signal and outputting the output delay adjustment command.
- generating a duty cycle correction command as a function of a duty cycle of the second clock signal and outputting the duty cycle correction command comprises generating a duty cycle correction command for execution by any specified one of the plurality of serial-connected slave devices.
- generating a duty cycle correction command as a function of a duty cycle of the second clock signal and outputting the duty cycle correction command comprises generating a duty cycle correction command for execution by all of the plurality of serial-connected slave devices.
- receiving the duty cycle correction command comprises receiving a command containing a command identifier that identifies the command as a duty cycle correction command, and containing data indicating how to adjust the duty cycle.
- generating a duty cycle corrected clock signal comprises: a) generating a half rate clock signal from the input clock signal; b) delaying the half rate clock signal by a selected one of a plurality of delays to produce a delayed half rate clock signal; c) combining the half rate clock signal with the delayed half rate clock signal to produce the duty cycle corrected clock signal.
- the data indicating how to adjust the duty cycle correction comprises an indication of the selected one of the plurality of delays. 76181-75
- the invention provides a slave device for use in an arrangement comprising a plurality of serial-connected slave devices, the slave device comprising: a command input for receiving a command from a master device specifying an adjustment to a duty cycle; a clock input for receiving an input clock signal; a duty cycle correction circuit for generating a duty cycle corrected clock signal from the clock input in accordance with the control command; a clock output for outputting the duty cycle corrected clock signal.
- the slave device is a memory device.
- the invention provides a slave device for use in an arrangement comprising a plurality of serial-connected slave devices, the slave device comprising: a command input for receiving a command from a master device specifying how to perform output delay adjustment; a clock input for receiving an input clock signal; an output delay adjustment circuit for generating a delayed clock signal from the clock input in accordance with the command; a clock output for outputting the delayed clock signal.
- the slave device comprises: a command processing circuit that processes the command, wherein the command contains a command identifier that identifies the command as an output delay adjustment command, and contains data indicating how to adjust the output delay.
- the slave device further comprises: a device address register; wherein the command further comprises a device address indicating which slave device is to execute the command, the slave device configured to execute the command if the device identifier matches contents of the device address register. 76181-75
- the output delay adjustment circuit comprises: for each of a plurality of input signals, inclusive of the input clock signal, a delay circuit that delays the input signal by a selected one of a plurality of delays to produce a delayed version of the input signal.
- the invention provides a memory system comprising: a plurality of serial-connected slave devices comprising at least a first slave device and a last slave device; a master device connected to the first slave device and to the last slave device; the master device configured to output a first clock signal that functions as an input clock signal of the first slave device; a clock input for receiving a second clock signal that is an output clock signal of the last slave device; a phase detector that determines an amount of phase offset between the first clock signal and the second clock signal; a command generator that generates an output delay adjustment command as a function of the amount of phase offset; wherein, the first slave device of the plurality of serial-connected slave devices: a) receives the first clock signal from the master device as the input clock signal of the first slave device; b) generates an output clock signal from the input clock signal; wherein each other slave device of the plurality of serial-connected slave devices: a) receives the output clock signal of a preceding slave device as an input clock signal of the slave device; b)
- the command generator is configured to generate the output delay adjustment command for execution by a specified one of the plurality of serial-connected slave devices.
- the methods and apparatus described herein can be applied to any kind of semiconductor integrated circuit system having any kind of semiconductor integrated circuit devices as slave devices in a serial-connected configuration with a common interface between adjacent devices.
- integrated circuit types include central processing units, graphics processing units, display controller IC, disk drive IC, memory devices like NAND Flash EEPROM, NOR 76181-75
- Figure 1 is a system block diagram of serial-connected memory system having a controller programmable duty cycle correction scheme
- Figure 2 is a block diagram of a memory device having controller programmable duty cycle correction scheme
- Figure 4 is a timing diagram of controller programmable duty cycle correction
- Figure 5 is a flowchart of a method of duty cycle correction
- Figure 7 is a block diagram of a programmable delay line for output delay adjustment
- Figure 10 is a timing diagram for a write output delay register command.
- Some of the memory system configurations referred to in the background employ a shared bus topology for the system clock distribution, which is referenced to as a 'common clock system' or 'multi-drop clocking system'. If the system clock is applied to too many memory devices in parallel and the clock signal travels too far from the clock source, typically a memory controller, the maximum operating clock frequency may be limited by the total loading of the clock signal and the distance that the clock travels in the memory system's physical layout.
- FIG. 1 shown is a system block diagram of a serial- connected memory system generally indicated at 101 employing a controller programmable duty cycle correction scheme.
- the memory system 101 includes a memory controller 10 as a master device connected to a first memory device 100-1.
- Memory device 100-1 is the first of a series of slave devices including devices 100-1 through 100-8 that are connected in a ring configuration, with the 76181-75
- a highly multiplexed unidirectional point-to-point bus architecture is provided to transfer information such as commands, addresses and data from the memory controller 10 to the memory devices 100-1 to 100-8.
- This bus architecture includes a link 90 from the memory controller 10 to the first memory device 100-1 , and a respective link between each pair of adjacent memory devices, these including links 90-1 through 90-7, and a link 90-8 between the last memory device 100-8 and the memory controller 10.
- the corresponding signals (and input ports) of a succeeding device are referred to as CSI (Command Strobe Input), DSI (Data Strobe Input), Dn (Data Input), CKI/CKI# (differential clock input signals).
- CSI Common Strobe Input
- DSI Data Strobe Input
- Dn Data Input
- CKI/CKI# differential clock input signals
- CE# chip enable
- RST# reset
- the physical interconnections include differential clock buses S111 , S111 -1 to S111 -8 for differential clock signals, S112, S112-1 to S112-8 for command strobe, S113, S113-1 to S113-8 for data strobe, S114, S114-1 to S114-8 for data.
- the width of the link may be programmed through a link configuration register to utilize 1 , 2, 4, or 8 of a device package's available data input and output pins. This feature allows these memory devices to operate in a ring configuration together with devices that have smaller or larger maximum link widths provided they are all programmed to use the same link width. See for example 'Switching Method of Link and Bit Width' (WO 2008/070978), hereby incorporated by reference in its entirety.
- DSI Data Strobe Input
- Qn buffer When Data Strobe Input (DSI) is HIGH while the memory device is in 'Read- Mode', it enables the read data output path and Qn buffer (not shown). If DSI is LOW, the Qn buffer holds the previous data accessed. If DSI is HIGH while the memory device is in 'Write-Mode', it enables a Dn buffer and receives Write Data Packet on the rising edges of CKI or falling edges of CKI#. 76181-75
- Data Strobe Output is an echo signal of DSI. It echoes DSI transitions with latency tIOL referenced to the rising edges of CKO or to the falling edges of CKO#. As indicated above, tIOL is two clock cycles in a particular implementation.
- the memory controller 10 contains a phase detector 11 , a duty detector 13 and a command generator 12. In some embodiments, the memory controller 10 only includes the phase detector 11 in which case only output delay adjustment is performed. In some embodiments, the memory controller 10 includes only the duty detector 13 in which case only duty cycle correction is performed. In some embodiments, both the phase detector 11 and the duty detector 13 are included in which case both output delay adjustment and duty cycle correction may be performed. This last case is assumed in the detailed description which follows.
- the phase detector 11 and the duty detector 13 are connected to the command generator 12 through signal buses S11 and S12 respectively.
- the command generator 12 has an output signal bus S13 connected to CSO and Qn ports through which it can output commands.
- the second memory device 100-2 receives the three buses, S112-1 , S113-1 and S114-1, through its input ports, CSI, DSI and Dn, respectively. This approach applies to all of the eight memory 76181-75
- the device includes a memory core 150, command/address packet logic 130, data packet logic 140, and duty cycle correction logic 120.
- Memory core 150 may be a single bank of memory cell arrays or it could be multiple banks of memory cell arrays, depending on design variations.
- Data packet logic 140 processes and stores all necessary data transferring information.
- Command/address packet logic 130 processes all command instructions and/or 76181-75
- the device 100 includes clock input receiver 102D for CKI/CKI# which may for example be a differential type input buffer to handle the differential clock inputs, CKI & CKI#.
- the clock input receiver 102D translates the external interface levels of CKI/CKI# signals to the internal logic levels of an internal clock signal 'cki_i'.
- the internal clock signal, cki_i may be used in other internal logic blocks for various operations.
- the duty cycle correction logic 120 takes the internal clock signal, cki_i, and produces a duty cycle corrected clock signal clk_dcc.
- the duty cycle corrected clock signal, 'clk_dcc' is delayed by a controller programmable delay line, PDL2, 105D, and its delayed signal, 'clk_dcc_d', is finally driven to the input port of an output driver block 108D, which outputs the external clock output signals, CKO/CKO#.
- the device 100 includes command strobe receiver 102A which generates a buffered signal 'csi_i' from a CSI input signal.
- the buffered signal, csij is connected to the D port of a D-type flip-flop 103A.
- the flip-flop 103A is driven by the clock signal, 'cki_i', and latches the status of the 'csij' signal at every rising edge of 'cki_i'.
- the latched signal 'csijat' is provided to the command/address packet logic 130, and also is provided to the D port of another flip-flop 103E, whose clock input port is driven by the duty corrected clock signal, clk_dcc.
- the flip-flop 103G's output signal, 'dso_i' is delayed by a controller programmable delay line, PDL2, 105C, and its delayed signal, 'dso_d', is finally driven to the input port of an output driver block 108C, which outputs the external signal, DSO.
- PDL2, 105C controller programmable delay line
- 'dso_d' delayed signal
- DSO external signal
- the latched signal 'dnjat' is provided to the command/address packet logic 130 and also is provided to data packet logic 140.
- the latched signal, 'dnjat' is also provided to one input port of a multiplexer 104.
- the other port of the multiplexer 104 is driven by a signal, 'core_data' from the data packet logic 140.
- the output of the multiplexer 104 is connected to the D input port of a flip- flop 103F, whose clock input port is driven by the duty corrected clock signal, clk_dcc, and latches the status of the output of the multiplexer 104 at every rising 76181-75
- the internal signal dn_i includes both command content (as delineated by the command strobe input) and data input (as delineated by the data strobe input) when present.
- Each device has a device address, in some embodiments stored in a device address register 131.
- Each command includes a Device Address portion that contains the device address of one of the memory devices to which the command is addressed. There may also be a broadcast address that requires the command to be processed by all devices.
- the memory device 100 processes each command by examining the Device Address portion. If the Device Address information in the received command/address packet matches the memory device 100's own stored device address, the command/address packet logic 130 processes the command, and also issues an "id_match" signal to signify that the command is for that memory device.
- the id_match signal is used to steer the data flow path of the multiplexer 104. If “id_match” is in a HIGH logic state (more generally in a “match state” however that is defined) as a result of device address matching process, the multiplexer 104 selects "core_data" to be outputted, so that the data from the memory core 150 can be transferred to the flip-flop 103F.
- the multiplexer 104 selects "dnjat" to be outputted, so that the data received from the data input Dn can be transferred to the flip-flop 103F to be echoed at the output Qn.
- the multiplexer 104 allows for the selection between a) bypassing data received from the data input Dn by selecting the dnjat input of the multiplexer 104, and b) outputting the core_data by selecting the core_data input of the 76181-75
- the signal 'core_data' is usually transferred from the memory core 150 to the data packet logic 140, for example as part of a 'PAGE READ' operation upon request from the memory controller 10. Then after the 'PAGE READ' operation is done, the memory controller 10 can request a 'BURST READ' operation to the memory device with a command addressed to that memory device. In that case, the memory device processes the 'BURST READ' command and the corresponding address information including Device Address portion. If the Device Address information in the received command/address packet matches the memory device 100's own stored device address, the command/address packet logic 130 issues "id_match" signal in order to steer the data flow path of the multiplexer 104.
- the multiplexer 104 selects "core_data" to be outputted, so that the data previously transferred from the memory core 150 to the data packet logic 140 can be transferred to the flip-flop 103F.
- a delayed version of the data input signal Dn is produced as one component of a data output signal (Qn). Some of the time the data output signal is the delayed version of the data input signal. For the implementation described, this will be the case when there is content on the data 76181-75
- the data output signal comprises a delayed version of a signal produced locally to the memory device, after applying the delay to the signal produced locally to the memory device in accordance with the command.
- the signal produced locally to the memory device is the so-called core_data output from the data packet logic 140 but other scenarios are possible.
- a "Write Duty Cycle Correction Register” command assumes an implementation, as described herein, in which an amount of delay to be applied in performing duty cycle correction is controlled by writing a value to a duty cycle correction register. More generally, any command, referred to herein as a duty cycle correction command, may be employed that has the effect of causing a device to set how duty cycle correction is to be performed. Thus, the described "Write Duty Cycle Correction Register” command is to be considered a specific example of a duty cycle correction command.
- any command referred to herein as an output delay adjustment command, may be employed that has the effect of causing a device to set the amount of delay to be applied.
- the described "Write Output Delay Register" command is to be considered a specific example of an output delay adjustment command.
- the duty cycle correction circuit 120 includes a clock divider 123, and a controller programmable delay line 121 that includes a '4-to-16 Decoder' block and 'Programmable Delay Line (PDL1 )'. Respective outputs clk_ref, clk_del of the clock divider 123 and the controller programmable delay line 121 are input to an XOR gate 122 the output of which is the duty cycle corrected clock clk_dcc.
- the clock divider 123 derives an output signal 'clk_ref which has a frequency that is one half that of the input 'cki_i' signal.
- Clock divider circuits are well known in the art.
- the clock divider 123 includes a D-type flip-flop 103D that is driven by the internal clock signal, cki_i, through its clock input port.
- the output port Q of the D-type Flip-Flop 103D is connected to the input port D though inverter logic 124 in order to obtain a half frequency output signal.
- the controller programmable delay line 121 produces an output signal, elk del, which is a delayed version of clk_ref.
- the amount of delay is determined by the '4-to-16 Decoder' logic block's select signals, which are controlled by DCR ⁇ 0:3> signal information received from command/address packet logic 130.
- the XOR logic gate 122 receives the two half clock signals, clk_ref and elk del, and outputs a duty cycle adjusted full clock signal, clk_dcc.
- Figure 3 is a block diagram of an example implementation of a programmable delay line 121 for duty cycle correction that may, for example, be used in the duty cycle correction circuit 120 of Figure 2.
- the unit delay block is composed of two NAND logic gates 1211 and 1212 and one inverter logic gate 1213.
- the first NAND logic gate 1211 receives the clk_ref input at its first input, and receives an output from a 4-to-16 decoder 1210 at its second input.
- the output of the first NAND logic gate 1211 is input to a first input of the second logic NAND gate 1212.
- the second input of the second logic NAND gate 1212 is connected to Vdd.
- the 4-to-16 Decoder block 1210 has a 4-bits wide input bus, DCR ⁇ 0:3> as its input.
- the decoder block 1210 decodes the input and outputs a 16-bit wide bus, SEI_ ⁇ 15:0>, with one line of the bus connected to each of the 16 unit delay blocks.
- the unit delay logic shown is an example of a known circuit technique has been used to to produce a register controlled delay-locked-loop. Other unit delay logics can alternatively be employed.
- a default setting for the power-on initialization is that having a logic HIGH state on the SEI_ ⁇ 7> bit, as it is in the middle position of the delay line.
- the default settings can be different, and it may be recommended to have minimum delay setting in order to be ready for operating at the maximum frequency.
- FIG 4 is an example of a timing diagram of the controller programmable duty cycle correction procedure, where all of the signals are as shown in Figure 3 except CKI which is the raw input clock signal that is to be duty corrected.
- the timing diagram is showing one extremely distorted clock input signal, CKI at the top, for the sake of example only.
- the half clock signal, clk_ref is derived from the 'clock divider' block 123 of Figure 2 and its rising and falling edges are aligned with two rising edges of CKI.
- the clock signal, clk_dcc would have a distorted duty ratio, such as 45% on, 55% off, for example, in the absence of any change to the DCR ⁇ 0:3> values which are shown to initially be set to "01 11 b".
- the duty cycle of the clock signal, clk_dcc is corrected to be 50% on and 50% off as the result of a shift in the selection of the controller programmable delay line 121 from SEL (7) being enabled to SEL (8) being enabled. 76181-75
- the contents of the DCR 132 are used to control the amount of delay introduced by the controller programmable delay line 121 in the duty cycle correction circuit 120, thereby controlling the duty cycle correction.
- the contents of the DCR 132 can be written with a 'Write Duty Cycle Register' command.
- FIG. 5 is a flow chart for the duty cycle correction procedure from the perspective of the controller.
- the method begins at block 5-1 with power on of the devices. At this point, all of the delay lines are initialized and device addresses for all devices are assigned.
- the memory controller 10 monitors the duty ratio of CKI/CKI# using the duty detector 13. If there is a duty cycle error, yes path block 5-3, then in block 5-4 the duty detector 13 asserts the "Duty_Add" or the "Duty_Sub” signal S12. After this, the command generator 12 issues the 'Write Duty Cycle Register' command with "DCR+1 " or "DCR-1" values.
- step 5-6 If there is still a duty cycle error, yes path block 5-6, then the method continues back at step 5-4 with the further adjustment to the duty cycle register. If there is no longer a duty cycle error, no path block 5-6, then duty cycle correction is completed at 5-7. Similarly, if no duty cycle error was detected in block 5-3, then at that point the method also is completed at 5-7.
- Table 1 below is an example command packet definition for writing to the Duty Cycle Register (DCR).
- a broadcast address is provided, for example FFh. If DA is set to the broadcast address, it means that the command is a broadcasting command, so that every memory device is expected to execute the command. Otherwise, only a specific memory device that is matching the DA will execute the command.
- a 'Read Duty Cycle Register' command is also implemented in order to give more flexibility to the controller 10. 76181-75
- FIG. 6 is an example of a timing diagram of a 'Write Duty Cycle Register' command packet sequence based on SDR (Single Data Rate) operation.
- SDR Single Data Rate
- this means that the 'Write Duty Cycle Register' command is a broadcasting command, so that every memory device is expected to execute the command.
- the broadcasting command is used for Duty Cycle Correction operation.
- the circuit disclosed also allows for the more flexible 76181-75
- tWDCR Write Duty Cycle Register Latency
- tWDCR value is set as 4 clock cycles as shown in Figure 6.
- the described programmable delay lines 105A, 105B, 105C, 105D are provided to allow programmably delaying the output signals CSO, Qn, DSO and CKO/CKO# in order to allow phase correction.
- Figure 1 also shows output delay register signal buses ODR ⁇ 0:1 > connected to a 2-to-4 Decoder logic block 106.
- the 2-to-4 Decoder logic 106 outputs four select signal buses, SEL2 ⁇ 0:3>. Those SEL2 ⁇ 0:3> select signals are all connected to the four controller programmable delay lines 105A, 105B, 105C and 105D.
- Figure 7 is showing an exemplary circuit block implementation for the output delay adjustment.
- programmable delay lines 105A, 105B, 105C and 105D are composed of four unit delay elements that are the same as those used in Figure 3. This means that the range of delay adjustment for the output is only 4/16 that of the range of delay of adjustment of the duty 76181-75
- Each programmable delay line 105A, 105B, 105C, 105D receives a respective signal cso_i, q_i, dso_i and clk_dcc, as the input of the delay line and produces a respective delayed output cso_d, q_d, dso_d and clk_dcc_d.
- signals will be increased correspondingly, for example to be 8 in number, and the number of delay line blocks for q_i and q_d, will be increased correspondingly, for example to be 8 in number.
- the '2-to-4 Decoder' logic 106 produces the SEL2 ⁇ 0:3> output such that only one of the 4 select signals is in a HIGH logic state and all the other 3 select signals are to be logic LOW states. Only the selected unit delay block transfers the respective input signal through the remaining unit delay blocks to the right of the selected unit delay block.
- the control input ODR ⁇ 0:1 > is used to select which of the unit delay blocks will process the respective inputs. The minimum delay is selected by selecting the right most unit delay block UNIT_0 in which case each output signal is the respective input signal delayed by one unit delay block, whereas the maximum delay is selected by selecting the left most unit delay block UNIT_3 in which case each output signal is the respective input signal delayed by four delay unit blocks.
- the '2-to-4 decoder' logic 106 with four unit delay blocks is implemented in this example circuit design. However more generally, any required number of delay units and the corresponding decoder logic may be used.
- a default delay setting may be used during the power-on initialization period. In this example, the default selection might for example be set to SEL2 ⁇ 0>, and the memory device will have the least amount of delay for each output path after power-on or hard reset in some other design variations.
- the use of 4 unit delay blocks is implementation specific. For example, more generally, an N-to-M decoder might 76181-75
- the contents of the ODR 134 are used to control the amount of delay introduced by the delay lines 105A,105B,105C,105D thereby controlling the amount of output delay adjustment.
- the contents of the ODR 134 can be written with a 'Write Output Delay Register' command.
- the controller 10 When the phase detector 11 in the memory controller 10 detects an unacceptable phase difference between its CKI/CKI# and CKO/CKO# signals, the controller 10 will issue one "Write Output Delay Register" command packet with one added unit delay amount to allow the very first memory device 100-1 of Figure 1. After enough clock cycles for a first memory device, for example for the tWODR (Write Output Delay Register latency) and total tIOL latencies described below with respect to Figure 10, if there is still unacceptable phase difference, the controller 10 can issue another 'Write Output Delay Register" command packet to a second memory device, for example the second memory device 100- 2 of Figure 1. This sequence of operations can be continued until the memory 76181-75
- the methods and apparatus described herein have assumed a serial-connected architecture featuring a controller and a set of memory devices connected in a ring.
- the memory devices are slave devices
- the memory controller is a master device.
- the methods and apparatus described herein can be applied to any kind of semiconductor integrated circuit system having any kind of semiconductor integrated circuit devices that are configured as slave devices in the serial-connected configuration with a common interface between adjacent devices, with a device that is configured to act as a master device that controls the duty cycle correction and/or phase correction performed by the slave devices .
Abstract
Description
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Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US12/241,832 US8181056B2 (en) | 2008-09-30 | 2008-09-30 | Serial-connected memory system with output delay adjustment |
US12/241,960 US8161313B2 (en) | 2008-09-30 | 2008-09-30 | Serial-connected memory system with duty cycle correction |
PCT/CA2009/001271 WO2010037205A1 (en) | 2008-09-30 | 2009-09-17 | Serial-connected memory system with output delay adjustment |
Publications (2)
Publication Number | Publication Date |
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EP2329496A1 true EP2329496A1 (en) | 2011-06-08 |
EP2329496A4 EP2329496A4 (en) | 2012-06-13 |
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EP09817125A Withdrawn EP2329496A4 (en) | 2008-09-30 | 2009-09-17 | Serial-connected memory system with output delay adjustment |
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EP (1) | EP2329496A4 (en) |
JP (2) | JP2012504263A (en) |
KR (1) | KR20110081958A (en) |
CN (1) | CN102165529B (en) |
TW (1) | TW201027556A (en) |
WO (1) | WO2010037205A1 (en) |
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US8665665B2 (en) * | 2011-03-30 | 2014-03-04 | Mediatek Inc. | Apparatus and method to adjust clock duty cycle of memory |
US9257164B2 (en) * | 2013-03-14 | 2016-02-09 | Altera Corporation | Circuits and methods for DQS autogating |
JP6232313B2 (en) * | 2014-02-25 | 2017-11-15 | 新日本無線株式会社 | Synchronous serial communication method and slave device |
KR20180033368A (en) * | 2016-09-23 | 2018-04-03 | 삼성전자주식회사 | Electronic device comprising storage devices transmitting reference clock via cascade coupling structure |
KR20190009534A (en) * | 2017-07-19 | 2019-01-29 | 에스케이하이닉스 주식회사 | Semiconductor device |
KR101999125B1 (en) * | 2017-11-24 | 2019-07-11 | 파밀넷 주식회사 | Output signal automatic controller for RS-422 and RS-485 serial communication |
KR20200048607A (en) | 2018-10-30 | 2020-05-08 | 삼성전자주식회사 | System on chip performing training of duty cycle of write clock using mode register write command, operating method of system on chip, electronic device including system on chip |
JP2020155841A (en) * | 2019-03-18 | 2020-09-24 | キオクシア株式会社 | Semiconductor integrated circuit and transmitting device |
US10937468B2 (en) * | 2019-07-03 | 2021-03-02 | Micron Technology, Inc. | Memory with configurable die powerup delay |
CN112332881B (en) * | 2020-10-19 | 2022-04-26 | 深圳市信锐网科技术有限公司 | Enabling circuit and communication device |
CN112698683A (en) * | 2020-12-28 | 2021-04-23 | 深圳市合信自动化技术有限公司 | Method and device for solving error of transmission delay data by configurable bus and PLC |
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Also Published As
Publication number | Publication date |
---|---|
JP2013008386A (en) | 2013-01-10 |
WO2010037205A1 (en) | 2010-04-08 |
KR20110081958A (en) | 2011-07-15 |
EP2329496A4 (en) | 2012-06-13 |
CN102165529B (en) | 2014-12-31 |
TW201027556A (en) | 2010-07-16 |
CN102165529A (en) | 2011-08-24 |
JP5599852B2 (en) | 2014-10-01 |
JP2012504263A (en) | 2012-02-16 |
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