EP2591449A1 - Methods and systems for replaceable synaptic weight storage in neuro-processors - Google Patents
Methods and systems for replaceable synaptic weight storage in neuro-processorsInfo
- Publication number
- EP2591449A1 EP2591449A1 EP11733755.0A EP11733755A EP2591449A1 EP 2591449 A1 EP2591449 A1 EP 2591449A1 EP 11733755 A EP11733755 A EP 11733755A EP 2591449 A1 EP2591449 A1 EP 2591449A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- neuro
- processor chip
- weights
- removable memory
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/831,484 US8676734B2 (en) | 2010-07-07 | 2010-07-07 | Methods and systems for replaceable synaptic weight storage in neuro-processors |
PCT/US2011/043254 WO2012006468A1 (en) | 2010-07-07 | 2011-07-07 | Methods and systems for replaceable synaptic weight storage in neuro-processors |
Publications (1)
Publication Number | Publication Date |
---|---|
EP2591449A1 true EP2591449A1 (en) | 2013-05-15 |
Family
ID=44584777
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP11733755.0A Ceased EP2591449A1 (en) | 2010-07-07 | 2011-07-07 | Methods and systems for replaceable synaptic weight storage in neuro-processors |
Country Status (6)
Country | Link |
---|---|
US (1) | US8676734B2 (en) |
EP (1) | EP2591449A1 (en) |
JP (3) | JP2013534017A (en) |
KR (1) | KR101466251B1 (en) |
CN (1) | CN102971754B (en) |
WO (1) | WO2012006468A1 (en) |
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US20150324691A1 (en) * | 2014-05-07 | 2015-11-12 | Seagate Technology Llc | Neural network connections using nonvolatile memory devices |
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US11100397B2 (en) | 2015-05-21 | 2021-08-24 | Rochester Institute Of Technology | Method and apparatus for training memristive learning systems |
US11226840B2 (en) | 2015-10-08 | 2022-01-18 | Shanghai Zhaoxin Semiconductor Co., Ltd. | Neural network unit that interrupts processing core upon condition |
US11216720B2 (en) | 2015-10-08 | 2022-01-04 | Shanghai Zhaoxin Semiconductor Co., Ltd. | Neural network unit that manages power consumption based on memory accesses per period |
US10664751B2 (en) | 2016-12-01 | 2020-05-26 | Via Alliance Semiconductor Co., Ltd. | Processor with memory array operable as either cache memory or neural network unit memory |
US11029949B2 (en) | 2015-10-08 | 2021-06-08 | Shanghai Zhaoxin Semiconductor Co., Ltd. | Neural network unit |
US11221872B2 (en) | 2015-10-08 | 2022-01-11 | Shanghai Zhaoxin Semiconductor Co., Ltd. | Neural network unit that interrupts processing core upon condition |
US10725934B2 (en) | 2015-10-08 | 2020-07-28 | Shanghai Zhaoxin Semiconductor Co., Ltd. | Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode |
CN114037068A (en) * | 2016-03-21 | 2022-02-11 | 杭州海存信息技术有限公司 | Neural computation circuit using three-dimensional memory to store activation function look-up table |
US11270193B2 (en) | 2016-09-30 | 2022-03-08 | International Business Machines Corporation | Scalable stream synaptic supercomputer for extreme throughput neural networks |
US10489702B2 (en) * | 2016-10-14 | 2019-11-26 | Intel Corporation | Hybrid compression scheme for efficient storage of synaptic weights in hardware neuromorphic cores |
CN108073982B (en) * | 2016-11-18 | 2020-01-03 | 上海磁宇信息科技有限公司 | Brain-like computing system |
US10423876B2 (en) | 2016-12-01 | 2019-09-24 | Via Alliance Semiconductor Co., Ltd. | Processor with memory array operable as either victim cache or neural network unit memory |
US11580373B2 (en) * | 2017-01-20 | 2023-02-14 | International Business Machines Corporation | System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks |
US11238334B2 (en) | 2017-04-04 | 2022-02-01 | Hailo Technologies Ltd. | System and method of input alignment for efficient vector operations in an artificial neural network |
US11551028B2 (en) | 2017-04-04 | 2023-01-10 | Hailo Technologies Ltd. | Structured weight based sparsity in an artificial neural network |
US10387298B2 (en) | 2017-04-04 | 2019-08-20 | Hailo Technologies Ltd | Artificial neural network incorporating emphasis and focus techniques |
US11615297B2 (en) | 2017-04-04 | 2023-03-28 | Hailo Technologies Ltd. | Structured weight based sparsity in an artificial neural network compiler |
US11544545B2 (en) | 2017-04-04 | 2023-01-03 | Hailo Technologies Ltd. | Structured activation based sparsity in an artificial neural network |
US10197971B1 (en) | 2017-08-02 | 2019-02-05 | International Business Machines Corporation | Integrated optical circuit for holographic information processing |
JP6914342B2 (en) * | 2017-09-07 | 2021-08-04 | パナソニック株式会社 | Neural network arithmetic circuit using semiconductor memory element |
US11074499B2 (en) | 2017-11-20 | 2021-07-27 | International Business Machines Corporation | Synaptic weight transfer between conductance pairs with polarity inversion for reducing fixed device asymmetries |
WO2019141902A1 (en) * | 2018-01-17 | 2019-07-25 | Nokia Technologies Oy | An apparatus, a method and a computer program for running a neural network |
CN109886416A (en) * | 2019-02-01 | 2019-06-14 | 京微齐力(北京)科技有限公司 | The System on Chip/SoC and machine learning method of integrated AI's module |
CN112684977A (en) * | 2019-10-18 | 2021-04-20 | 旺宏电子股份有限公司 | Memory device and in-memory computing method thereof |
KR20210047413A (en) | 2019-10-21 | 2021-04-30 | 삼성전자주식회사 | Flash memory device and computing device incuding flash meory cells |
US11270759B2 (en) | 2019-10-21 | 2022-03-08 | Samsung Electronics Co., Ltd. | Flash memory device and computing device including flash memory cells |
KR20210050634A (en) | 2019-10-28 | 2021-05-10 | 삼성전자주식회사 | Memory device, memory system and autonomous driving apparatus |
US11264082B2 (en) | 2019-10-28 | 2022-03-01 | Samsung Electronics Co., Ltd. | Memory device, memory system and autonomous driving apparatus |
US11811421B2 (en) | 2020-09-29 | 2023-11-07 | Hailo Technologies Ltd. | Weights safety mechanism in an artificial neural network processor |
US11221929B1 (en) | 2020-09-29 | 2022-01-11 | Hailo Technologies Ltd. | Data stream fault detection mechanism in an artificial neural network processor |
US11263077B1 (en) | 2020-09-29 | 2022-03-01 | Hailo Technologies Ltd. | Neural network intermediate results safety mechanism in an artificial neural network processor |
US11237894B1 (en) | 2020-09-29 | 2022-02-01 | Hailo Technologies Ltd. | Layer control unit instruction addressing safety mechanism in an artificial neural network processor |
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-
2010
- 2010-07-07 US US12/831,484 patent/US8676734B2/en active Active
-
2011
- 2011-07-07 CN CN201180033657.2A patent/CN102971754B/en active Active
- 2011-07-07 WO PCT/US2011/043254 patent/WO2012006468A1/en active Application Filing
- 2011-07-07 KR KR1020137003298A patent/KR101466251B1/en active IP Right Grant
- 2011-07-07 EP EP11733755.0A patent/EP2591449A1/en not_active Ceased
- 2011-07-07 JP JP2013518841A patent/JP2013534017A/en not_active Withdrawn
-
2015
- 2015-04-01 JP JP2015075223A patent/JP2015167019A/en active Pending
-
2017
- 2017-08-14 JP JP2017156493A patent/JP2018014114A/en active Pending
Non-Patent Citations (2)
Title |
---|
JACOB VOGELSTEIN R ET AL: "Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses", IEEE TRANSACTIONS ON NEURAL NETWORKS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 18, no. 1, 1 January 2007 (2007-01-01), pages 253 - 265, XP011152920, ISSN: 1045-9227, DOI: 10.1109/TNN.2006.883007 * |
See also references of WO2012006468A1 * |
Also Published As
Publication number | Publication date |
---|---|
JP2018014114A (en) | 2018-01-25 |
KR20130036323A (en) | 2013-04-11 |
JP2015167019A (en) | 2015-09-24 |
JP2013534017A (en) | 2013-08-29 |
KR101466251B1 (en) | 2014-11-27 |
US8676734B2 (en) | 2014-03-18 |
US20120011087A1 (en) | 2012-01-12 |
CN102971754A (en) | 2013-03-13 |
WO2012006468A1 (en) | 2012-01-12 |
CN102971754B (en) | 2016-06-22 |
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