US20010001097A1 - Stress-follower circuit configuration - Google Patents
Stress-follower circuit configuration Download PDFInfo
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- US20010001097A1 US20010001097A1 US09/753,646 US75364601A US2001001097A1 US 20010001097 A1 US20010001097 A1 US 20010001097A1 US 75364601 A US75364601 A US 75364601A US 2001001097 A1 US2001001097 A1 US 2001001097A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
Definitions
- the invention is related to transistors, and more particularly, to a stress-follower circuit configuration to protect such transistors.
- transistors may suffer from Electrical Over Stress (EOS), which in this context refers to the application of voltages above the specified safe range of an electrical device, and may result in device degradation. This may occur, for example, when the transistor is employed in the manner using a significantly higher operating voltage than the native process transistors are able to tolerate.
- EOS Electrical Over Stress
- Native process transistors are the basic building blocks of a semiconductor process. For example, a 0.25 micron semiconductor fabrication process may have native transistors with specified operating voltages of 1.8 to 2.5 volts. However, if a technique or approach were devised in which these transistors could tolerate these higher operating voltages, this would allow devices and/or systems operating at higher voltages to be created using this technology.
- legacy devices, components, or systems such as those employing or combining with Peripheral Component Interconnect (PCI), Accelerated Graphics Port (AGP), or Dynamic Random Access Memory (DRAM), for example, employ higher voltages than state-of-the art transistors fabricated using native processes.
- PCI Peripheral Component Interconnect
- AGP Accelerated Graphics Port
- DRAM Dynamic Random Access Memory
- an integrated circuit includes: a stress-follower circuit configuration.
- the stress-follower circuit of the configuration is coupled to a pad of the integrated circuit.
- the stress-follower circuit configuration is coupled so as to reduce the voltage stress on the gate of a transistor in a transistor stack so that in operation the transistor in the stack tolerates an operating voltage approximately 1.5 volts above its nominal voltage.
- the transistor stack is also coupled to the pad.
- FIG. 1 is a circuit diagram illustrating an embodiment of a stress-follower circuit configuration in accordance with the present invention
- FIG. 2 is a circuit diagram of an embodiment of a bias voltage source that may be employed in the embodiment illustrated in FIG.1;
- FIG. 3 is a schematic diagram illustrating an embodiment of a vertical drain metal-oxide transistor (VDMOS), such as may be employed in the embodiment of FIG. 1.
- VDMOS vertical drain metal-oxide transistor
- transistors may suffer from Electrical Over Stress (EOS), which in this context refers to the application of voltages above the specified safe range of an electrical device, and may result in device degradation. This may occur, for example, in a situation in which a transistor is employed at a significantly higher operating voltage than the native process transistors are able to tolerate. Typically, this can occur when the transistors are employed in an interface because this is a common situation in which a particular operating voltage may be employed. Likewise, as is also well-known, operating voltages for circuits, particularly integrated circuits, have been declining over the last few years.
- EOS Electrical Over Stress
- a legacy interface voltage level for input-output (I/O) operation is about 3.3 volts
- DRAM Dynamic Random Access Memory
- the native voltage level is on the order of 1.8 volts, for example.
- I/O input-output
- the transistors could be modified or employed in a manner that allowed them to operate at such legacy interface voltage levels with reliability and with reduced risk of damage due to a high or relatively higher operating voltage.
- FIG. 1 is a circuit diagram illustrating an embodiment 100 of a stress-follower circuit configuration in accordance with the present invention.
- This particular stress-follower circuit configuration embodiment includes the stress-follower circuit embodiment illustrated, and additional components.
- This embodiment is illustrated on an integrated circuit (IC) chip.
- IC integrated circuit
- the invention of course, is not limited in scope to this particular embodiment. Therefore, alternative embodiments may include only an embodiment of a stress-follower circuit in accordance with the invention or more than just an embodiment of a stress-follower circuit, and these alternatives may also be embodied on an IC, embodied on more than one IC, or not embodied on an IC at all, for example.
- a two transistor stack is illustrated as coupled to a voltage V dd .
- these transistors comprise P-channel metal-oxide semiconductor (MOS) transistors, such as 120 and 130 , as illustrated in FIG. 1. Therefore, the stack comprises a pull-up stack; however, the invention is not limited in scope in this respect.
- the stack may comprise N-channel transistors and may operate as a pull-down stack instead.
- bias voltage clamps are applied to the gates of the transistors of the stack.
- an isolation bias 105 is applied to the gate of transistor 120 and a level shifter 140 is applied to the gate of transistor 130 .
- a level shifter in this context comprises a circuit that changes a logical signal at one voltage level to an appropriate voltage level for use elsewhere.
- FIG. 2 illustrates one such embodiment.
- the output voltage in this embodiment is the sum of the voltage across the diode and the voltage across the N-channel metal-oxide semiconductor (NMOS) transistor.
- NMOS N-channel metal-oxide semiconductor
- a bandgap circuit might be employed, although the voltage produced may or may not be useful, depending on the particular embodiment of the invention.
- the bias voltage clamps are coupled in the circuit so that the bias voltage “automatically” accounts or adjusts for pad voltage excursions, that is, pad voltage overshoots or undershoots from the power rails of the circuit.
- the isolation layers comprise oxide gates, although the invention is not limited in scope in this respect.
- Embodiment 100 includes stress-follower circuit 110 .
- the stress-follower circuit when embodied on an IC, the stress-follower circuit is coupled to a pad of the IC, here 150 .
- the stress-follower circuit is coupled here so as to reduce the voltage stress across the gate of the transistors in a two transistor stack, so that in operation the transistors in the stack tolerate an operating voltage exceeding their nominal or native voltage.
- the two transistor stack is also coupled to pad 150 in this particular embodiment.
- the stress-follower circuit allows the transistors in the stack to tolerate an operating voltage approximately 1.5 volts above their nominal voltage.
- transistors 120 and 130 have a nominal or native voltage of approximately 1.8 volts, whereas for this particular embodiment the operating voltage is approximately 3.3 volts.
- the transistors employed comprise vertical drain metal-oxide semiconductors field effect transistors (hereinafter, VDMOS transistors).
- VDMOS transistors may be formed by coupling the drain node of a transistor to the channel of the transistor through a lightly doped well layer which passes underneath a field oxide isolation layer and couples vertically up into the transistor channel. This reduces the high electric field at the drain/gate interface, and allows higher drain voltages without substantial of the transistor gate.
- FIG. 3 comprises a drain and channel formation that allows such transistors to withstand higher voltages than native transistors. For example, in a nominal 1.8 volt fabrication process, it would not be unusual for such transistors to tolerate greater than six volts.
- isolation voltage bias 105 is applied to the gate of transistor 120 of the stack. As illustrated, transistor 120 is directly coupled to pad 150 , whereas transistor 130 is coupled to the pad indirectly via transistor 120 . Furthermore, three VDMOS transistors, 160 , 170 , and 180 , couple pad 150 to isolation bias 105 in this particular embodiment. For example, transistor 180 couples between bias 105 and pad 150 . A bias is applied to the gate of transistor 180 . In this embodiment, the bias voltage applied comprises a semiconductor threshold voltage deviation from a source operating voltage for the integrated circuit, in this embodiment one threshold voltage for an N-channel transistor above V SS . Of course, in an alternative embodiment, such as where a P-channel transistor is employed, for example, a different bias voltage may be applied.
- VDMOS transistors, 160 and 170 for this particular embodiment, as illustrated in FIG. 1, are coupled together with each coupled in a diode configuration. Likewise, these two transistors, 160 and 170 , together couple between pad 150 and isolation bias 105 in this embodiment. It is noted that for the embodiment illustrated in FIG. 1, transistor 175 also comprises a VDMOS transistor, although, again, alternative embodiments are possible and, therefore, the invention is not restricted in scope in this respect.
- the circuit configuration of FIG. 1 is employed to reduce voltage stress on the isolation layers or gates as the pad voltage overshoots or undershoots the power rails for the circuit. For example, when the pad voltage is driven “low,” the stress-follower circuit in this embodiment pulls the voltage of bias 105 lower. Likewise, when the pad voltage overshoots V dd , the stress-follower circuit pulls the bias voltage higher. However, nominally the bias, 105 , is set to the native voltage level.
- transistors 160 and 170 when the pad receives an input voltage signal, transistors 160 and 170 , due at least in part to the diode configuration employed, pull the bias node voltage up, thereby reducing the stress across the gate oxide of transistor 120 .
- the bias node voltage is pulled lower via transistor 180 , to again reduce the stress on the gate oxide of transistor 120 .
- transistor 130 alternatively, its gate in this embodiment is tied, via level shifter 140 , to a semiconductor threshold voltage down from a drain operating voltage, which in this particular embodiment is V dd minus a P-channel transistor threshold voltage.
- the intermediate node designated 115 in FIG. 1
- the drain/gate interface of transistor 120 experiences little or no overstressed.
- node 115 is designed such that it does not drop more than the native process voltage, which in this example is 1.8 volts, although the invention is not limited in scope in this respect, plus one p-channel threshold voltage, down from V dd , then the gate/source interface of device 130 also experiences little or no overstress.
- the voltage stresses at device 130 are maintained in the range of the native process, which in this case is 1.8 volts, although, again, the invention is not limited in scope in this respect.
- This operation also allows the transistor stack to be employed as an MOS clamp for the pad.
- leading edge circuit products may be manufactured using lower voltage native processes and continue to interface with devices, components or systems employing higher, legacy operating voltages, such as, for example, 3.3 volt buses and other such systems.
- An embodiment of a method of reducing the voltage stress on the isolation layer of a transistor coupled to the pad of an integrated circuit in accordance with the present invention is as follows.
- a voltage bias is applied to or coupled to the isolation layer of the transistor, such as illustrated in FIG. 1, for example.
- another port of the transistor such as the drain or source, is coupled to the pad.
- the voltage bias is also coupled to the pad via one or more semiconductor devices capable of tolerating a voltage greater than the nominal transistor operation voltage, such as, for example, as illustrated in FIG. 1, VDMOS transistors. Therefore, as previously explained, the pad bias “automatically” adjusts to reduce the stress on the isolation layer of the transistor.
- the invention is not limited in scope to this particular embodiment.
Abstract
Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a stress-follower circuit configuration. The stress-follower circuit of the configuration is coupled to a pad of the integrated circuit. The stress-follower circuit configuration is coupled so as to reduce the voltage stress on the gate of a transistor in a transistor stack so that in operation the transistor in the stack tolerates an operating voltage approximately 1.5 volts above its nominal voltage. The transistor stack is also coupled to the pad.
Description
- 1. 1. Field
- 2. The invention is related to transistors, and more particularly, to a stress-follower circuit configuration to protect such transistors.
- 3. 2. Background Information
- 4. As is well-known, transistors may suffer from Electrical Over Stress (EOS), which in this context refers to the application of voltages above the specified safe range of an electrical device, and may result in device degradation. This may occur, for example, when the transistor is employed in the manner using a significantly higher operating voltage than the native process transistors are able to tolerate. Native process transistors are the basic building blocks of a semiconductor process. For example, a 0.25 micron semiconductor fabrication process may have native transistors with specified operating voltages of 1.8 to 2.5 volts. However, if a technique or approach were devised in which these transistors could tolerate these higher operating voltages, this would allow devices and/or systems operating at higher voltages to be created using this technology. In today's environment typically legacy devices, components, or systems, such as those employing or combining with Peripheral Component Interconnect (PCI), Accelerated Graphics Port (AGP), or Dynamic Random Access Memory (DRAM), for example, employ higher voltages than state-of-the art transistors fabricated using native processes.
- 5. Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a stress-follower circuit configuration. The stress-follower circuit of the configuration is coupled to a pad of the integrated circuit. The stress-follower circuit configuration is coupled so as to reduce the voltage stress on the gate of a transistor in a transistor stack so that in operation the transistor in the stack tolerates an operating voltage approximately 1.5 volts above its nominal voltage. The transistor stack is also coupled to the pad.
- 6. The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:
- 7.FIG. 1 is a circuit diagram illustrating an embodiment of a stress-follower circuit configuration in accordance with the present invention;
- 8.FIG. 2 is a circuit diagram of an embodiment of a bias voltage source that may be employed in the embodiment illustrated in FIG.1;
- 9.FIG. 3 is a schematic diagram illustrating an embodiment of a vertical drain metal-oxide transistor (VDMOS), such as may be employed in the embodiment of FIG. 1.
- 10. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
- 11. As previously described, and as is well-known, transistors may suffer from Electrical Over Stress (EOS), which in this context refers to the application of voltages above the specified safe range of an electrical device, and may result in device degradation. This may occur, for example, in a situation in which a transistor is employed at a significantly higher operating voltage than the native process transistors are able to tolerate. Typically, this can occur when the transistors are employed in an interface because this is a common situation in which a particular operating voltage may be employed. Likewise, as is also well-known, operating voltages for circuits, particularly integrated circuits, have been declining over the last few years. As a result, a situation has arisen in which transistors are being manufactured in a native process that tolerates a lower operating voltage than legacy interface operating voltage levels for some transistor applications. For example, this is the case in some situations for interfaces that comply with, for example, the Peripheral Component Interconnect (PCI) Specification, version 2.1, available from the PCI Special Interest Group, 2575 NE Kathryn St #17, Hillsboro, Oreg. 97124, December 1997, the Accelerated Graphics Port (APG) Interface Specification,
version 1, dated Aug. 1, 1996, or version 2.0, dated May 4, 1998, available from, for example, the AGP Implementors Forum or Intel Corp, or that comply with Dynamic Random Access Memory (DRAM), which may employ in the range of 3 to 5 volts. In one particular situation, although the intention is not limited in scope to this particular situation, a legacy interface voltage level for input-output (I/O) operation is about 3.3 volts, whereas in some state-of-the art transistor fabrication processes the native voltage level is on the order of 1.8 volts, for example. Of course, it is not intended to limit the scope of the invention to state-of-the-art fabrication processes. It would be desirable if the transistors could be modified or employed in a manner that allowed them to operate at such legacy interface voltage levels with reliability and with reduced risk of damage due to a high or relatively higher operating voltage. - 12.FIG. 1 is a circuit diagram illustrating an
embodiment 100 of a stress-follower circuit configuration in accordance with the present invention. This particular stress-follower circuit configuration embodiment includes the stress-follower circuit embodiment illustrated, and additional components. This embodiment is illustrated on an integrated circuit (IC) chip. The invention, of course, is not limited in scope to this particular embodiment. Therefore, alternative embodiments may include only an embodiment of a stress-follower circuit in accordance with the invention or more than just an embodiment of a stress-follower circuit, and these alternatives may also be embodied on an IC, embodied on more than one IC, or not embodied on an IC at all, for example. For the embodiment illustrated in FIG. 1, a two transistor stack is illustrated as coupled to a voltage Vdd. In this particular embodiment, these transistors comprise P-channel metal-oxide semiconductor (MOS) transistors, such as 120 and 130, as illustrated in FIG. 1. Therefore, the stack comprises a pull-up stack; however, the invention is not limited in scope in this respect. For example, alternatively, the stack may comprise N-channel transistors and may operate as a pull-down stack instead. For the embodiment illustrated in FIG. 1, bias voltage clamps are applied to the gates of the transistors of the stack. For example, anisolation bias 105 is applied to the gate oftransistor 120 and alevel shifter 140 is applied to the gate oftransistor 130. A level shifter in this context comprises a circuit that changes a logical signal at one voltage level to an appropriate voltage level for use elsewhere. As only one example, it may change ground to a 1.8 voltage signals used in core logic to 1.5 to 3.3 voltage signal levels used in an output circuit. Level-shifters are well-known circuit blocks and need not be described in additional detail here. Any one of a variety of possibilities will provide satisfactory operation. Circuit configurations for producing a bias voltage source are also well-known in the art and will not be described in great detail here. Any one of a variety of bias voltage sources or bias generator circuits may be employed. FIG. 2, without limitation, illustrates one such embodiment. The output voltage in this embodiment is the sum of the voltage across the diode and the voltage across the N-channel metal-oxide semiconductor (NMOS) transistor. In addition, as another example, a bandgap circuit might be employed, although the voltage produced may or may not be useful, depending on the particular embodiment of the invention. As shall be explained in greater detail below, the bias voltage clamps are coupled in the circuit so that the bias voltage “automatically” accounts or adjusts for pad voltage excursions, that is, pad voltage overshoots or undershoots from the power rails of the circuit. In this particular embodiment in accordance with the invention, it is desirable to reduce the stress due to voltage on the isolation layers or gates oftransistors - 13.
Embodiment 100, as illustrated in FIG. 1, includes stress-follower circuit 110. As illustrated in this particular embodiment, when embodied on an IC, the stress-follower circuit is coupled to a pad of the IC, here 150. As previously suggested, the stress-follower circuit is coupled here so as to reduce the voltage stress across the gate of the transistors in a two transistor stack, so that in operation the transistors in the stack tolerate an operating voltage exceeding their nominal or native voltage. Likewise, the two transistor stack is also coupled to pad 150 in this particular embodiment. In this particular embodiment, the stress-follower circuit allows the transistors in the stack to tolerate an operating voltage approximately 1.5 volts above their nominal voltage. For example, although the invention is not limited in scope in this respect,transistors - 14. For the stress-follower circuit illustrated in FIG. 1, the transistors employed comprise vertical drain metal-oxide semiconductors field effect transistors (hereinafter, VDMOS transistors). Of course, the invention is not limited in scope in this respect. In one embodiment, VDMOS transistors may be formed by coupling the drain node of a transistor to the channel of the transistor through a lightly doped well layer which passes underneath a field oxide isolation layer and couples vertically up into the transistor channel. This reduces the high electric field at the drain/gate interface, and allows higher drain voltages without substantial of the transistor gate. This embodiment is illustrated in FIG. 3 and comprises a drain and channel formation that allows such transistors to withstand higher voltages than native transistors. For example, in a nominal 1.8 volt fabrication process, it would not be unusual for such transistors to tolerate greater than six volts.
- 15. For the embodiment illustrated in FIG. 1,
isolation voltage bias 105 is applied to the gate oftransistor 120 of the stack. As illustrated,transistor 120 is directly coupled to pad 150, whereastransistor 130 is coupled to the pad indirectly viatransistor 120. Furthermore, three VDMOS transistors, 160, 170, and 180,couple pad 150 toisolation bias 105 in this particular embodiment. For example, transistor 180 couples betweenbias 105 andpad 150. A bias is applied to the gate of transistor 180. In this embodiment, the bias voltage applied comprises a semiconductor threshold voltage deviation from a source operating voltage for the integrated circuit, in this embodiment one threshold voltage for an N-channel transistor above VSS. Of course, in an alternative embodiment, such as where a P-channel transistor is employed, for example, a different bias voltage may be applied. Likewise, two VDMOS transistors, 160 and 170 for this particular embodiment, as illustrated in FIG. 1, are coupled together with each coupled in a diode configuration. Likewise, these two transistors, 160 and 170, together couple betweenpad 150 andisolation bias 105 in this embodiment. It is noted that for the embodiment illustrated in FIG. 1,transistor 175 also comprises a VDMOS transistor, although, again, alternative embodiments are possible and, therefore, the invention is not restricted in scope in this respect. - 16. As previously indicated, the circuit configuration of FIG. 1 is employed to reduce voltage stress on the isolation layers or gates as the pad voltage overshoots or undershoots the power rails for the circuit. For example, when the pad voltage is driven “low,” the stress-follower circuit in this embodiment pulls the voltage of
bias 105 lower. Likewise, when the pad voltage overshoots Vdd, the stress-follower circuit pulls the bias voltage higher. However, nominally the bias, 105, is set to the native voltage level. - 17. Specifically, on voltage overshoots above Vdd, when the pad receives an input voltage signal,
transistors transistor 120. Alternatively, if the pad voltage undershoots, the bias node voltage is pulled lower via transistor 180, to again reduce the stress on the gate oxide oftransistor 120. Fortransistor 130, alternatively, its gate in this embodiment is tied, vialevel shifter 140, to a semiconductor threshold voltage down from a drain operating voltage, which in this particular embodiment is Vdd minus a P-channel transistor threshold voltage. When the voltage ofpad 150 undershoots, the intermediate node, designated 115 in FIG. 1, is also pulled somewhat lower. Thus, the drain/gate interface oftransistor 120 experiences little or no overstressed. If node 115 is designed such that it does not drop more than the native process voltage, which in this example is 1.8 volts, although the invention is not limited in scope in this respect, plus one p-channel threshold voltage, down from Vdd, then the gate/source interface ofdevice 130 also experiences little or no overstress. Thus, the voltage stresses atdevice 130 are maintained in the range of the native process, which in this case is 1.8 volts, although, again, the invention is not limited in scope in this respect. This operation also allows the transistor stack to be employed as an MOS clamp for the pad. In this regard, see, for example, U.S. Pat. No. 5,546,016, titled “MOS Termination for Low Power Signaling,” by M. Allen, issued Jul. 3, 1995, assigned to the assignee of the present invention. - 18. One advantage of this embodiment is that it allows a significantly higher operating voltage relative to native process voltage capability with acceptable EOS and reliability risk. Whereas typical approaches allow about 1.4 times operating voltage over native voltage, this approach allows two times operating voltage over native voltage. Other advantages of this approach is neither extra pins nor power supplies are employed to achieve its results. Therefore, by employing this particular embodiment, leading edge circuit products may be manufactured using lower voltage native processes and continue to interface with devices, components or systems employing higher, legacy operating voltages, such as, for example, 3.3 volt buses and other such systems.
- 19. An embodiment of a method of reducing the voltage stress on the isolation layer of a transistor coupled to the pad of an integrated circuit in accordance with the present invention is as follows. A voltage bias is applied to or coupled to the isolation layer of the transistor, such as illustrated in FIG. 1, for example. Likewise, another port of the transistor, such as the drain or source, is coupled to the pad. The voltage bias is also coupled to the pad via one or more semiconductor devices capable of tolerating a voltage greater than the nominal transistor operation voltage, such as, for example, as illustrated in FIG. 1, VDMOS transistors. Therefore, as previously explained, the pad bias “automatically” adjusts to reduce the stress on the isolation layer of the transistor. Of course, the invention is not limited in scope to this particular embodiment.
- 20. While certain features of the invention have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
Claims (15)
1. An integrated circuit comprising:
a stress-follower circuit configuration;
the stress-follower circuit of the configuration being coupled to a pad of the integrated circuit;
the stress-follower circuit configuration being coupled so as to reduce the voltage stress on an isolation layer of a transistor in a transistor stack so that in operation the transistor in the stack tolerates approximately 1.5 volts above its nominal voltage;
the transistor stack also being coupled to the pad.
2. The integrated circuit of , wherein the isolation layer comprises a gate and the transistors in the transistor stack comprise metal-oxide semiconductor transistors.
claim 1
3. The integrated circuit of , wherein the nominal voltage comprises approximately 1.8 volts and the operating voltage comprises approximately 3.3 volts.
claim 2
4. The integrated circuit of , wherein the transistors of said stress-follower circuit comprise vertical drain metal-oxide semiconductor field effect transistors (VDMOS transistors).
claim 2
5. The integrated circuit of , wherein the stress-follower circuit comprises three VDMOS transistors;
claim 4
the integrated circuit further comprising a voltage bias applied to the gate of the transistor of said stack that is directly coupled to said pad;
one of said VDMOS transistors coupling said pad to said voltage bias, said one VDMOS transistor having a voltage bias applied to its gate;
the remaining VDMOS transistors being coupled together, each in a diode configuration, and also coupling said pad to said voltage bias.
6. The integrated circuit of , wherein the voltage bias applied to said one VDMOS transistor comprises a threshold voltage deviation from a source operating voltage for said integrated circuit.
claim 5
7. The integrated circuit of , wherein a voltage bias applied to the other transistor of said stack comprises a threshold voltage from a drain operating voltage for said integrated circuit.
claim 6
8. The integrated circuit of , wherein the transistor stack comprises one of a p-channel transistor stack and an n-channel transistor stack.
claim 2
9. The integrated circuit of , wherein the transistor stack comprises a two transistor stack;
claim 2
the stress-follower circuit configuration being coupled to reduce the voltage stress on the gate of both transistors in the stack.
10. A method of reducing the voltage stress on the isolation layer of a transistor coupled to the pad of an integrated circuit including the transistor comprising:
coupling the isolation layer of the transistor to a voltage bias and coupling another port of the transistor to the pad; and
coupling the voltage bias to the pad via one or more semiconductor devices capable of tolerating a voltage greater than the nominal transistor operating voltage.
11. The method of , wherein the transistor comprises a metal-oxide semiconductor transistor, the isolation layer comprises a gate and the other port comprises one of a drain and a source.
claim 10
12. The method of , wherein the one or more semiconductor devices capable of tolerating a voltage greater than the nominal transistor operating voltage comprise one or more vertical drain metal-oxide semiconductor transistors.
claim 11
13. An stress-follower circuit configuration for an integrated circuit comprising:
a transistor stack;
means for reducing the voltage stress on the gate of a transistor, the voltage stress reduction means being coupled to a pad of the integrated circuit;
the transistor stack also being coupled to the pad.
14. The stress-follower circuit of , wherein the transistor stack comprises one of a pull-up and a pull-down stack.
claim 13
15. The stress-follower circuit of , wherein the transistor stack comprises a two transistor stack.
claim 13
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/753,646 US6285537B2 (en) | 1998-06-11 | 2001-01-02 | Stress-follower circuit configuration |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/096,283 US6351358B1 (en) | 1998-06-11 | 1998-06-11 | Stress-follower circuit configuration |
US09/753,646 US6285537B2 (en) | 1998-06-11 | 2001-01-02 | Stress-follower circuit configuration |
Related Parent Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US9628698A Continuation | 1998-06-11 | 1998-06-11 | |
US09/096,283 Continuation US6351358B1 (en) | 1998-06-11 | 1998-06-11 | Stress-follower circuit configuration |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010001097A1 true US20010001097A1 (en) | 2001-05-10 |
US6285537B2 US6285537B2 (en) | 2001-09-04 |
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/096,283 Expired - Lifetime US6351358B1 (en) | 1998-06-11 | 1998-06-11 | Stress-follower circuit configuration |
US09/753,646 Expired - Fee Related US6285537B2 (en) | 1998-06-11 | 2001-01-02 | Stress-follower circuit configuration |
US10/015,727 Expired - Lifetime US6643110B2 (en) | 1998-06-11 | 2001-11-01 | Stress-follower circuit configuration |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/096,283 Expired - Lifetime US6351358B1 (en) | 1998-06-11 | 1998-06-11 | Stress-follower circuit configuration |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/015,727 Expired - Lifetime US6643110B2 (en) | 1998-06-11 | 2001-11-01 | Stress-follower circuit configuration |
Country Status (6)
Country | Link |
---|---|
US (3) | US6351358B1 (en) |
AU (1) | AU3878499A (en) |
DE (1) | DE19983293B4 (en) |
GB (1) | GB2355121B (en) |
HK (2) | HK1056268A1 (en) |
WO (1) | WO1999065130A1 (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4648533B2 (en) * | 2000-10-30 | 2011-03-09 | Okiセミコンダクタ株式会社 | Semiconductor device |
US6803801B2 (en) * | 2002-11-07 | 2004-10-12 | Lsi Logic Corporation | CMOS level shifters using native devices |
US7411415B2 (en) * | 2004-02-25 | 2008-08-12 | Ashfaq Shaikh | Bus termination scheme having concurrently powered-on transistors |
US7812638B2 (en) * | 2007-09-06 | 2010-10-12 | National Sun Yat-Sen University | Input output device for mixed-voltage tolerant |
US8022729B2 (en) | 2008-04-11 | 2011-09-20 | Micron Technology, Inc. | Signal driver circuit having adjustable output voltage for a high logic level output signal |
US7839174B2 (en) * | 2008-12-09 | 2010-11-23 | Himax Technologies Limited | Mixed-voltage tolerant I/O buffer and output buffer circuit thereof |
US8421501B1 (en) * | 2011-12-07 | 2013-04-16 | Arm Limited | Digital data handling in a circuit powered in a high voltage domain and formed from devices designed for operation in a lower voltage domain |
US9219473B2 (en) | 2013-03-15 | 2015-12-22 | International Business Machines Corporation | Overvoltage protection circuit |
US8766675B1 (en) | 2013-03-15 | 2014-07-01 | International Business Machines Corporation | Overvoltage protection circuit |
US9117547B2 (en) | 2013-05-06 | 2015-08-25 | International Business Machines Corporation | Reduced stress high voltage word line driver |
US9401711B2 (en) | 2014-11-14 | 2016-07-26 | International Business Machines Corporation | Driver output with dynamic switching bias |
CN106325352B (en) * | 2015-06-30 | 2019-01-29 | 奇景光电股份有限公司 | Output-stage circuit |
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US5381062A (en) * | 1993-10-28 | 1995-01-10 | At&T Corp. | Multi-voltage compatible bidirectional buffer |
GB9419689D0 (en) * | 1994-09-29 | 1994-11-16 | Inmos Ltd | Off-chip driver circuit |
US5576635A (en) * | 1995-02-14 | 1996-11-19 | Advanced Micro Devices, Inc. | Output buffer with improved tolerance to overvoltage |
US5546016A (en) | 1995-07-03 | 1996-08-13 | Intel Corporation | MOS termination for low power signaling |
US5726589A (en) * | 1995-11-01 | 1998-03-10 | International Business Machines Corporation | Off-chip driver circuit with reduced hot-electron degradation |
US5892371A (en) * | 1996-02-12 | 1999-04-06 | Advanced Micro Devices, Inc. | Gate oxide voltage limiting devices for digital circuits |
US5736869A (en) * | 1996-05-16 | 1998-04-07 | Lsi Logic Corporation | Output driver with level shifting and voltage protection |
US5874838A (en) * | 1996-06-13 | 1999-02-23 | Cypress Semiconductor Corporation | High voltage-tolerant low voltage input/output cell |
US5874836A (en) * | 1996-09-06 | 1999-02-23 | International Business Machines Corporation | High reliability I/O stacked fets |
US5804998A (en) * | 1996-12-26 | 1998-09-08 | International Business Machines Corporation | Voltage upwardly compliant CMOS off-chip driver |
US6028449A (en) * | 1997-08-05 | 2000-02-22 | Lsi Logic Corporation | Integrated circuit I/O buffer having pull-up to voltages greater than transistor tolerance |
US5952875A (en) * | 1997-09-09 | 1999-09-14 | Motorola Inc. | Circuit with hot electron protection and method |
US5852540A (en) * | 1997-09-24 | 1998-12-22 | Intel Corporation | Circuit for protecting the input/output stage of a low voltage integrated circuit device from a failure of the internal voltage supply or a difference in the power-up sequencing of supply voltage levels |
US6054875A (en) | 1997-12-31 | 2000-04-25 | Intel Corporation | Output buffer for a mixed voltage environment |
TW428253B (en) * | 1998-04-20 | 2001-04-01 | United Microelectronics Corp | Buried channel vertical doubly-diffused metal oxide semiconductor device |
-
1998
- 1998-06-11 US US09/096,283 patent/US6351358B1/en not_active Expired - Lifetime
-
1999
- 1999-05-03 AU AU38784/99A patent/AU3878499A/en not_active Abandoned
- 1999-05-03 DE DE19983293T patent/DE19983293B4/en not_active Expired - Fee Related
- 1999-05-03 GB GB0029868A patent/GB2355121B/en not_active Expired - Fee Related
- 1999-05-03 WO PCT/US1999/009672 patent/WO1999065130A1/en active Application Filing
-
2001
- 2001-01-02 US US09/753,646 patent/US6285537B2/en not_active Expired - Fee Related
- 2001-05-11 HK HK03108550A patent/HK1056268A1/en not_active IP Right Cessation
- 2001-05-11 HK HK01103302A patent/HK1032684A1/en not_active IP Right Cessation
- 2001-11-01 US US10/015,727 patent/US6643110B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
GB2355121A (en) | 2001-04-11 |
US6643110B2 (en) | 2003-11-04 |
US6351358B1 (en) | 2002-02-26 |
GB2355121B (en) | 2003-09-17 |
US20020044400A1 (en) | 2002-04-18 |
WO1999065130A1 (en) | 1999-12-16 |
HK1032684A1 (en) | 2001-07-27 |
DE19983293T1 (en) | 2001-05-10 |
US6285537B2 (en) | 2001-09-04 |
AU3878499A (en) | 1999-12-30 |
DE19983293B4 (en) | 2006-08-31 |
GB0029868D0 (en) | 2001-01-24 |
HK1056268A1 (en) | 2004-02-06 |
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