US20010010406A1 - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- US20010010406A1 US20010010406A1 US09/811,795 US81179501A US2001010406A1 US 20010010406 A1 US20010010406 A1 US 20010010406A1 US 81179501 A US81179501 A US 81179501A US 2001010406 A1 US2001010406 A1 US 2001010406A1
- Authority
- US
- United States
- Prior art keywords
- conductive contacts
- bonding pads
- tape layer
- dielectric tape
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the invention relates to a semiconductor device and method for manufacturing the same, more particularly to a semiconductor device that can be produced at a relatively low manufacturing cost and with a relatively high production yield.
- a conventional semiconductor device 1 is shown to comprise a semiconductor chip 10 , a dielectric tape layer 2 and a printed circuit board 3 .
- the semiconductor chip 10 has a pad mounting surface 12 with a plurality of bonding pads 11 provided thereon.
- the dielectric tape layer 2 has an adhesive surface 21 adhered onto the pad mounting surface 12 of the semiconductor chip 10 , and a plurality of holes 20 that are registered with the bonding pads 11 to expose the latter.
- the dielectric tape layer 2 further has a wire mounting surface 22 opposite to the adhesive surface 21 .
- a plurality of wires 23 that traverse the holes 20 are disposed on the wire mounting surface 22 .
- a wire-bonding machine (not shown) processes the portions of the wires 23 that traverse the holes 20 (in the direction of the arrows shown in FIG. 1) so as to bond the wires 23 to the bonding pads 11 in the holes 20 .
- solder balls 24 are subsequently formed on the wires 23 .
- the printed circuit board 3 has a circuit layout surface 30 formed with circuit traces 31 that bond with the solder balls 24 to establish electrical connection between the circuit traces 31 and the bonding pads 11 via the solder balls 24 and the wires 23 .
- the wires 23 are susceptible to oxidation and corrosion because they are exposed to air, thereby affecting reliability of the semiconductor device 1 .
- solder balls 24 are needed to establish connection between the circuit traces 31 on the printed circuit board 3 and the semiconductor chip 10 .
- the solder balls 24 are liable to drop off or form unstable electrical contacts, thereby affecting adversely the production yield.
- solder balls 24 are used to connect the printed circuit board 3 and the semiconductor chip 10 , the contact area between the printed circuit board 3 and the semiconductor chip 10 is relatively small and can lead to eventual undesired separation between the printed circuit board 3 and the semiconductor chip 10 .
- the main object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device capable of overcoming the aforesaid drawbacks that are associated with the prior art.
- a semiconductor device comprises:
- a semiconductor chip having a pad mounting surface with a plurality of bonding pads provided thereon;
- a dielectric tape layer having opposite first and second adhesive surfaces, the first adhesive surface being adhered onto the pad mounting surface of the semiconductor chip, the dielectric tape layer being formed with a plurality of holes at positions registered with the bonding pads to expose the bonding pads, each of the holes being confined by a wall that cooperates with a registered one of the bonding pads to form a contact receiving space;
- a printed circuit board having a circuit layout surface adhered onto the second adhesive surface of the dielectric tape layer, the circuit layout surface being formed with circuit traces that are bonded to the conductive contacts to establish electrical connection with the bonding pads.
- a method for manufacturing a semiconductor device comprises:
- the second adhesive surface is provided with a heat-curable adhesive having a curing point that is lower than melting point of the conductive contacts.
- adhering of the printed circuit board onto the dielectric tape layer and bonding of the circuit traces to the conductive contacts can be performed simultaneously via a heat curing operation such that the circuit layout surface is already adhered onto the second adhesive layer prior to melting of the conductive contacts.
- FIG. 1 is a partly exploded fragmentary schematic view illustrating a conventional semiconductor device
- FIG. 2 is a fragmentary schematic view of the conventional semiconductor device of FIG. 1;
- FIGS. 3 to 5 are fragmentary schematic views illustrating the steps of the method for manufacturing the first preferred embodiment of a semiconductor device according to the present invention
- FIG. 6 is a fragmentary schematic view illustrating an intermediate product of the second preferred embodiment of a method for manufacturing a semiconductor device according to the present invention.
- FIGS. 7 and 8 are fragmentary schematic views illustrating some of the steps of the method for manufacturing the third preferred embodiment of a semiconductor device according to the present invention.
- the first preferred embodiment of a semiconductor device 4 is shown to comprise a semiconductor chip 40 , a dielectric tape layer 5 and a printed circuit board 6 .
- the semiconductor chip 40 has a pad mounting surface 42 with a plurality of bonding pads 41 provided thereon.
- the dielectric tape layer 5 has opposite first and second adhesive surfaces 50 , 51 .
- a heat-curable adhesive 55 is provided on the first adhesive surface 50 such that the first adhesive surface 50 can be adhered onto the pad mounting surface 42 of the semiconductor chip 40 during a heat curing operation.
- a conventional laser cutting technique is employed to form a plurality of holes 52 in the dielectric tape layer 5 at positions registered with the bonding pads 41 to expose the latter.
- Each of the holes 52 is confined by a wall 53 that cooperates with a registered one of the bonding pads 41 to form a contact receiving space.
- a plurality of conductive contacts 54 are placed in the contact receiving spaces, respectively.
- a tin ball is planted in each contact receiving space and serves as a conductive contact 54 .
- the printed circuit board 6 has a circuit layout surface 60 formed with circuit traces 61 that are to be connected to the conductive contacts 54 .
- a heat curing operation is conducted to bond the conductive contacts 54 to the circuit traces 61 , and to adhere the circuit layout surface 60 onto the second adhesive surface 51 of the dielectric tape layer 50 .
- the second adhesive surface 51 is provided with a heat-curable adhesive 55 having a curing point that is lower than the melting point of the conductive contacts 54 .
- the circuit layout surface 60 is already adhered onto the second adhesive surface 51 prior to melting of the conductive contacts 54 , thereby sealing the contact receiving spaces so that the melt of each conductive contact 54 is prevented from flowing out of the respective contact receiving space to avoid formation of undesired connections with adjacent conductive contacts 54 .
- each contact 54 ′ is formed from conductive paste, such as conductive silver paste.
- each contact 54 ′′ is formed by placing a conductive metal material 56 , such as a gold or aluminum ball, in each contact receiving space. A chemical electroplating process is subsequently performed to complete each contact 54 ′′ prior to bonding with the circuit traces on the printed circuit board (not shown).
- a conductive metal material 56 such as a gold or aluminum ball
- the printed circuit board 6 can be mounted directly on the dielectric tape layer 5 with a relatively large contact area therebetween to prevent undesired separation of the printed circuit board 6 from the dielectric tape layer 5 .
- the production yield can be substantially higher as compared to the conventional semiconductor device that uses solder balls.
Abstract
A semiconductor device includes a semiconductor chip, a dielectric tape layer and a printed circuit board. The semiconductor chip has a pad mounting surface with a plurality of bonding pads provided thereon. The dielectric tape layer has opposite first and second adhesive surfaces. The first adhesive surface is adhered onto the pad mounting surface of the semiconductor chip. The dielectric tape layer is formed with a plurality of holes at positions registered with the bonding pads to expose the bonding pads. Each of the holes is confined by a wall that cooperates with a registered one of the bonding pads to form a contact receiving space. A plurality of conductive contacts are placed in the contact receiving spaces, respectively. The printed circuit board has a circuit layout surface adhered onto the second adhesive surface of the dielectric tape layer. The circuit layout surface is formed with circuit traces that are bonded to the conductive contacts to establish electrical connection with the bonding pads. A method for manufacturing the semiconductor device is also disclosed.
Description
- 1. Field of the Invention
- The invention relates to a semiconductor device and method for manufacturing the same, more particularly to a semiconductor device that can be produced at a relatively low manufacturing cost and with a relatively high production yield.
- 2. Description of the Related Art
- Referring to FIGS. 1 and 2, a conventional semiconductor device1 is shown to comprise a
semiconductor chip 10, adielectric tape layer 2 and a printedcircuit board 3. - The
semiconductor chip 10 has apad mounting surface 12 with a plurality ofbonding pads 11 provided thereon. Thedielectric tape layer 2 has anadhesive surface 21 adhered onto thepad mounting surface 12 of thesemiconductor chip 10, and a plurality ofholes 20 that are registered with thebonding pads 11 to expose the latter. Thedielectric tape layer 2 further has awire mounting surface 22 opposite to theadhesive surface 21. A plurality ofwires 23 that traverse theholes 20 are disposed on thewire mounting surface 22. A wire-bonding machine (not shown) processes the portions of thewires 23 that traverse the holes 20 (in the direction of the arrows shown in FIG. 1) so as to bond thewires 23 to thebonding pads 11 in theholes 20.Solder balls 24 are subsequently formed on thewires 23. The printedcircuit board 3 has acircuit layout surface 30 formed withcircuit traces 31 that bond with thesolder balls 24 to establish electrical connection between thecircuit traces 31 and thebonding pads 11 via thesolder balls 24 and thewires 23. - Some of the drawbacks of the conventional semiconductor device1 are as follows:
- 1. An expensive wire-bonding machine is needed to establish connection between the
wires 23 and thebonding pads 11, thereby increasing the production costs. Also, defective products are produced during the wire-bonding operation due to inadequacies of the latter. Particularly, defective products are formed when wires break during the wire-bonding operation, thereby reducing the production yield. - 2. The
wires 23 are susceptible to oxidation and corrosion because they are exposed to air, thereby affecting reliability of the semiconductor device 1. - 3.
Solder balls 24 are needed to establish connection between thecircuit traces 31 on the printedcircuit board 3 and thesemiconductor chip 10. Thesolder balls 24 are liable to drop off or form unstable electrical contacts, thereby affecting adversely the production yield. - 4. Because
solder balls 24 are used to connect the printedcircuit board 3 and thesemiconductor chip 10, the contact area between theprinted circuit board 3 and thesemiconductor chip 10 is relatively small and can lead to eventual undesired separation between the printedcircuit board 3 and thesemiconductor chip 10. - Therefore, the main object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device capable of overcoming the aforesaid drawbacks that are associated with the prior art.
- According to one aspect of the present invention, a semiconductor device comprises:
- a semiconductor chip having a pad mounting surface with a plurality of bonding pads provided thereon;
- a dielectric tape layer having opposite first and second adhesive surfaces, the first adhesive surface being adhered onto the pad mounting surface of the semiconductor chip, the dielectric tape layer being formed with a plurality of holes at positions registered with the bonding pads to expose the bonding pads, each of the holes being confined by a wall that cooperates with a registered one of the bonding pads to form a contact receiving space;
- a plurality of conductive contacts placed in the contact receiving spaces, respectively; and
- a printed circuit board having a circuit layout surface adhered onto the second adhesive surface of the dielectric tape layer, the circuit layout surface being formed with circuit traces that are bonded to the conductive contacts to establish electrical connection with the bonding pads.
- According to another aspect of the present invention, a method for manufacturing a semiconductor device comprises:
- adhering a first adhesive surface of a dielectric tape layer onto a pad mounting surface of a semiconductor chip, the dielectric tape layer being formed with a plurality of holes at positions registered with bonding pads provided on the pad mounting surface to expose the bonding pads, each of the holes being confined by a wall that cooperates with a registered one of the bonding pads to form a contact receiving space;
- placing a plurality of conductive contacts in the contact receiving spaces, respectively; and
- adhering a circuit layout surface of a printed circuit board onto a second adhesive surface of the dielectric tape layer opposite to the first adhesive surface, and bonding circuit traces formed on the circuit layout surface to the conductive contacts to establish electrical connection with the bonding pads.
- Preferably, the second adhesive surface is provided with a heat-curable adhesive having a curing point that is lower than melting point of the conductive contacts. Thus, adhering of the printed circuit board onto the dielectric tape layer and bonding of the circuit traces to the conductive contacts can be performed simultaneously via a heat curing operation such that the circuit layout surface is already adhered onto the second adhesive layer prior to melting of the conductive contacts.
- Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which:
- FIG. 1 is a partly exploded fragmentary schematic view illustrating a conventional semiconductor device;
- FIG. 2 is a fragmentary schematic view of the conventional semiconductor device of FIG. 1;
- FIGS.3 to 5 are fragmentary schematic views illustrating the steps of the method for manufacturing the first preferred embodiment of a semiconductor device according to the present invention;
- FIG. 6 is a fragmentary schematic view illustrating an intermediate product of the second preferred embodiment of a method for manufacturing a semiconductor device according to the present invention; and
- FIGS. 7 and 8 are fragmentary schematic views illustrating some of the steps of the method for manufacturing the third preferred embodiment of a semiconductor device according to the present invention.
- Referring to FIGS.3 to 5, the first preferred embodiment of a
semiconductor device 4 according to the present invention is shown to comprise asemiconductor chip 40, adielectric tape layer 5 and a printedcircuit board 6. - The
semiconductor chip 40 has apad mounting surface 42 with a plurality ofbonding pads 41 provided thereon. Thedielectric tape layer 5 has opposite first and secondadhesive surfaces curable adhesive 55 is provided on the firstadhesive surface 50 such that the firstadhesive surface 50 can be adhered onto thepad mounting surface 42 of thesemiconductor chip 40 during a heat curing operation. A conventional laser cutting technique is employed to form a plurality ofholes 52 in thedielectric tape layer 5 at positions registered with thebonding pads 41 to expose the latter. - Each of the
holes 52 is confined by awall 53 that cooperates with a registered one of thebonding pads 41 to form a contact receiving space. A plurality ofconductive contacts 54 are placed in the contact receiving spaces, respectively. In this embodiment, a tin ball is planted in each contact receiving space and serves as aconductive contact 54. - The printed
circuit board 6 has acircuit layout surface 60 formed withcircuit traces 61 that are to be connected to theconductive contacts 54. A heat curing operation is conducted to bond theconductive contacts 54 to thecircuit traces 61, and to adhere thecircuit layout surface 60 onto the secondadhesive surface 51 of thedielectric tape layer 50. Preferably, the secondadhesive surface 51 is provided with a heat-curable adhesive 55 having a curing point that is lower than the melting point of theconductive contacts 54. Thus, thecircuit layout surface 60 is already adhered onto the secondadhesive surface 51 prior to melting of theconductive contacts 54, thereby sealing the contact receiving spaces so that the melt of eachconductive contact 54 is prevented from flowing out of the respective contact receiving space to avoid formation of undesired connections with adjacentconductive contacts 54. - Referring to FIG. 6, in the second preferred embodiment of a semiconductor device according to the present invention, instead of using tin balls as conductive contacts, each
contact 54′ is formed from conductive paste, such as conductive silver paste. - Referring to FIGS. 7 and 8, in the third preferred embodiment of a semiconductor device according to the present invention, each
contact 54″ is formed by placing aconductive metal material 56, such as a gold or aluminum ball, in each contact receiving space. A chemical electroplating process is subsequently performed to complete eachcontact 54″ prior to bonding with the circuit traces on the printed circuit board (not shown). - While the preferred embodiments as hereinbefore described involve only one
semiconductor chip 40 on the printedcircuit board 6, it should be noted that, in practice, two ormore semiconductor chips 40 may be mounted on the printedcircuit board 6 according to the actual requirements. - Some of the advantageous attributes of the
semiconductor device 4 according to this invention are as follows: - 1. Since no wire-bonding machine is required, the production costs can be dramatically reduced. Moreover, the adverse effects of wire bonding on the production yield of the
semiconductor device 4 are also eliminated. - 2. Because the
conductive contacts circuit board 6 and thedielectric tape layer 5, theconductive contacts - 3. Because no solder balls are present between the
circuit layout surface 60 of the printedcircuit board 6 and the secondadhesive surface 51 of thedielectric tape layer 5, the printedcircuit board 6 can be mounted directly on thedielectric tape layer 5 with a relatively large contact area therebetween to prevent undesired separation of the printedcircuit board 6 from thedielectric tape layer 5. - 4. Due to the design of the
conductive contacts semiconductor device 4 of this invention, the production yield can be substantially higher as compared to the conventional semiconductor device that uses solder balls. - While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
Claims (11)
1. A semiconductor device comprising:
a semiconductor chip having a pad mounting surface with a plurality of bonding pads provided thereon;
a dielectric tape layer having opposite first and second adhesive surfaces, said first adhesive surface being adhered onto said pad mounting surface of said semiconductor chip, said dielectric tape layer being formed with a plurality of holes at positions registered with said bonding pads to expose said bonding pads, each of said holes being confined by a wall that cooperates with a registered one of said bonding pads to form a contact receiving space;
a plurality of conductive contacts placed in said contact receiving spaces, respectively; and
a printed circuit board having a circuit layout surface adhered onto said second adhesive surface of said dielectric tape layer, said circuit layout surface being formed with circuit traces that are bonded to said conductive contacts to establish electrical connection with said bonding pads.
2. The semiconductor device as claimed in , wherein said second adhesive surface is provided with a heat-curable adhesive having a curing point that is lower than melting point of said conductive contacts.
claim 1
3. The semiconductor device as claimed in , wherein each of said conductive contacts is a tin ball.
claim 1
4. The semiconductor device as claimed in , wherein each of said conductive contacts is formed from conductive paste.
claim 1
5. The semiconductor device as claimed in , wherein each of said conductive contacts is formed from a conductive material that undergoes chemical electroplating prior to bonding with said circuit traces.
claim 1
6. A method for manufacturing a semiconductor device, comprising:
adhering a first adhesive surface of a dielectric tape layer onto a pad mounting surface of a semiconductor chip, the dielectric tape layer being formed with a plurality of holes at positions registered with bonding pads provided on the pad mounting surface to expose the bonding pads, each of the holes being confined by a wall that cooperates with a registered one of the bonding pads to form a contact receiving space;
placing a plurality of conductive contacts in the contact receiving spaces, respectively; and
adhering a circuit layout surface of a printed circuit board onto a second adhesive surface of the dielectric tape layer opposite to the first adhesive surface, and bonding circuit traces formed on the circuit layout surface to the conductive contacts to establish electrical connection with the bonding pads.
7. The method as claimed in , wherein the second adhesive surface is provided with a heat-curable adhesive having a curing point that is lower than melting point of the conductive contacts, and adhering of the printed circuit board onto the dielectric tape layer and bonding of the circuit traces to the conductive contacts are performed simultaneously through a heat curing operation such that the circuit layout surface is already adhered onto the second adhesive surface prior to melting of the conductive contacts.
claim 6
8. The method as claimed in , wherein adhering of the dielectric tape layer onto the semiconductor chip is accomplished by heat curing of a heat-curable adhesive provided on the first adhesive surface.
claim 6
9. The method as claimed in , wherein each of the conductive contacts is a tin ball.
claim 6
10. The method as claimed in , wherein each of the conductive contacts is formed from conductive paste.
claim 6
11. The method as claimed in , wherein each of the conductive contacts is formed from a conductive material that undergoes chemical electroplating prior to bonding with the circuit traces.
claim 6
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/811,795 US6420210B2 (en) | 1999-04-16 | 2001-03-19 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW88106140 | 1999-04-16 | ||
TW088106140A TW432650B (en) | 1999-04-16 | 1999-04-16 | Semiconductor chip device and the manufacturing method thereof |
US09/329,599 US6278183B1 (en) | 1999-04-16 | 1999-06-10 | Semiconductor device and method for manufacturing the same |
US09/811,795 US6420210B2 (en) | 1999-04-16 | 2001-03-19 | Semiconductor device and method for manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/329,599 Division US6278183B1 (en) | 1999-04-16 | 1999-06-10 | Semiconductor device and method for manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010010406A1 true US20010010406A1 (en) | 2001-08-02 |
US6420210B2 US6420210B2 (en) | 2002-07-16 |
Family
ID=21640335
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/329,599 Expired - Fee Related US6278183B1 (en) | 1999-04-16 | 1999-06-10 | Semiconductor device and method for manufacturing the same |
US09/811,795 Expired - Fee Related US6420210B2 (en) | 1999-04-16 | 2001-03-19 | Semiconductor device and method for manufacturing the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/329,599 Expired - Fee Related US6278183B1 (en) | 1999-04-16 | 1999-06-10 | Semiconductor device and method for manufacturing the same |
Country Status (3)
Country | Link |
---|---|
US (2) | US6278183B1 (en) |
JP (1) | JP3084023B1 (en) |
TW (1) | TW432650B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW415050B (en) * | 1999-04-16 | 2000-12-11 | Shen Ming Dung | Semiconductor chipset module and the manufacturing method of the same |
US7575999B2 (en) * | 2004-09-01 | 2009-08-18 | Micron Technology, Inc. | Method for creating conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5835935A (en) | 1981-08-28 | 1983-03-02 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JP2706077B2 (en) | 1988-02-12 | 1998-01-28 | 株式会社日立製作所 | Resin-sealed semiconductor device and method of manufacturing the same |
JP2512999B2 (en) | 1988-08-24 | 1996-07-03 | 横河電機株式会社 | DRAM controller |
US5468681A (en) * | 1989-08-28 | 1995-11-21 | Lsi Logic Corporation | Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias |
US5148265A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
JPH04199723A (en) | 1990-11-29 | 1992-07-20 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
JP3492711B2 (en) | 1992-06-15 | 2004-02-03 | 富士通株式会社 | Bare chip mounting board |
JP3105089B2 (en) | 1992-09-11 | 2000-10-30 | 株式会社東芝 | Semiconductor device |
JPH07240434A (en) | 1994-03-02 | 1995-09-12 | Oki Electric Ind Co Ltd | Bump electrode and its manufacture |
JP2655496B2 (en) | 1994-11-21 | 1997-09-17 | 日本電気株式会社 | Integrated circuit device for face-down connection |
EP0740340B1 (en) | 1995-04-07 | 2002-06-26 | Shinko Electric Industries Co. Ltd. | Structure and process for mounting semiconductor chip |
US5776799A (en) * | 1996-11-08 | 1998-07-07 | Samsung Electronics Co., Ltd. | Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and method for manufacturing same |
JPH113909A (en) | 1997-06-11 | 1999-01-06 | Nitto Denko Corp | Flip chip member, sheet-like sealing material, and semiconductor device and its manufacture |
-
1999
- 1999-04-16 TW TW088106140A patent/TW432650B/en not_active IP Right Cessation
- 1999-06-10 US US09/329,599 patent/US6278183B1/en not_active Expired - Fee Related
- 1999-07-30 JP JP11216869A patent/JP3084023B1/en not_active Expired - Fee Related
-
2001
- 2001-03-19 US US09/811,795 patent/US6420210B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP3084023B1 (en) | 2000-09-04 |
JP2000306956A (en) | 2000-11-02 |
US6420210B2 (en) | 2002-07-16 |
US6278183B1 (en) | 2001-08-21 |
TW432650B (en) | 2001-05-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6362532B1 (en) | Semiconductor device having ball-bonded pads | |
US5854507A (en) | Multiple chip assembly | |
US5519936A (en) | Method of making an electronic package with a thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
US5773884A (en) | Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
USRE39603E1 (en) | Process for manufacturing semiconductor device and semiconductor wafer | |
KR100445072B1 (en) | Bumped chip carrier package using lead frame and method for manufacturing the same | |
KR100224133B1 (en) | Semiconductor chip mounting method bonded to circuit board through bumps | |
US5633533A (en) | Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
US5118370A (en) | LSI chip and method of producing same | |
US5530282A (en) | Semiconductor device having a multilayer interconnection structure | |
US5960262A (en) | Stitch bond enhancement for hard-to-bond materials | |
JP2001015679A (en) | Semiconductor device and manufacture thereof | |
US6242283B1 (en) | Wafer level packaging process of semiconductor | |
JPH1050886A (en) | Conductive polymer ball bonding to grid array semiconductor package | |
JPH05152375A (en) | Film carrier semiconductor device and manufacture thereof | |
US6271057B1 (en) | Method of making semiconductor chip package | |
US5559305A (en) | Semiconductor package having adjacently arranged semiconductor chips | |
US6420210B2 (en) | Semiconductor device and method for manufacturing the same | |
KR100769204B1 (en) | Semiconductor Package and Manufacture Method The Same | |
EP1061574A1 (en) | Semiconductor device and method for manufacturing the same | |
US6624008B2 (en) | Semiconductor chip installing tape, semiconductor device and a method for fabricating thereof | |
US6734041B2 (en) | Semiconductor chip module and method for manufacturing the same | |
KR100301096B1 (en) | Semiconductor device and method for manufacturing the same | |
KR20080051658A (en) | Printed circuit board, method of manufacturing the printed circuit board, semiconductor package having the printed circuit board and method of manufacturing the semiconductor package | |
US6307270B1 (en) | Electro-optic device and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: COMPUTECH INTERNATIONAL VENTURES LIMITED, HONG KON Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHEN, MING-TUNG;REEL/FRAME:012962/0131 Effective date: 20020426 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20060716 |