US20010010953A1 - Thin film transistor and method of fabricating the same - Google Patents
Thin film transistor and method of fabricating the same Download PDFInfo
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- US20010010953A1 US20010010953A1 US09/810,232 US81023201A US2001010953A1 US 20010010953 A1 US20010010953 A1 US 20010010953A1 US 81023201 A US81023201 A US 81023201A US 2001010953 A1 US2001010953 A1 US 2001010953A1
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- 239000010409 thin film Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 79
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 26
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 41
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 30
- 239000011651 chromium Substances 0.000 claims description 29
- 229910052750 molybdenum Inorganic materials 0.000 claims description 27
- 239000011733 molybdenum Substances 0.000 claims description 27
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 24
- 229910052804 chromium Inorganic materials 0.000 claims description 20
- 238000001020 plasma etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000002161 passivation Methods 0.000 claims description 5
- 239000010408 film Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 239000011521 glass Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
Definitions
- the present invention relates to a semiconductor device, and in particular, to a thin film transistor and a method of fabricating the thin film transistor.
- Thin film transistors serve as switching devices switching image data signals in each pixel region.
- Thin film transistors can be used instead of CMOS load transistors or load resistors of a static random access memory (SRAM) of more than 1M bit.
- a liquid crystal display (LCD) includes an upper glass, a lower glass, and a liquid crystal interposed between the upper and lower glasses.
- the upper glass has a black matrix layer, a common electrode, and R, G and B color filter layers.
- the lower glass has data lines and gate lines crossing each other and pixel regions arranged in matrix.
- a pixel electrode is formed in each pixel region, and an amorphous thin film transistor acting like an analog switch is formed to control charge stored in its capacitor.
- FIG. 1 is a lay-out of a related art liquid crystal display.
- the lower glass includes a plurality of scanning lines 11 formed extending in one direction, a gate electrode 11 a extending from each scanning line 11 and data lines 12 crossing the scanning lines 11 .
- a thin film transistor includes a source electrode 12 a and a drain electrode 12 b extending from the data lines 12 .
- Black matrix layers are arranged on the upper glass like a gauze to shut out the light in a region except the pixel electrodes (not shown) formed on the lower glass.
- R, G and B color filter layers are formed between the black matrix layers.
- a common electrode is formed over the color filter layers and black matrix layers.
- a related art thin film transistor includes a gate electrode 11 a formed on an insulating substrate 21 , a gate insulating layer 22 disposed on gate electrode 11 a and an amorphous silicon layer 23 disposed on gate insulating layer 22 to enclose the gate electrode 11 a .
- An n+ silicon layer is formed as an ohmic layer 24 to expose a part of the amorphous silicon layer 23 on the gate electrode 11 a , and the source electrode 12 a and the drain electrode 12 b are formed on the ohmic layer 24 .
- the material of each of the source and drain electrodes 12 a and 12 b is molybdenum.
- the gate electrode 11 a is formed on a predetermined area of the insulating substrate 21 .
- An insulating layer such as siliconitride SiN is formed on the substrate 21 including the gate electrode 11 a to form the gate insulating layer 22 .
- the insulating material used as the gate insulating layer 22 serves as a capacitor dielectric in a storage capacitor area.
- an amorphous silicon layer 32 and an n+ silicon layer 33 are formed on the gate insulating layer 22 .
- the n+ silicon layer 33 and the amorphous silicon layer 32 are selectively removed to enclose the gate electrode 11 a .
- Molybdenum (Mo) is applied all over substrate 21 including the n+ silicon layer 33 as source and drain electrodes.
- the molybdenum material forming the source and drain electrodes and the n+ silicon layer 33 are serially etched to expose the amorphous silicon layer 32 corresponding to a channel region and form the source and drain electrodes 12 a and 12 b .
- Molybdenum (not shown), the material forming the source and drain electrodes, is patterned on the gate insulating 11 layer 22 in the storage capacitor area of the pixel region to contact a pixel electrode in the post manufacturing process.
- a passivation layer 34 is formed all over the substrate 21 including the source and drain electrodes 12 a and 12 b .
- the manufacture of the thin film transistor is complete.
- FIGS. 4A to 4 J depict the steps in the manufacture of the second related art thin film transistor.
- a gate material 44 formed of chromium 42 and molybdenum 43 is formed on a predetermined area of substrate 41 .
- the gate material 44 can be constituted by either two layers (e.g., chromium 42 and molybdenum 43 ) or one layer.
- the gate material 44 is patterned to form a gate electrode 44 a by a general patterning process. Sides of the gate electrode 44 a have a slant when formed by a reactive ion etching (RIE) when patterning the two-layered gate electrode 44 a formed by molybdenum 43 and chromium 42 .
- RIE reactive ion etching
- a gate insulating layer 45 is deposited all over the gate electrode 44 a and the substrate 41 .
- the gate electrode 44 a is inclined at its edge to improve the coverage in the corresponding area.
- a gate electrode having a slant at its edge and a technique of improving the coverage are disclosed in U.S. Pat. No. 5,132,745.
- an amorphous silicon layer 46 is serially deposited on the gate insulating layer 45 in a vacuum chamber.
- An n+ amorphous silicon layer 47 is serially deposited on the amorphous silicon layer 46 .
- the n+ amorphous silicon layer 47 and the amorphous silicon layer 46 are selectively removed except in an area where a thin film transistor is formed on the substrate 41 .
- a first conductive layer 48 is deposited to a thickness of 0.01 to 0.1 ⁇ m on the gate insulating layer 45 including the patterned n+ amorphous silicon layer 47 and the amorphous silicon layer 46 .
- the first conductive layer 48 is made of chromium (Cr) in ohmic contact with the n+ amorphous silicon layer 47 .
- the first conductive layer 48 can be made of a material such as nichromium (nickel and chromium) and tantalum.
- a second conductive layer 49 is deposited to a thickness of 0.1 to 1 ⁇ m on the first conductive layer 48 .
- the second conductive layer 49 is made of molybdenum, and may be made of aluminum or tungsten.
- the use of molybdenum as second conductive layer 49 assures better conductivity than that of source and drain electrodes made of chromium (Cr), which constitutes the first conductive layer 48 .
- Molybdenum assures a good ohmic contact for source and drain electrodes and the n+ amorphous silicon layer 47 .
- a photoresist 50 is applied on the second conductive material 49 .
- the photoresist 50 corresponding to the channel region of the thin film transistor is removed, and the photoresist 50 is patterned to have edges slanted by 45°.
- the second conductive material 49 is etched using the photoresist 50 as a mask with a requirement that the first conductive layer 48 is not effected. Based on the requirement of the etching process, SF 6 gas of 37.5 sccm, Cl 2 gas of 6.5 sccm, and O 2 gas of 16 sccm are used and a pressure of 6.5 mTorr is maintained. The etching process is carried out under Rf plasma. Since the photoresist 50 is patterned with inclined edges, the second conductive material 49 also becomes patterned with inclined edges.
- the exposed first conductive layer 48 , Cr is selectively etched by changing the requirements for etching the second conductive layer 49 .
- the first conductive layer 48 is etched in a different process than the second conductive layer 49 .
- Etching the first conductive layer 48 forms a source electrode 51 and a drain electrode 51 a , which are respectively made of the first conductive layer 48 and second conductive layer 49 .
- the first conductive layer 48 is etched away by the use of chroline gas, Cl 2 gas of 70 sccm and O 2 gas of 30 sccm as a source gas under the pressure of 100 mTorr.
- the first conductive material 48 and the photoresist are in the etching ratio of 1 to 1.
- the first conductive layer 48 , Cr is used as an etch stopper of the second conductive layer 49 , and the etching speed of molybdenum, the second conductive layer 49 is higher than that of first conductive layer 48 , Cr.
- the exposed n+ amorphous silicon layer 47 is etched to expose a part of the amorphous silicon layer 46 . Further, after removing the photoresist, a the passivation layer 60 is formed all over the substrate 41 including the source electrode 51 and the drain electrode 51 a , to complete the manufacture of the second related art thin film transistor.
- the related art method of manufacturing the thin film transistor has various problems.
- a two-step etching process is needed that increases the time to perform the etching process.
- the etching gas for etching the molybdenum etches the n+ amorphous silicon through the holes.
- An object of the present invention is to provide a thin film transistor and method of fabricating a thin film transistor that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
- Another object of the present invention is to provide a thin film transistor and method of manufacturing the same that has source and drain electrodes formed by a single etching process.
- Another object of the present invention is to provide a thin film transistor and method of manufacturing the same that has a less complex manufacturing process.
- the present invention includes a thin film transistor that includes a thin film transistor including a substrate; a gate on the substrate; a gate insulating layer on the substrate and the gate electrode; a first semiconductor layer on the gate insulating layer; a second semiconductor layer on the first semiconductor layer; and first and second electrodes on the second semiconductor layer to expose the second semiconductor layer over the gate, wherein edges of the first and second electrodes adjacent to the exposed surface or the second semiconductor layer are non-linearly inclined.
- a thin film transistor includes a thin film transistor including a substrate; a gate electrode on the substrate; a gate insulating layer on the substrate and the gate electrode; a first semiconductor layer on the gate insulating layer; a second semiconductor layer on the first semiconductor layer on the gate electrode; a first conductive material on the second semiconductor layer; and a second conductive material on the first conductive material, to expose edges of the first conductive material.
- a method of fabricating a thin film transistor includes forming a trapezoidal shaped gate electrode on a substrate; forming a gate insulating layer on the substrate and the gate electrode; forming a first semiconductor layer on the gate insulating layer; forming a second semiconductor layer on the first semiconductor layer; depositing a first conductive material and a second conductive material on the second semiconductor layer; and selectively removing the first conductive material and the second conductive material using a single etching gas to expose a prescribed part of the second semiconductor layer over the gate electrode, wherein respective edges of the etched first and second conductive materials are non-linearly inclined.
- FIG. 1 is a diagram showing a related art liquid crystal display
- FIG. 2 is a diagram showing a sectional view along line of I-I′ of FIG. 1;
- FIGS. 3A to 3 D are diagrams showing sectional views of a related art thin film transistor
- FIGS. 4A to 4 J are diagrams showing sectional views of steps in the manufacture of a related art thin film transistor
- FIG. 5 is a diagram showing a sectional view of a preferred embodiment of a thin film transistor in accordance with the present invention.
- FIGS. 6A to 6 H are diagrams showing cross-sectional views of a preferred embodiment of a method to manufacture a thin film transistor in accordance with the present invention.
- FIG. 5 is a diagram showing a cross-section of a preferred embodiment of a thin film transistor in accordance with the present invention.
- the preferred embodiment of the thin film transistor includes a substrate 61 , a gate electrode 64 formed on the substrate 61 , a gate insulating layer 65 formed all over substrate 61 including the gate electrode 64 and an amorphous silicon layer 66 formed on the gate insulating layer 65 .
- the gate electrode 64 preferably has a trapezoidal cross-section.
- An n+ amorphous silicon layer 67 is separately formed on the amorphous silicon layer 66 to expose the amorphous silicon layer 66 , which is used as a channel region.
- Source and drain electrodes 71 and 71 b are formed on the n+ amorphous silicon layer 67 and preferably have a non-linear slant or step at their edges.
- a passivation layer 72 is formed on the substrate 61 including the source and drain electrodes 71 a and 71 b .
- the source and drain electrodes 71 a and 71 b are preferably made of two-layered conductive material.
- a first conductive material is preferably chromium (Cr) and a second conductive material is preferably molybdenum. As shown in FIG. 5, an edge of the first conductive material (Cr) adjacent to the channel region does not correspond to an edge of the second conductive material (Mo).
- TFT thin film transistor
- a chromium (Cr) layer 62 is formed on an insulating substrate 61 as a gate electrode material, and a molybdenum layer 63 is formed on the chromium layer 62 .
- the gate electrode material is selectively removed by an etching technique to form the gate electrode 64 .
- the gate electrode 64 is preferably made of chromium and molybdenum.
- the gate electrode 64 can be made, for example, of molybdenum only.
- the gate electrode preferably has a trapezoidal cross-section.
- a gate insulating layer 65 is formed all over the substrate 61 including the gate electrode 64 .
- An amorphous silicon layer 66 is deposited on the gate insulating layer 65 in a vacuum chamber used for the deposition of gate insulating layer 65 .
- An n+ amorphous silicon layer 67 is serially deposited on the amorphous silicon layer 66 .
- the n+ amorphous silicon layer 67 and the amorphous silicon layer 66 on the substrate 61 are selectively removed except for a thin film transistor area.
- a first conductive material 68 is deposited on the gate insulating layer 65 including the patterned n+ amorphous silicon layer 67 , and the amorphous silicon layer 66 to be used as a source and a drain electrode material.
- Chromium is preferably used for the first conductive material 68 .
- the first conductive material 68 may be nichromium (alloy of nickel and chromium) or tantalum having a good ohmic contact with the n+ amorphous silicon layer 67 .
- a second conductive material 69 is deposited on the first conductive material 68 to be relatively thicker than the first conductive material 68 .
- the second conductive material 69 is preferably molybdenum, but can be aluminum or tungsten.
- photoresist 70 is applied to the second conductive material 69 .
- the photoresist 70 is removed on the channel region of the thin film transistor by photolithography.
- the second conductive material 69 and the first conductive material 68 are serially etched by the same etching gas in a single process using the patterned photoresist 70 as a mask.
- Cl 2 gas+O 2 gas are preferably used as the etching gas, and the amount of Cl 2 gas is approximately in the range of 400 to 600 sccm and more preferably, 500 sccm.
- the amount of O 2 gas is approximately in the range of 300 to 500 sccm, and more preferably, 400 sccm.
- the pressure during etching is approximately in the range of 100 to 200 mTorr, and RF power is approximately 0.5 to 0.8 watts/cm 2 , and more preferably, 0.66 watts/cm 2 .
- Reactive ion etching or plasma etching can be used.
- the first conductive material 68 and the second conductive material 69 are serially etched in the same chamber without changing the etching condition to pattern the source and drain electrodes 71 a and 71 b.
- chromium, the first conductive material 68 and molybdenum, the second conductive material 69 have different etching ratios. Accordingly, edges of the source and drain electrodes are in steps or tiers. Chromium and molybdenum reacting to the Cl 2 +O 2 etching gas, have an etching ratio of 10 to 1. Further, chromium, the first conductive material 68 , and the n+ amorphous silicon layer 67 have an etching ratio of 4 to 1.
- the n+ amorphous silicon layer 67 is not over-etched even if holes area formed by particles when depositing the first conductive material 68 .
- the etching selection ratio of the gate insulating layer 65 in the pixel area adjacent to the edge of drain electrode 71 b can be secured to prevent the gate insulating layer 65 from being over-etched.
- the exposed n+ amorphous silicon layer 67 is etched to expose the amorphous silicon layer 66 .
- the photoresist 70 is removed.
- passivation layer 72 is formed all over substrate 61 including the source and drain electrodes 71 a and 71 b to complete the preferred embodiment of a method for manufacturing a thin film transistor according to the present invention.
- the preferred embodiments of a thin film transistor and a manufacturing method for the same have various advantages.
- the preferred embodiments employ a single etching process in patterning the two-layered source and drain electrodes to simplify the production process, reduce the process steps (e.g., separate etching steps) and reduce manufacturing costs. Further, the preferred embodiments improve step coverage at the edge of the drain electrode toward the storage capacitor to increase the reliability of semiconductor devices.
- a nail and a screw may not be structural equivalents in that a nail employs a cylindrical surface to secure wooden parts together, whereas a screw employs a helical surface, in the environment of fastening wooden parts, a nail and a screw may be equivalent structures.
Abstract
A thin film transistor is provided that includes a substrate, a gate electrode formed on the substrate, and a gate insulating layer formed all over the substrate including the gate electrode. A first semiconductor layer is formed on the gate insulating layer, and a second semiconductor layer is formed on the first semiconductor layer. Source and drain electrodes are separately etched together to expose a prescribed portion surface of the second semiconductor layer over the gate electrode. The source and drain electrodes adjacent to the prescribed portion of the second semiconductor layer are non-linearly inclined at their edges. A method of fabricating a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode and the substrate, forming a first semiconductor layer on the gate insulating layer and forming a second semiconductor layer on the first semiconductor layer. First and second conductive materials are deposited on the second semiconductor layer. A single etching process is performed on the first and second conductive materials using the same etching gas to expose a prescribed part of the second semiconductor layer over the gate electrode to make the etched first and second conductive materials have a tier structure at edges of the prescribed part.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device, and in particular, to a thin film transistor and a method of fabricating the thin film transistor.
- 2. Background of the Related Art
- Thin film transistors serve as switching devices switching image data signals in each pixel region. Thin film transistors can be used instead of CMOS load transistors or load resistors of a static random access memory (SRAM) of more than 1M bit. A liquid crystal display (LCD) includes an upper glass, a lower glass, and a liquid crystal interposed between the upper and lower glasses. The upper glass has a black matrix layer, a common electrode, and R, G and B color filter layers. The lower glass has data lines and gate lines crossing each other and pixel regions arranged in matrix. A pixel electrode is formed in each pixel region, and an amorphous thin film transistor acting like an analog switch is formed to control charge stored in its capacitor.
- FIG. 1 is a lay-out of a related art liquid crystal display. As shown in FIG. 1, the lower glass includes a plurality of
scanning lines 11 formed extending in one direction, agate electrode 11 a extending from eachscanning line 11 anddata lines 12 crossing thescanning lines 11. A thin film transistor includes asource electrode 12 a and adrain electrode 12 b extending from thedata lines 12. - Black matrix layers (not shown) are arranged on the upper glass like a gauze to shut out the light in a region except the pixel electrodes (not shown) formed on the lower glass. R, G and B color filter layers (not shown) are formed between the black matrix layers. Further, a common electrode (not shown) is formed over the color filter layers and black matrix layers.
- As shown in FIG. 2, a related art thin film transistor includes a
gate electrode 11 a formed on aninsulating substrate 21, agate insulating layer 22 disposed ongate electrode 11 a and anamorphous silicon layer 23 disposed ongate insulating layer 22 to enclose thegate electrode 11 a. An n+ silicon layer is formed as anohmic layer 24 to expose a part of theamorphous silicon layer 23 on thegate electrode 11 a, and thesource electrode 12 a and thedrain electrode 12 b are formed on theohmic layer 24. The material of each of the source anddrain electrodes - The process of manufacturing a related art thin film transistor will now be described. As shown in FIG. 3A, the
gate electrode 11 a is formed on a predetermined area of theinsulating substrate 21. An insulating layer such as siliconitride SiN is formed on thesubstrate 21 including thegate electrode 11 a to form thegate insulating layer 22. The insulating material used as thegate insulating layer 22 serves as a capacitor dielectric in a storage capacitor area. As shown in FIG. 3B, anamorphous silicon layer 32 and ann+ silicon layer 33 are formed on thegate insulating layer 22. - As shown in FIG. 3C, the
n+ silicon layer 33 and theamorphous silicon layer 32 are selectively removed to enclose thegate electrode 11 a. Molybdenum (Mo) is applied all oversubstrate 21 including then+ silicon layer 33 as source and drain electrodes. The molybdenum material forming the source and drain electrodes and then+ silicon layer 33 are serially etched to expose theamorphous silicon layer 32 corresponding to a channel region and form the source anddrain electrodes layer 22 in the storage capacitor area of the pixel region to contact a pixel electrode in the post manufacturing process. - As shown in FIG. 3D, a
passivation layer 34 is formed all over thesubstrate 21 including the source anddrain electrodes - In the manufacture of the thin film transistor, when fluorine (F) gas is used as an etching gas in an etching process to form source and drain electrodes, an etching selection ratio of
n+ silicon layer 33 andamorphous silicon layer 32 cannot be secured. Thus, Chlorine (Cl) gas is used instead of the fluorine gas to solve the above problem. When using Cl gas, there is no etching selection ratio withgate insulating layer 22 of the storage capacitor area, which causes excessive etching ofgate insulating layer 22, and, what is worse,gate insulating layer 22 may be opened. - A second related art thin film transistor was proposed to solve the above problem, and a method of fabricating the second related art thin film transistor will now be described. FIGS. 4A to4J depict the steps in the manufacture of the second related art thin film transistor.
- As shown in FIG. 4A, a
gate material 44 formed ofchromium 42 andmolybdenum 43 is formed on a predetermined area ofsubstrate 41. Thegate material 44 can be constituted by either two layers (e.g.,chromium 42 and molybdenum 43) or one layer. - Referring to FIG. 4B, the
gate material 44 is patterned to form a gate electrode 44 a by a general patterning process. Sides of the gate electrode 44 a have a slant when formed by a reactive ion etching (RIE) when patterning the two-layered gate electrode 44 a formed bymolybdenum 43 andchromium 42. - As shown in FIG. 4C, after patterning the gate electrode44 a, a
gate insulating layer 45 is deposited all over the gate electrode 44 a and thesubstrate 41. The gate electrode 44 a is inclined at its edge to improve the coverage in the corresponding area. A gate electrode having a slant at its edge and a technique of improving the coverage are disclosed in U.S. Pat. No. 5,132,745. - As shown in FIG. 4D, an
amorphous silicon layer 46 is serially deposited on thegate insulating layer 45 in a vacuum chamber. An n+amorphous silicon layer 47 is serially deposited on theamorphous silicon layer 46. Subsequently, as shown in FIG. 4E, the n+amorphous silicon layer 47 and theamorphous silicon layer 46 are selectively removed except in an area where a thin film transistor is formed on thesubstrate 41. - As shown in FIG. 4F, a first
conductive layer 48 is deposited to a thickness of 0.01 to 0.1 μm on thegate insulating layer 45 including the patterned n+amorphous silicon layer 47 and theamorphous silicon layer 46. The firstconductive layer 48 is made of chromium (Cr) in ohmic contact with the n+amorphous silicon layer 47. The firstconductive layer 48 can be made of a material such as nichromium (nickel and chromium) and tantalum. - A second
conductive layer 49 is deposited to a thickness of 0.1 to 1 μm on the firstconductive layer 48. Thus, the secondconductive layer 49 is relatively larger than the firstconductive layer 48. The secondconductive layer 49 is made of molybdenum, and may be made of aluminum or tungsten. The use of molybdenum as secondconductive layer 49 assures better conductivity than that of source and drain electrodes made of chromium (Cr), which constitutes the firstconductive layer 48. Molybdenum assures a good ohmic contact for source and drain electrodes and the n+amorphous silicon layer 47. - As shown in FIG. 4G, a
photoresist 50 is applied on the secondconductive material 49. Thephotoresist 50 corresponding to the channel region of the thin film transistor is removed, and thephotoresist 50 is patterned to have edges slanted by 45°. - As shown in FIG. 4H, the second
conductive material 49 is etched using thephotoresist 50 as a mask with a requirement that the firstconductive layer 48 is not effected. Based on the requirement of the etching process, SF6 gas of 37.5 sccm, Cl2 gas of 6.5 sccm, and O2 gas of 16 sccm are used and a pressure of 6.5 mTorr is maintained. The etching process is carried out under Rf plasma. Since thephotoresist 50 is patterned with inclined edges, the secondconductive material 49 also becomes patterned with inclined edges. - As shown in FIG. 4I, the exposed first
conductive layer 48, Cr, is selectively etched by changing the requirements for etching the secondconductive layer 49. In other words, the firstconductive layer 48 is etched in a different process than the secondconductive layer 49. Etching the firstconductive layer 48 forms asource electrode 51 and adrain electrode 51 a, which are respectively made of the firstconductive layer 48 and secondconductive layer 49. - The first
conductive layer 48 is etched away by the use of chroline gas, Cl2 gas of 70 sccm and O2 gas of 30 sccm as a source gas under the pressure of 100 mTorr. The firstconductive material 48 and the photoresist are in the etching ratio of 1 to 1. Thus, the firstconductive layer 48, Cr, is used as an etch stopper of the secondconductive layer 49, and the etching speed of molybdenum, the secondconductive layer 49 is higher than that of firstconductive layer 48, Cr. When etching molybdenum and chromium as the source and drainelectrodes amorphous silicon layer 47 is etched to expose a part of theamorphous silicon layer 46. Further, after removing the photoresist, a thepassivation layer 60 is formed all over thesubstrate 41 including thesource electrode 51 and thedrain electrode 51 a, to complete the manufacture of the second related art thin film transistor. - The related art method of manufacturing the thin film transistor has various problems. When etching the source and drain electrodes made of molybdenum, the first conductive material, and chromium, the second conductive material, a two-step etching process is needed that increases the time to perform the etching process. Further, when etching molybdenum, the first conductive material, if the chromium, which is used as an etch stopper, is not uniformly deposited and has holes, the etching gas for etching the molybdenum etches the n+ amorphous silicon through the holes. Thus, an open in a signal line or driving degradation of thin film transistors can occur.
- The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
- An object of the present invention is to provide a thin film transistor and method of fabricating a thin film transistor that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
- Another object of the present invention is to provide a thin film transistor and method of manufacturing the same that has source and drain electrodes formed by a single etching process.
- Another object of the present invention is to provide a thin film transistor and method of manufacturing the same that has a less complex manufacturing process.
- To achieve at least these objects and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes a thin film transistor that includes a thin film transistor including a substrate; a gate on the substrate; a gate insulating layer on the substrate and the gate electrode; a first semiconductor layer on the gate insulating layer; a second semiconductor layer on the first semiconductor layer; and first and second electrodes on the second semiconductor layer to expose the second semiconductor layer over the gate, wherein edges of the first and second electrodes adjacent to the exposed surface or the second semiconductor layer are non-linearly inclined.
- To further achieve the above objects in a whole or in parts, a thin film transistor according to the present invention includes a thin film transistor including a substrate; a gate electrode on the substrate; a gate insulating layer on the substrate and the gate electrode; a first semiconductor layer on the gate insulating layer; a second semiconductor layer on the first semiconductor layer on the gate electrode; a first conductive material on the second semiconductor layer; and a second conductive material on the first conductive material, to expose edges of the first conductive material.
- To further achieve the above objects in a whole or in parts, a method of fabricating a thin film transistor according to the present invention includes forming a trapezoidal shaped gate electrode on a substrate; forming a gate insulating layer on the substrate and the gate electrode; forming a first semiconductor layer on the gate insulating layer; forming a second semiconductor layer on the first semiconductor layer; depositing a first conductive material and a second conductive material on the second semiconductor layer; and selectively removing the first conductive material and the second conductive material using a single etching gas to expose a prescribed part of the second semiconductor layer over the gate electrode, wherein respective edges of the etched first and second conductive materials are non-linearly inclined.
- Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those have ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
- The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:
- FIG. 1 is a diagram showing a related art liquid crystal display;
- FIG. 2 is a diagram showing a sectional view along line of I-I′ of FIG. 1;
- FIGS. 3A to3D are diagrams showing sectional views of a related art thin film transistor;
- FIGS. 4A to4J are diagrams showing sectional views of steps in the manufacture of a related art thin film transistor;
- FIG. 5 is a diagram showing a sectional view of a preferred embodiment of a thin film transistor in accordance with the present invention; and
- FIGS. 6A to6H are diagrams showing cross-sectional views of a preferred embodiment of a method to manufacture a thin film transistor in accordance with the present invention.
- FIG. 5 is a diagram showing a cross-section of a preferred embodiment of a thin film transistor in accordance with the present invention. As shown in FIG. 5, the preferred embodiment of the thin film transistor includes a
substrate 61, agate electrode 64 formed on thesubstrate 61, agate insulating layer 65 formed all oversubstrate 61 including thegate electrode 64 and anamorphous silicon layer 66 formed on thegate insulating layer 65. Thegate electrode 64 preferably has a trapezoidal cross-section. An n+amorphous silicon layer 67 is separately formed on theamorphous silicon layer 66 to expose theamorphous silicon layer 66, which is used as a channel region. Source anddrain electrodes 71 and 71 b are formed on the n+amorphous silicon layer 67 and preferably have a non-linear slant or step at their edges. Apassivation layer 72 is formed on thesubstrate 61 including the source and drainelectrodes electrodes - A first conductive material is preferably chromium (Cr) and a second conductive material is preferably molybdenum. As shown in FIG. 5, an edge of the first conductive material (Cr) adjacent to the channel region does not correspond to an edge of the second conductive material (Mo).
- A preferred embodiment of a method for manufacturing a thin film transistor (TFT) in accordance with the present invention will now be described. The preferred embodiment of the method for manufacturing the TFT can be used, for example, to produce the preferred embodiment of a TFT shown in FIG. 5.
- As shown in FIG. 6A, a chromium (Cr)
layer 62 is formed on an insulatingsubstrate 61 as a gate electrode material, and amolybdenum layer 63 is formed on thechromium layer 62. The gate electrode material is selectively removed by an etching technique to form thegate electrode 64. Thus, thegate electrode 64 is preferably made of chromium and molybdenum. However, thegate electrode 64 can be made, for example, of molybdenum only. Further, the gate electrode preferably has a trapezoidal cross-section. - As shown in FIG. 6B, a
gate insulating layer 65 is formed all over thesubstrate 61 including thegate electrode 64. Anamorphous silicon layer 66 is deposited on thegate insulating layer 65 in a vacuum chamber used for the deposition ofgate insulating layer 65. An n+amorphous silicon layer 67 is serially deposited on theamorphous silicon layer 66. - As shown in FIG. 6C, the n+
amorphous silicon layer 67 and theamorphous silicon layer 66 on thesubstrate 61 are selectively removed except for a thin film transistor area. - As shown in FIG. 6D, a first
conductive material 68 is deposited on thegate insulating layer 65 including the patterned n+amorphous silicon layer 67, and theamorphous silicon layer 66 to be used as a source and a drain electrode material. Chromium is preferably used for the firstconductive material 68. However, the firstconductive material 68 may be nichromium (alloy of nickel and chromium) or tantalum having a good ohmic contact with the n+amorphous silicon layer 67. - A second
conductive material 69 is deposited on the firstconductive material 68 to be relatively thicker than the firstconductive material 68. The secondconductive material 69 is preferably molybdenum, but can be aluminum or tungsten. As shown in FIG. 6E,photoresist 70 is applied to the secondconductive material 69. Thephotoresist 70 is removed on the channel region of the thin film transistor by photolithography. - As shown in FIG. 6F, the second
conductive material 69 and the firstconductive material 68 are serially etched by the same etching gas in a single process using the patternedphotoresist 70 as a mask. - Cl2 gas+O2 gas are preferably used as the etching gas, and the amount of Cl2 gas is approximately in the range of 400 to 600 sccm and more preferably, 500 sccm. The amount of O2 gas is approximately in the range of 300 to 500 sccm, and more preferably, 400 sccm. The pressure during etching is approximately in the range of 100 to 200 mTorr, and RF power is approximately 0.5 to 0.8 watts/cm2, and more preferably, 0.66 watts/cm2. Reactive ion etching or plasma etching can be used. The first
conductive material 68 and the secondconductive material 69 are serially etched in the same chamber without changing the etching condition to pattern the source and drainelectrodes - When using the Cl2 gas+O2 gas mixture according to the present invention for etching, chromium, the first
conductive material 68 and molybdenum, the secondconductive material 69, have different etching ratios. Accordingly, edges of the source and drain electrodes are in steps or tiers. Chromium and molybdenum reacting to the Cl2+O2 etching gas, have an etching ratio of 10 to 1. Further, chromium, the firstconductive material 68, and the n+amorphous silicon layer 67 have an etching ratio of 4 to 1. - Since molybdenum and the n+
amorphous silicon layer 67 are in the etching ratio of 40 to 1, the n+amorphous silicon layer 67 is not over-etched even if holes area formed by particles when depositing the firstconductive material 68. In addition, the etching selection ratio of thegate insulating layer 65 in the pixel area adjacent to the edge ofdrain electrode 71 b can be secured to prevent thegate insulating layer 65 from being over-etched. - As shown in FIG. 6G, the exposed n+
amorphous silicon layer 67 is etched to expose theamorphous silicon layer 66. Then, thephotoresist 70 is removed. Subsequently,passivation layer 72 is formed all oversubstrate 61 including the source and drainelectrodes - As described above, the preferred embodiments of a thin film transistor and a manufacturing method for the same have various advantages. The preferred embodiments employ a single etching process in patterning the two-layered source and drain electrodes to simplify the production process, reduce the process steps (e.g., separate etching steps) and reduce manufacturing costs. Further, the preferred embodiments improve step coverage at the edge of the drain electrode toward the storage capacitor to increase the reliability of semiconductor devices.
- The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. For example, although a nail and a screw may not be structural equivalents in that a nail employs a cylindrical surface to secure wooden parts together, whereas a screw employs a helical surface, in the environment of fastening wooden parts, a nail and a screw may be equivalent structures.
Claims (19)
1. A thin film transistor, comprising:
a substrate;
a gate on the substrate;
a gate insulating layer on the substrate and the gate electrode;
a first semiconductor layer on the gate insulating layer;
a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer exposes a prescribed portion of the first semiconductor layer; and
first and second electrodes on the second semiconductor layer to expose the first and second semiconductor layers over the gate, wherein edges of the first and second electrodes adjacent to the exposed surface of the second semiconductor layer are non-linearly inclined.
2. The thin film transistor according to , wherein the first and second electrodes include a first conductive material and a second conductive material stacked on the first conductive material.
claim 1
3. The thin film transistor according to , wherein the first and second conductive layers are etched concurrently in a single process using a single etchant to form source and drain electrodes.
claim 2
4. The thin film transistor according to , wherein the first conductive material does not correspond to the second conductive material at the edges of the first and second electrodes, and wherein the first conductive material is chromium and the second conductive material is molybdenum.
claim 2
5. The thin film transistor according to , wherein the second conductive material is thicker than the first conductive material, and wherein an etching ratio of the second conductive material to the first conductive material is approximately 10 to 1.
claim 2
6. The thin film transistor according to , wherein the first semiconductor layer is an amorphous silicon layer, the second semiconductor layer is an n+ amorphous silicon layer and wherein the gate comprises:
claim 1
a gate electrode patterned on the substrate; and
a gate insulating layer on the substrate and the gate electrode, wherein the gate electrode has a trapezoidal shape.
7. A thin film transistor, comprising:
a substrate;
a gate electrode on the substrate;
a gate insulating layer on the substrate and the gate electrode;
a first semiconductor layer on the gate insulating layer;
a second semiconductor layer on the first semiconductor layer on the gate electrode;
a first conductive material on the second semiconductor layer; and
a second conductive material on the first conductive material, wherein the first and second conductive materials expose the second semiconductor layer over the gate electrode, and wherein the first and second conductive materials have a tier structure to expose edges of the first conductive material.
8. The thin film transistor according to , wherein the first conductive material and the second conductive material are stacked to be source and drain electrodes.
claim 7
9. The thin film transistor according to , wherein the first conductive material and the second conductive material are selectively removed at the same time using a single etchant.
claim 7
10. The thin film transistor according to , wherein the edges of first conductive material do not correspond to the second conductive material.
claim 7
11. The film transistor according to , wherein etching the second conductive material is higher than etching the first conductive material in speed, and etching the first conductive material is higher than etching the second conductive material in speed.
claim 6
12. The thin film transistor according to , wherein the first semiconductor layer is an amorphous silicon layer, the second semiconductor layer is an n+ amorphous silicon layer, the first conductive layer is chromium, and the second conductive layer is molybdenum, and wherein an etching ratio of the n+ amorphous silicon layer to the molybdenum is approximately 40 to 1.
claim 6
13. A method of fabricating a thin film transistor comprising the steps of:
forming a trapezoidal shaped gate electrode on a substrate;
forming a gate insulating layer on the substrate and the gate electrode;
forming a first semiconductor layer on the gate insulating layer;
forming a second semiconductor layer on the first semiconductor layer;
depositing a first conductive material and a second conductive material on the second semiconductor layer; and
selectively etching the first conductive material and the second conductive material using a single etching gas to expose a prescribed part of the second semiconductor layer over the gate electrode, wherein respective edges of the etched first and second conductive materials are non-linearly inclined.
14. The method according to , wherein the selectively etching step is at least one of a reactive ion etching and a plasma etching, further comprising etching the second semiconductor layer over the gate electrode to expose the first semiconductor layer.
claim 13
15. The method according to , wherein the single etching gas is Cl2+O2 gas.
claim 13
16. The method according to , wherein the amount of the Cl2 gas is approximately in the range of 400 to 600 sccm and the amount of the O2 gas is approximately in the range of 300 to 500 sccm, and wherein the selectively removing step is performed under the pressure of 100 to 200 mTorr and RF power of 0.5 to 0.8 watts/cm2.
claim 15
17. The method according to , further comprising depositing a passivation layer wherein the respective edges of the etched first and second conductive materials are tiered to improve step coverage.
claim 13
18. The method according to , wherein an etching selection ratio of the first conductive material to the gate insulating layer is high.
claim 13
19. The method according to , wherein the second and first conductive materials are etched to form source and drain electrodes, and wherein an etching selection ratio of the second conductive material to the first conductive material and the first conductive material to the second semiconductor layer is high, and wherein the first and second conductive materials have a tiered structure at edges of the prescribed part of the second semiconductive layer.
claim 12
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KR1019980020848A KR100301803B1 (en) | 1998-06-05 | 1998-06-05 | Thin film transistor and its manufacturing method |
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KR98-20848 | 1998-06-05 | ||
US09/317,952 US6255668B1 (en) | 1998-06-05 | 1999-05-25 | Thin film transistor with inclined eletrode side surfaces |
US09/810,232 US6455357B2 (en) | 1998-06-05 | 2001-03-19 | Thin film transistor and method of fabricating the same |
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1998
- 1998-06-05 KR KR1019980020848A patent/KR100301803B1/en not_active IP Right Cessation
- 1998-07-29 TW TW087112416A patent/TW571443B/en not_active IP Right Cessation
- 1998-12-17 JP JP10358628A patent/JP3133987B2/en not_active Expired - Fee Related
-
1999
- 1999-04-09 DE DE19916073A patent/DE19916073B4/en not_active Expired - Lifetime
- 1999-05-25 US US09/317,952 patent/US6255668B1/en not_active Expired - Lifetime
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2001
- 2001-03-19 US US09/810,232 patent/US6455357B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
US6255668B1 (en) | 2001-07-03 |
DE19916073B4 (en) | 2006-07-27 |
JPH11354812A (en) | 1999-12-24 |
JP3133987B2 (en) | 2001-02-13 |
TW571443B (en) | 2004-01-11 |
DE19916073A1 (en) | 1999-12-16 |
KR20000000907A (en) | 2000-01-15 |
KR100301803B1 (en) | 2001-09-22 |
US6455357B2 (en) | 2002-09-24 |
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