US20010020861A1 - Delay circuit - Google Patents
Delay circuit Download PDFInfo
- Publication number
- US20010020861A1 US20010020861A1 US09/800,025 US80002501A US2001020861A1 US 20010020861 A1 US20010020861 A1 US 20010020861A1 US 80002501 A US80002501 A US 80002501A US 2001020861 A1 US2001020861 A1 US 2001020861A1
- Authority
- US
- United States
- Prior art keywords
- voltage
- load capacitance
- mos transistor
- type mos
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a delay circuit using MOS capacitors, and more particularly to a delay circuit formed within a semiconductor integrated circuit and capable of obtaining a stable delay effect even when signal voltage varies.
- 2. Description of the Related Art
- Conventionally, when clock centering adjustment or signal timing adjustment is performed in a wafer test step or a test step after assembly for a semiconductor integrated circuit, a MOS transistor for load capacitance is mainly used as a delay circuit. For example, a circuit used as the delay circuit is formed such that gates of a P-type MOS transistor for load capacitance and an N-type MOS transistor for load capacitance are connected to a clock line or a signal line, supply voltage VDD is applied to a terminal at which a source and a drain are joined together (hereinafter referred to as “source-drain”) of the P-type MOS transistor for load capacitance and ground voltage VGND is applied to a source-drain of the N-type MOS transistor for load capacitance. When a signal with an appropriate voltage is input to the signal line of this circuit, the MOS transistors act as capacitors which cause the signal current to be charged in the MOS transistors for load capacitance and thus to be outputted with a certain delay after the input.
- FIG. 1 shows an example of a conventional delay circuit.
Signal line 10 is connected to a gate of P-type MOS transistor 3 for load capacitance and to a gate of N-type MOS transistor 4 for load capacitance. Source-drains of theseMOS transistors CMOS inverters CMOS inverters resistor 8 is connected to an input terminal ofCMOS inverter 5. Output terminal ofinverter 7 is connected to input terminal ofCMOS inverter 6, while input terminal ofinverter 7 is connected to a fuse orresistor 8. - In the aforementioned circuit, switching of the fuse or
resistor 8 enables selection of voltages applied to the source-drains ofMOS transistors inverters MOS transistors MOS transistors signal line 10 to produce a delay effect for the signal. - The aforementioned delay circuit, however, has a problem of a narrow range of signal voltages in which stable load capacitances can be obtained. Such a tendency is significant especially when the supply voltage is low. More detailed description is hereinafter made with reference to FIG. 1. When fuse or
resistor 8 is at a low level, the voltage at the input terminal ofinverter 5 is at a low level, the P-type MOS transistor ininverter 5 is turned ON, and the N-type MOS transistor is turned OFF. Thus, the voltage at the source-drain of P-type MOS transistor 3 for load capacitance is at VDD. Since a signal through fuse orresistor 8 is reversed atinverter 7, a signal at a high level is input to the input terminal ofinverter 6. Therefore, the P-type MOS transistor ininverter 6 is turned OFF and the N-type MOS transistor is turned ON, and thus the voltage at the source-drain of N-type MOS transistor 4 for load capacitance is at VGND. - When a threshold voltage of the P-type MOS transistor is Vtp and a threshold voltage of the N-type MOS transistor is Vtn, a gate voltage for allowing P-
type MOS transistor 3 for load capacitance to have a load capacitance is equal to or lower than the voltage represented by VDD−Vtp, while a gate voltage for allowing N-type MOS transistor 4 for load capacitance to have a load capacitance is equal to or higher than the voltage represented by VGND+Vtn. - FIG. 2 shows ranges of gate voltages allowing to have load capacitances:
range 23 for allowing P-type MOS transistor 3 for load capacitance,range 21 for N-type MOS transistor for load capacitance andrange 22 effective for both P-type MOS transistor 3 and N-type MOS transistor 4 for load capacitance. Gate voltages range 22 in which both P-type MOS transistor 3 for load capacitance and N-type MOS transistor 4 for load capacitance have a load capacitance is from VGND+Vtn to VDD−Vtp. The range is narrower than the range of signal voltages when the latter extends from VGND to VDD. For this reason, a change in signal voltage may cause the inability to obtain a stable load capacitance value, leading to an unstable delay effect. Particularly, when the difference between the supply voltage and the ground voltage is smaller, the range of gate voltages in which both P-type MOS transistor 3 for load capacitance and N-type MOS transistor 4 for load capacitance have a load capacitance is further narrowed to present a more unstable delay effect. - The present invention has been made in view of such a problem, and it is an object thereof to provide a delay circuit which produces a stable delay effect even with changes in signal voltage.
- A delay circuit according to a first aspect of the present invention comprises a P-type MOS transistor for load capacitance whose gate is connected to a signal line and source and drain are connected to each other to make a source-drain, an N-type MOS transistor for load capacitance whose gate is connected to the signal line and source and drain are connected to each other to make a source-drain, first power supply means for applying a boosted voltage higher than supply voltage VDD to a source-drain of the P-type MOS transistor for load capacitance, and second power supply means for applying a substrate voltage lower than ground voltage VGND to a source-drain of the N-type MOS transistor for load capacitance.
- In this case, it is preferable that the delay circuit further comprises means for switching between the boosted voltage higher than supply voltage VDD and a voltage equal to or lower than ground voltage VGND as a voltage applied by the first power supply means to the source-drain of the P-type MOS transistor for load capacitance, and means for switching between a voltage equal to or higher than supply voltage VDD and the substrate voltage lower than ground voltage VGND as a voltage applied by the second power supply means to the source-drain of the N-type MOS transistor for load capacitance.
- A delay circuit according to a second aspect of the present invention comprises a P-type MOS transistor for load capacitance whose gate is connected to a signal line and source and drain are connected to each other to make a source-drain, an N-type MOS transistor for load capacitance whose gate is connected to the signal line and source and drain are connected to each other to make a source-drain, a first CMOS inverter having an output terminal connected to a source-drain of the P-type MOS transistor for load capacitance, first power supply means for applying a boosted voltage higher than supply voltage VDD to a higher potential side of the first CMOS inverter and for applying a voltage equal to or lower than ground voltage VGND to a lower potential side of the first CMOS inverter, a second CMOS inverter having an output terminal connected to a source-drain of the N-type MOS transistor for load capacitance, second power supply means for applying a voltage equal to or higher than supply voltage VDD to a higher potential side of the second CMOS inverter and for applying a substrate voltage lower than ground voltage VGND to a lower potential side of the second CMOS inverter, and switching means for applying a voltage for controlling the operations of the first and second CMOS inverters to the first and second CMOS inverters to switch between the voltage on the higher potential side and the voltage on the lower potential side as outputs from the first and second CMOS inverters.
- The switching means preferably includes an inverter having an output terminal connected to an input terminal of one of the first and second CMOS inverters and applies a potential with a phase reversed of the other CMOS inverters.
- In addition, the switching means may employ the inverter and a fuse, or the inverter and a resistor.
- FIG. 1 is a schematic diagram showing a conventional delay circuit;
- FIG. 2 is a diagram showing a gate voltage range in which MOS transistors for load capacitance have a capacitance to act as a capasitor in the conventional delay circuit;
- FIG. 3 is a schematic diagram showing a delay circuit in an embodiment of the present invention; and
- FIG. 4 is a diagram showing a gate voltage range in which MOS transistors for load capacitance have a capacitance to act as a capacitor in the delay circuit of the embodiment.
- An embodiment of the present invention is hereinafter described specifically with reference to the accompanying drawings. FIG. 3 shows a configuration of the embodiment of the present invention.
Buffer 1 andbuffer 2 for driving a signal current are disposed on the input side and the output side ofsignal line 10. A gate of P-type MOS transistor 3 for load capacitance and a gate of N-type MOS transistor 4 for load capacitance are connected betweenbuffer 1 andbuffer 2. A source-drain of P-type MOS transistor 3 for load capacitance is connected toCMOS inverter 5. Boosted voltage Vboot higher than supply voltage VDD is applied to a source of a P-type MOS transistor ofCMOS inverter 5, while ground voltage VGND is applied to a drain of an N-type MOS transistor thereof. A source-drain of N-type MOS transistor 4 for load capacitance is connected toCMOS inverter 6. Supply voltage VDD is applied to a source of a P-type MOS transistor ofCMOS inverter 6, while substrate voltage Vsub lower than ground voltage VGND is applied to a drain of an N-type MOS transistor thereof. An input terminal ofCOMS inverter 5 is connected toresistor 8, and an input terminal ofCMOS inverter 6 is connected toresistor 8 throughinverter 7. - Next, the operation of the embodiment is described.
Resistor 8 serving as means for switching a load capacitance selecting potential sets a load capacitance selecting potential at a low level. At this point, the input voltage toCMOS inverter 5 is at a low level, the P-type MOS transistor inCMOS inverter 5 is turned ON, and the N-type MOS transistor is turned OFF. Thus, the voltage at the source-drain of P-type MOS transistor 3 for load capacitance is at Vboot. Since a signal throughresistor 8 is reversed atinverter 7, a signal at a high level is inputted to the input terminal ofinverter 6. Therefore, since the P-type MOS transistor ininverter 6 is turned OFF and the N-type MOS transistor is turned ON, the voltage at the source-drain of N-type MOS transistor 4 for load capacitance is at Vsub. - In this case, a gate voltage range for allowing P-
type MOS transistor 3 for load capacitance to have a load capacitance includes voltages equal to or lower than the voltage represented by Vboot−Vtp, while a gate voltage range for allowing N-type MOS transistor 4 for load capacitance to have a load capacitance includes voltages equal to or higher than the voltage represented by Vsub+Vtn. Thus, when the load capacitance selecting potential is at the low level, both P-type MOS transistor 3 for load capacitance and N-type MOS transistor 4 for load capacitance have load capacitances to act as capacitors if signal voltages range from Vsub+Vtn to Vboot−Vtp. - Next, description is made for the operation when
resistor 8 sets the load capacitance selecting potential at a high level. In this case, the input voltage toCMOS inverter 5 is at a high level, the P-type MOS transistor inCMOS inverter 5 is turned OFF, and the N-type MOS transistor is turned ON. Thus, the voltage at the source-drain of P-type MOS transistor 3 for load capacitance is at VGND. A signal throughresistor 8 is reversed atinverter 7, and a signal at a low level is input to the input terminal ofCMOS inverter 6. Therefore, since the P-type MOS transistor inCMOS inverter 6 is turned ON and the N-type MOS transistor is turned OFF, the voltage at the source-drain of N-type MOS transistor 4 for load capacitance is at VDD. - In this case, a gate voltage range for allowing P-
type MOS transistor 3 for load capacitance to have a load capacitance includes voltages equal to or lower than the voltage represented by VGND−Vtp, while a gate voltage range for allowing N-type MOS transistor 4 for load capacitance to have a load capacitance includes voltages equal to or higher than the voltage represented by VDD+Vtn. Thus, when the load capacitance selecting potential is at the high level, none of P-type MOS transistor 3 for load capacitance and N-type MOS transistor 4 for load capacitance have load capacitances if signal voltages range from VGND to VDD, thereby presenting no delay effect for signals. - Next, the effects of the embodiment are described. FIG. 4 shows a
signal voltage range 12 effective for allowing both P-type MOS transistor 3 for load capacitance and N-type MOS transistor 4 for load capacitance to have load capacitances in the embodiment, comparing withrange 22 in the prior art shown in FIG. 2. When the load capacitance selecting potential is at the low level, the range of signal voltages for allowing both P-type MOS transistor 3 for load capacitance and N-type MOS transistor 4 for load capacitance to have capacitances r is from Vsub+Vtn to Vboot−Vtp, which is wider than the signal voltage range in the prior art by the voltage value represented by Vboot−VDD+VGND−Vsub. Thus, the embodiment can produce a more stable delay effect for changes in signal voltage than the prior art. - The aforementioned embodiment provides an example in which
inverter 7 is disposed betweenCMOS inverter 6 andresistor 8 such that P-type MOS transistor 3 for load capacitance and N-type MOS transistor 4 for load capacitance have load capacitances when the load capacitance selecting potential is at the low level. The present invention, however, also includes a delay circuit in whichinverter 7 is disposed betweenCMOS inverter 5 andresistor 8 such that P-type MOS transistor 3 for load capacitance and N-type MOS transistor 4 for load capacitance have load capacitances when the load capacitance selecting potential is at the high level. - While the embodiment employs a resistor as means for switching a load capacitance selecting potential, a fuse may be used. Another means which can switch voltages applied to the input terminals of
CMOS inverters CMOS inverters CMOS inverters - The aforementioned embodiment provides an example in which one P-type MOS transistor for load capacitance and one N-type MOS transistor for load capacitance are used. The present invention, however, also includes a delay circuit in which a plurality of one or both of two types of transistors are used.
- In addition, the present invention includes a delay circuit in which the gate structure of a transistor for load capacitance comprises a control gate and a floating gate as in a memory cell of a flash memory, and electrons are injected into or drawn from the floating gate to change a threshold voltage of the MOS transistor for load capacitance, thereby controlling a gate voltage range for allowing the MOS transistor for load capacitance to have a load capacitance.
- The present invention also includes a delay circuit in which ions are implanted into a MOS transistor for load capacitance to change a threshold voltage of the MOS transistor for load capacitance, thereby controlling a gate voltage range for allowing the MOS transistor for load capacitance to have a load capacitance.
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-062998 | 2000-03-08 | ||
JP2000062998A JP3586612B2 (en) | 2000-03-08 | 2000-03-08 | Delay circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010020861A1 true US20010020861A1 (en) | 2001-09-13 |
US6448833B2 US6448833B2 (en) | 2002-09-10 |
Family
ID=18582931
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/800,025 Expired - Lifetime US6448833B2 (en) | 2000-03-08 | 2001-03-06 | Delay circuit |
Country Status (3)
Country | Link |
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US (1) | US6448833B2 (en) |
JP (1) | JP3586612B2 (en) |
KR (1) | KR100367312B1 (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004034404A2 (en) * | 2002-10-08 | 2004-04-22 | Impinj, Inc. | Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined |
US6909389B1 (en) | 2002-06-14 | 2005-06-21 | Impinj, Inc. | Method and apparatus for calibration of an array of scaled electronic circuit elements |
US20050140449A1 (en) * | 2002-10-08 | 2005-06-30 | Impiji, Inc., A Delaware Corporation | Use of analog-valued floating-gate transistors for parallel and serial signal processing |
US20060236203A1 (en) * | 2005-03-24 | 2006-10-19 | Diorio Christopher J | Error recovery in RFID reader systems |
US20070188249A1 (en) * | 2006-02-14 | 2007-08-16 | International Business Machines Corporation | Programmable capacitors and methods of using the same |
US9337816B2 (en) | 2014-01-27 | 2016-05-10 | Fuji Electric Co., Ltd. | Delay circuit using capacitor as delay element |
CN115395943A (en) * | 2022-10-26 | 2022-11-25 | 深圳芯能半导体技术有限公司 | Level shift circuit and switching tube drive circuit |
US11528020B2 (en) | 2020-11-25 | 2022-12-13 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
US11550350B2 (en) | 2020-11-25 | 2023-01-10 | Changxin Memory Technologies, Inc. | Potential generating circuit, inverter, delay circuit, and logic gate circuit |
US11681313B2 (en) | 2020-11-25 | 2023-06-20 | Changxin Memory Technologies, Inc. | Voltage generating circuit, inverter, delay circuit, and logic gate circuit |
US11887652B2 (en) | 2020-11-25 | 2024-01-30 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
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WO2004088834A1 (en) * | 2003-03-27 | 2004-10-14 | Fujitsu Limited | Varactor capacitor improving temperature variation |
KR100558600B1 (en) * | 2005-02-02 | 2006-03-13 | 삼성전자주식회사 | Delay circuit in semiconductor device |
CN101009484B (en) * | 2006-01-28 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Novel single-end unit delay part |
US8179208B2 (en) * | 2007-10-23 | 2012-05-15 | Oracle America, Inc. | Interconnect for surfing circuits |
CN102237675B (en) | 2010-04-26 | 2014-07-23 | 鸿富锦精密工业(深圳)有限公司 | Electronic device |
US11264974B2 (en) | 2020-03-18 | 2022-03-01 | Mediatek Inc. | Processing circuit using delay element coupled between control terminal and connection terminal of input transistor for hold time violation immunity |
CN114545807B (en) * | 2020-11-25 | 2024-03-26 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2685203B2 (en) * | 1988-02-22 | 1997-12-03 | 富士通株式会社 | Delay circuit |
JPH0413305A (en) * | 1990-05-02 | 1992-01-17 | Toshiba Corp | Delay circuit |
JPH0661810A (en) | 1992-08-12 | 1994-03-04 | Hitachi Ltd | Variable delay circuit and semiconductor integrated circuit device using it |
JPH0746098A (en) * | 1993-08-03 | 1995-02-14 | Nec Corp | Delay circuit |
US5386151A (en) | 1993-08-11 | 1995-01-31 | Advanced Micro Devices, Inc. | Low voltage charge pumps using p-well driven MOS capacitors |
GB2289178B (en) * | 1993-11-09 | 1998-05-20 | Motorola Inc | Circuit and method for generating a delayed output signal |
US5539348A (en) * | 1994-03-17 | 1996-07-23 | Advanced Micro Devices, Inc. | Precise delay line circuit with predetermined reset time limit |
JP3561012B2 (en) * | 1994-11-07 | 2004-09-02 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
JPH10125801A (en) * | 1996-09-06 | 1998-05-15 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
JP3338758B2 (en) * | 1997-02-06 | 2002-10-28 | 日本電気株式会社 | Delay circuit |
KR100428688B1 (en) * | 1997-06-26 | 2004-07-19 | 주식회사 하이닉스반도체 | Delay apparatus according to power supply voltage, in which paths of high power supply voltage and a low power supply voltage are implemented separately |
KR100271633B1 (en) * | 1997-11-01 | 2000-11-15 | 김영환 | Delay circuit |
KR100289385B1 (en) * | 1997-12-02 | 2001-05-02 | 김영환 | Delay circuit |
US6154078A (en) * | 1998-01-07 | 2000-11-28 | Micron Technology, Inc. | Semiconductor buffer circuit with a transition delay circuit |
-
2000
- 2000-03-08 JP JP2000062998A patent/JP3586612B2/en not_active Expired - Fee Related
-
2001
- 2001-03-02 KR KR10-2001-0010730A patent/KR100367312B1/en not_active IP Right Cessation
- 2001-03-06 US US09/800,025 patent/US6448833B2/en not_active Expired - Lifetime
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6909389B1 (en) | 2002-06-14 | 2005-06-21 | Impinj, Inc. | Method and apparatus for calibration of an array of scaled electronic circuit elements |
WO2004034404A2 (en) * | 2002-10-08 | 2004-04-22 | Impinj, Inc. | Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined |
US20040124892A1 (en) * | 2002-10-08 | 2004-07-01 | Impinj, Inc., A Delaware Corporation | Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined circuits |
WO2004034404A3 (en) * | 2002-10-08 | 2004-09-23 | Impinj Inc | Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined |
US20050140449A1 (en) * | 2002-10-08 | 2005-06-30 | Impiji, Inc., A Delaware Corporation | Use of analog-valued floating-gate transistors for parallel and serial signal processing |
US20050140448A1 (en) * | 2002-10-08 | 2005-06-30 | Impiji, Inc., A Delaware Corporation | Use of analog-valued floating-gate transistors for parallel and serial signal processing |
US7049872B2 (en) | 2002-10-08 | 2006-05-23 | Impinj, Inc. | Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined circuits |
US20060145744A1 (en) * | 2002-10-08 | 2006-07-06 | Impinj, Inc. | Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined circuits |
US20060236203A1 (en) * | 2005-03-24 | 2006-10-19 | Diorio Christopher J | Error recovery in RFID reader systems |
US7405660B2 (en) | 2005-03-24 | 2008-07-29 | Impinj, Inc. | Error recovery in RFID reader systems |
US20070188249A1 (en) * | 2006-02-14 | 2007-08-16 | International Business Machines Corporation | Programmable capacitors and methods of using the same |
US7358823B2 (en) * | 2006-02-14 | 2008-04-15 | International Business Machines Corporation | Programmable capacitors and methods of using the same |
US9337816B2 (en) | 2014-01-27 | 2016-05-10 | Fuji Electric Co., Ltd. | Delay circuit using capacitor as delay element |
US11528020B2 (en) | 2020-11-25 | 2022-12-13 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
US11550350B2 (en) | 2020-11-25 | 2023-01-10 | Changxin Memory Technologies, Inc. | Potential generating circuit, inverter, delay circuit, and logic gate circuit |
US11681313B2 (en) | 2020-11-25 | 2023-06-20 | Changxin Memory Technologies, Inc. | Voltage generating circuit, inverter, delay circuit, and logic gate circuit |
US11887652B2 (en) | 2020-11-25 | 2024-01-30 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
CN115395943A (en) * | 2022-10-26 | 2022-11-25 | 深圳芯能半导体技术有限公司 | Level shift circuit and switching tube drive circuit |
Also Published As
Publication number | Publication date |
---|---|
KR100367312B1 (en) | 2003-01-09 |
JP3586612B2 (en) | 2004-11-10 |
KR20010088371A (en) | 2001-09-26 |
JP2001251171A (en) | 2001-09-14 |
US6448833B2 (en) | 2002-09-10 |
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