US20010024861A1 - Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions - Google Patents
Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions Download PDFInfo
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- US20010024861A1 US20010024861A1 US09/861,404 US86140401A US2001024861A1 US 20010024861 A1 US20010024861 A1 US 20010024861A1 US 86140401 A US86140401 A US 86140401A US 2001024861 A1 US2001024861 A1 US 2001024861A1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
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Abstract
Description
- The present invention relates to a method for manufacturing electronic devices having high voltage (HV) transistors and low voltage (LV) transistors with salicided junctions.
- In advanced processes (gate lengths of 0.35 μm or less), the need has recently arisen to integrate HV transistors in high-speed devices which use the technique of saliciding the diffusions. As is known, this technique is based on the use of a layer of self-aligned silicide (“salicide”), which reduces the resistivity of the junctions. The salicide layer (typically of titanium, but also cobalt or another transition metal) is obtained by depositing a titanium layer on the entire surface of the device, and performing a heat treatment that makes the titanium react with the silicon, which is left bare on the junctions and the gate regions, such as to form titanium silicide. Subsequently, the non-reacted titanium (for example that deposited on oxide regions), is removed by etching with an appropriate solution, which leaves the titanium silicide intact. Thereby, both the gate regions and the junctions have in parallel a layer of silicide with low resistivity (approximately 3-4 Ω/square), which makes it possible to reduce the resistance in series at the transistors. The salicide technique is described for example in the article “Application of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxide-semiconductor and complementary metal-oxide-semi-conductor technologies” by R. A. Haken, in J. Vac. Sci. Technol. B, vol. 3, No. 6, November/December 1985.
- The HV transistors are formed without intensive implanting doping ionic species, to obtain lightly doped junctions, which thus have a high breakdown voltage. The saliciding process is difficult if the silicon beneath is lightly doped, and this means that it is necessary to avoid saliciding the junctions of the HV transistors.
- Process flows are thus being designed which permit integration of HV transistors and LV transistors with saliciding; however this integration is made difficult by the fact that these components have different characteristics, and require different process steps.
- The invention described herein provides a method for manufacturing high-speed HV transistors and LV transistors that is simple and has the lowest possible costs.
- According to the invention, a method is provided for manufacturing electronic devices comprising high-speed HV transistors and LV transistors with salicided junctions.
- Hereinafter, a production process will be described, aimed to produce EEPROM memory cells, besides LV and HV transistors; however, the invention relates in general to the production of LV and HV transistors, irrespective of the memory cells and the specific process described.
- For the understanding of the present invention, a preferred embodiment is now described, purely by way of non-limiting example, with reference to the attached drawings, in which:
- FIG. 1 shows a cross-section through a silicon wafer, in an initial step of the manufacturing method according to the invention;
- FIG. 2 shows a view from above of the wafer of FIG. 1;
- FIGS.3-7 show cross-sections similar to FIG. 1, in successive manufacturing steps;
- FIG. 8 shows a view from above of the wafer of FIG. 7;
- FIGS.9-11 show cross-sections similar to FIG. 7, in successive manufacturing steps;
- FIG. 12 shows a view from above of the wafer of FIG. 11;
- FIG. 13 shows a cross-section similar to FIG. 11, in a successive manufacturing step;
- FIG. 14 is a cross-section, taken along lines XIV-XIV of FIG. 13;
- FIG. 15 shows a view from above of the wafer of FIG. 13;
- FIGS.16-19 show cross-sections similar to FIG. 13, in successive manufacturing steps;
- FIG. 20 shows a view from above of the wafer of FIG. 19; and
- FIGS.21-23 show cross-sections similar to FIG. 19, in successive manufacturing steps.
- The following description relates to an embodiment for forming LV (low voltage and high speed) and HV (high voltage) NMOS transistors, LV and HV PMOS transistors, and EEPROM memory cells, comprising a selection transistor and a memory transistor. In particular, in view of the duality in manufacturing NMOS and PMOS transistors, the drawings show only the steps relating to NMOS transistors, and the steps relating to PMOS transistors are described in words alone. The EEPROM cells form a memory array, and are produced in a part of the wafer which is also known hereinafter as
array zone 15. - In FIG. 1, a
wafer 1, formed from amonocrystalline silicon substrate 2, which here is of P-type, has been subjected to the steps of defining the active areas. In detail, with thesurface 3 ofsubstrate 2 covered by anactive area mask 4 of non-oxidizable material (typically comprising a double layer of silicon oxide and silicon nitride, defined through resist),wafer 1 has been subjected to thermal oxidation; consequently, on the parts ofsubstrate 2 which are not covered byactive area mask 4, thick oxide (field oxide)layers 5 have been grown, which delimit between one another active areas of the substrate designed to accommodate the various components of the device to be formed. In particular, FIG. 1 shows three active areas, anactive LV area 6, which is designed to accommodate an LV NMOS transistor, anactive HV area 7, which is designed to accommodate an HV NMOS transistor, and anactive array area 8, which is designed to accommodate EEPROM memory cells. - In detail, and in a known manner,
active array area 8 defines a grid, of which FIG. 2 shows in full only the part of one cell, showed at 9, which has substantially the shape of a “T” rotated by 90°, and comprises aleg 9 a (far from active HV area 7) and across-piece 9 b. Theleg 9 a is adjacent, and is electrically connected, tocorresponding legs 9 a of other cells, which are arranged above and below the shown cell, and of which only parts are shown; in addition,leg 9 a is connected to a leg of an adjacent cell to the right (not shown), which has a structure that is symmetrical to that shown. Thelegs 9 a are designed to accommodate source regions of the memory transistors; the end ofcross-pieces 9 b are designed to accommodate drain regions of the selection transistors; and gate regions of the cells must be formed on thecross-pieces 9 b. Further active areas are generally provided in order to produce LV or HV PMOS transistors, which are not shown in the drawings. - Subsequently the
active area mask 4 is removed, oxidation of thefree surface 3 of the substrate is carried out to form asacrificial oxide layer 10, and masked implanting of doping ionic species of N-type is carried out to form N-HV regions (not shown) for HV PMOS transistors; then, using an HV P-well resist mask 11 that covers the entire surface ofwafer 1, except the HVactive area 7 and thearray area 8, implanting of doping ionic species of P-type is carried out, as shown schematically in FIG. 3 byarrows 12. In thesubstrate 2, P-HV regions 13 of P-type are thus formed for high-voltage transistors, and a P-array region 14, also of P-type, is formed for the cells, as shown in FIG. 3. P-HV region 13 and P-array region 14 reproduce exactly the shape of the respective HVactive area 7 andarray area 8, and thus, for each cell,legs 14 a (corresponding tolegs 9 a of the cellactive areas 9 of cell, see FIG. 8), andcross-pieces 14 b (FIG. 8, corresponding to thecross-pieces 9 b) are shown. - After HV P-
well mask 11 has been removed, masked implanting of doping ionic species of N-type is carried out, to form N-LV regions (not shown) for LV PMOS transistors; then, using an LV P-well resist mask 17 which covers the entire surface ofwafer 1, except for the LVactive areas 6, implanting of doping ionic species of P-type is carried out, as shown schematically in FIG. 4 byarrows 18. In thesubstrate 2, P-LV regions 19 of P-type are thus formed for the LV NMOS transistors, as shown in FIG. 3. Thereby, P-HV regions 13 and P-LV regions 19 are separated from one another, and their electrical characteristics can be optimised to the required electrical characteristics. - After LV P-
well mask 17 has been removed, acapacitor mask 20 is formed, which covers the entire surface ofwafer 1, with the exception of strips perpendicular to thecross-pieces 14 b. Implanting of doping species of N-type (for example phosphorous) is then carried out, as shown schematically in FIG. 5 byarrows 21. In thecross-pieces 14b continuity regions 22, of N-type, are thus formed which are necessary for electrical continuity between each selection transistor and the corresponding memory transistor of each cell. The structure in FIG. 5 is thus obtained. - After
capacitor mask 20 has been removed,wafer 1 is subjected to annealing,sacrificial layer 10 is removed, and array oxidation is carried out, which leads to the formation of anarray oxide layer 25 on the surface of all theregions array oxide layer 25 is removed from above thecontinuity region 22; after the tunnel mask has been removed,wafer 1 is oxidized again, and in the zone where thearray oxide 25 had been removed, atunnel oxide region 26 with a thickness of approximately 80 Å is formed, in a known manner. The structure in FIG. 6 is thus obtained. - A first polycrystalline silicon layer (poly1 layer27) is then deposited, and is suitably doped; a
floating gate mask 28 is then formed which covers all the surface ofwafer 1, except for windows that exposelegs 14 a (FIG. 8) and thefield oxide regions 5, laterally to thecross-pieces 14 b adjacent to thelegs 14 a, as shown in FIG. 8. Then, through thefloating gate mask 28,poly1 layer 27 is removed where it is exposed. In particular, the portions ofpoly1 layer 27 removed laterally to thecross-pieces 14 b, formvertical walls 27′, which are arranged on two opposite sides of a quadrilateral, and the width of which (shown vertically in FIG. 8) defines the floating gate regions of the memory transistors, and the portions of thepoly1 layer 27 removed from above thelegs 14 a form avertical wall 27″, which is disposed on a third side of the quadrilateral (FIG. 8). On the other hand, thepoly1 layer 27 is not removed where the selection transistors are to be formed. Subsequently, implanting of doping ionic species of N-type is carried out, as shown schematically byarrows 29 in FIG. 7, to reduce the resistance of the source lines.First source regions 30 of the memory transistors are then formed, at thelegs 14 a of the P-array region 14, as shown in FIG. 7. - After the
floating gate mask 28 has been removed, an interpolydielectric layer 31 is formed, which for example comprising a triple layer of ONO (silicon oxide-silicon nitride-silicon oxide), which, inter alia, covers thevertical walls 27′ and 27″(FIG. 8) ofpoly1 layer 27, for electrically isolating the floating gate regions of adjacent cells. Amatrix mask 33 is then formed, which covers the surface ofwafer 1, at thearray zone 15, and leaves exposed all the N and P regions designed to accommodate LV and HV, NMOS and PMOS transistors, including regions P-HV 13 and P-LV 19; using thematrix mask 33, interpolydielectric layer 31,poly1 layer 27, andarray oxide layer 25 are etched in succession, where they are exposed. Thus the structure of FIG. 9 is obtained. - After
matrix mask 33 has been removed, an HV oxidation step is carried out, thus forming an HVgate oxide layer 34 on the entire free surface of thesubstrate 2, and in particular on regions P-LV 19 and P-HV 13. A thin oxide layer (not shown) is also formed on theinterpoly dielectric layer 31. Subsequently, using an HV resistoxide mask 35, which covers regions P-HV 13 andarray zone 15, the HVgate oxide layer 34 is removed from above the regions P-LV 19, as shown in FIG. 10. - After the
HV oxide mask 35 has been removed, an LV oxidation step is carried out, thus forming an LVgate oxide layer 36 on regions P-LV 19, increases the thickness of the HVgate oxide layer 34 on regions P-HV 13, and (with the layer previously formed), forms athin oxide layer 38 on theinterpoly dielectric layer 31 in thearray zone 15. Subsequently, aselect mask 39 is formed, which covers completely the zones designed to accommodate LV and HV, NMOS and PMOS transistors, as well as, in thearray zone 15,cross-pieces 14 b and portions oflegs 14 a, as shown in FIG. 12. In practice,select mask 39 exposes most of the firstcell source regions 30 and pairs of zones 40 (FIG. 12) ofwafer 1, which are arranged on both sides of the free end portion of each cross-piece 14 b. Usingselect mask 39, the exposed portions ofthin oxide layer 38,interpoly dielectric layer 31, andpoly1 layer 27, are removed in succession. The dimensions ofselect mask 39 are such as to leaveportions 31 a ofdielectric layer 31 on thewalls 27″ of thepoly1 layer 27, and to remove virtually all the rest of thedielectric layer 31 from above thearray oxide layer 25. In addition, the pairs ofzones 40 make it possible to obtainvertical walls 27 a (FIG. 14), which are uncovered, for the purpose indicated hereinafter. The structure in FIG. 11 is thus obtained. - After
select mask 39 has been removed, a second polycrystalline layer (poly2 layer 43) is deposited and doped; owing to the removal ofzones 40,poly2 layer 43 is in direct contact with thewalls 27 a ofpoly1 layer 27, as can be seen in the cross-section of FIG. 14. Thereby, lower and upper portions of the gate region of the selection transistor of the cell are shorted to one another. AnLV gate mask 44 is then formed, which covers the regions N-HV (which are not shown), the regions P-HV 13, and thearray zone 15, except for the firstcell source regions 30; in addition, theLV gate mask 44 covers the poly2 layer on the regions P-LV 19, where the gate regions of the LV NMOS transistors are to be defined, as shown in FIGS. 13 and 15, and on the N-LV regions (which are not shown), where the gate regions of the LV PMOS transistors are to be defined. The exposed portions ofpoly2 layer 43 and of LV gate oxide layer 36 (as well as of thin oxide layer 38) are then removed, providing the intermediate structure of FIG. 13, wherein the remaining portions of poly2 on the regions P-LV 19form gate regions 43 a of the LV NMOS transistors. As shown, while defining the gate regions of the LV transistors, the layers over the regions P-HV 13 are protected, as are the layers on the regions N-HV (which are not shown); consequently, the method described provides separate definition of the gate regions of the LV transistors and the HV transistors. - After removal of
LV gate mask 44, wafer I is subjected to oxidation, such that anoxide layer 46 grows on the exposed portions of regions P-LV 19, at the sides ofgate regions 43 a, on the exposed portions of the regions N-LV (which are not shown), on the poly2 layer, and on the secondcell source regions 49. Using a resist mask, which is not shown, which covers the regions N-LV and N-HV, doping ionic species of N-type are implanted (LDDN implanting), as schematised byarrows 47 in FIG. 16. At the sides of thegate regions 43 a (inside regions P-LV 19),LDD regions 48 of N-type are then formed; inside the firstcell source regions 30, aligned with theportions 31 a ofdielectric layer 31, secondcell source regions 49 of N-type are formed, which are more highly doped than firstcell source regions 30; in addition thepoly2 layer 43 is suitably doped. The structure in FIG. 16 is thus obtained. - After the resist mask, not shown, has been removed, doping ionic species of P-type are implanted through a mask; in particular, during this step, regions P-
HV 13 and P-LV 19, as well asarray zone 15 are covered, whereas in the regions N-LV, LDD regions of P-type (which are not shown) are formed. A dielectric layer (for example TEOS-TetraEthylOrthoSilicate) is then deposited on the entire surface ofwafer 1; then, in a known manner, the TEOS layer is subjected to anisotropic etching and is removed completely from the horizontal portions, and remains only at the sides of thegate regions 43 a (where it forms spacers 52), and on the right-hand side of thepoly1 layer 27 and poly2 layer 43 (on the first and secondcell source regions field oxide regions 5, since the edges of the latter have the shape of a bird's beak (formed in a per se known manner, not shown for the sake of simplicity); in addition, no spacers are formed above regions P-HV 13, and corresponding regions N-HV, since the gate regions of the HV transistors are not yet defined.Oxide layer 46 is also removed in this step. Subsequently, using a resist mask, not shown, which covers the regions N-LV and NHV, implanting of doping ionic species of N-type is carried out, as schematised in FIG. 17 byarrows 54. LV-NMOS source and drainregions 55 of N+-type are then formed in regions P-LV 19, self-aligned with thespacers 52, and thirdcell source regions 56 of N+-type are formed, self-aligned with thespacers 53 in the P-array region 14. LV-NMOS source and drainregions 55 are more doped thanLDD regions 48, andthird source regions 56 are more doped than secondcell source regions 49. In addition,poly2 layer 43 andgate regions 43 a are doped of N-type, whereas the zones where HV and LV PMOS transistors are to be formed are covered. Then the structure of FIG. 17 is obtained. - After the resist mask (not shown) has been removed, a similar step of masked implanting of doping ionic species of P-type is carried out, for forming the respective source and drain regions in the N-LV regions (in a not shown manner), and for P-type
doping poly2 layer 43 above the regions P-LV and P-HV. In this step, the regions P-LV, P-HV and P-array are fully covered. Saliciding of the exposed layer of poly2 is then carried out. The saliciding, which is carried out in a known manner, as already described, causes the formation of regions of titanium silicide above the source and drain regions of LV NMOS and PMOS transistors (silicide regions 57 a 1 above LVNMOS source and drainregions 55, and similar regions for the LV PMOS transistors), above the gate regions of LV NMOS and PMOS transistors (silicide regions 57 a 2 abovegate regions 43 a for the LV NMOS transistors, and similar regions for the LV PMOS transistors), above the third cell source regions 56 (silicide regions 57 b 1), and above the EEPROM cells and the HV zones (silicide regions 57, where the gate regions are not yet defined), as shown in FIG. 18. - Subsequently an
HV gate mask 60 is formed, which covers the entire surface ofwafer 1, with the exception of the active areas where high voltage transistors are to be formed (P-HV regions 13, in case of HV NMOS) and the EEPROM cells; in particular,mask 60 covers the zone where the gate regions of the high voltage transistors are to be defined; the gate regions of the selection transistors and the gate and source regions of the memory transistors (in this respect see also FIG. 20, which showsHV gate mask 60 from above). The portions ofsilicide layer 57 and ofpoly2 43 layer which are not covered by theHV gate mask 60 are then etched. Thus the structure of FIG. 19 is obtained, wherein the control gate region of the memory transistor is indicated at 43 b, the upper portion of the gate region of the selection transistor (which is shorted to the lower portion, as already described) is indicated at 43 c, and the gate region of the HV NMOS transistor is indicated at 43 d; the corresponding portions of salicide are indicated at 57b regions - Without removing the
HV gate mask 60, a self-alignedmask 61 is formed, which covers completely the zone of the LV and HV, NMOS and PMOS transistors, and the zones above thecell source regions HV gate mask 60 and self-alignedmask 61, the exposed portions ofthin oxide layer 38,interpoly dielectric layer 31, andpoly1 layer 27 are etched. Thus floatinggate regions 27 b of the memory transistors andlower portions 27 c of the selection transistors are formed, as can be seen in FIG. 21. In practice, while defining thegate regions cell source regions gate regions - After
HV gate mask 60 and self-alignedmask 61 have been removed, anNHV mask 62 is formed, which covers the regions N-LV and N-HV (which are not shown), and the regions P-LV 19. UsingNHV mask 62, doping ionic species of N-type are implanted, as shown schematically in FIG. 22 byarrows 63. In the regions P-HV 13, at both sides of theHV gate regions 43 d, HV-NMOS source and drainregions 64 of N-type are thus formed, which are less doped than LV-NMOS source and drainregions 55; simultaneously, in P-array region 14, selection source and drainregions upper portion 43 c andlower portion 27 c of the gate region of the selection transistors. Selection source and drainregions regions 55, and than thirdcell source regions 56, and thus they have a higher breakdown voltage, as well as greater resistivity. - After
NHV mask 62 has been removed, the source and drain regions of the HV PMOS transistors (which are not shown) are similarly masked implanted; aprotective dielectric layer 66 is then deposited, providing the structure of FIG. 23, wherein anLV NMOS transistor 70, anHV NMOS transistor 71, and anEEPROM cell 72, comprising aselection transistor 73 and amemory transistor 74, are shown. Final steps then follow, including forming contacts and electrical interconnection lines, depositing a passivation layer etc. - Thus, in the final device,
EEPROM cells 72 have selection source and drain regions 65 with high breakdown voltages; third source regions 56 (which form source lines) which are planar (unlike those obtained by known self-aligned processes, wherein the etching for defining the cell gate regions gives rise to trenches in substrate 2); first source regions (LDD cell regions) 30, self-aligned with the floatinggate regions 27 b; source lines 56,control gate lines 43 b, andupper portions 43 c of the gate regions of theselection transistors 73 with low resistivity;control gate regions 43 b and floatinggate regions 27 b self-aligned on a single side (towards theregions 65 b which define the drain regions of thememory transistors 74 and the source regions of the selection transistors 73); and gate regions of theselection transistors 73, formed by a structure with two polysilicon levels which are shorted to one another. - The LV (NMOS and PMOS) transistors have a high-speed LDD structure with a dual gate (
gate region 43 a doped with doping ionic species of the same type as source and drainregions 48, 55); with salicized source and drainregions 55 andgate region 43 a. - The HV (NMOS and PMOS) transistors have a dual gate and drain extension structure, with
salicized gate region 43 d alone. - The described method thus allows simultaneous production of LV, HV and memory components which have very different characteristics, optimising the number of necessary steps.
- Finally, it is apparent that many modifications and variations can be made to the method and the device described and illustrated here, all of which come within the scope of the invention, as defined in the attached claims.
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/861,404 US6420769B2 (en) | 1998-07-22 | 2001-05-18 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions |
Applications Claiming Priority (7)
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EP98830443 | 1998-07-22 | ||
EP98830443 | 1998-07-22 | ||
EP98830443.2 | 1998-07-22 | ||
EP98120033A EP0975020B1 (en) | 1998-07-22 | 1998-10-22 | Method for manufacturing electronic devices and corresponding devices comprising HV transistors and LV transistors with salicided junctions |
EP98120033 | 1998-10-22 | ||
US09/359,923 US6251728B1 (en) | 1998-07-22 | 1999-07-22 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions |
US09/861,404 US6420769B2 (en) | 1998-07-22 | 2001-05-18 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions |
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US09/359,923 Division US6251728B1 (en) | 1998-07-22 | 1999-07-22 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions |
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US20010024861A1 true US20010024861A1 (en) | 2001-09-27 |
US6420769B2 US6420769B2 (en) | 2002-07-16 |
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US09/359,923 Expired - Lifetime US6251728B1 (en) | 1998-07-22 | 1999-07-22 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions |
US09/861,404 Expired - Lifetime US6420769B2 (en) | 1998-07-22 | 2001-05-18 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions |
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US09/359,923 Expired - Lifetime US6251728B1 (en) | 1998-07-22 | 1999-07-22 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions |
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Cited By (1)
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FR2856519A1 (en) * | 2003-06-20 | 2004-12-24 | Samsung Electronics Co Ltd | DEVICE FOR PROCESSING DATA ONLY A CHIP WITH INTEGRATED REMANENT MEMORY, AND METHOD OF FORMATION |
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EP0986100B1 (en) * | 1998-09-11 | 2010-05-19 | STMicroelectronics Srl | Electronic device comprising EEPROM memory cells, HV transistors, and LV transistors with silicided junctions, as well as manufacturing method thereof |
US6350652B1 (en) * | 1998-10-23 | 2002-02-26 | Stmicroelectronics S.R.L. | Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions |
WO2001047012A1 (en) * | 1999-12-21 | 2001-06-28 | Koninklijke Philips Electronics N.V. | Non-volatile memory cells and periphery |
US6482723B1 (en) * | 2000-09-21 | 2002-11-19 | National Semiconductor Corporation | Method for forming self-aligned floating gates |
JP2003023114A (en) * | 2001-07-05 | 2003-01-24 | Fujitsu Ltd | Semiconductor integrated circuit device and its manufacturing method |
KR100399350B1 (en) * | 2001-08-09 | 2003-09-26 | 삼성전자주식회사 | Non volatile memory having floating trap type device and method of forming the same |
US6933199B1 (en) | 2003-10-15 | 2005-08-23 | Microchip Technology Incorporated | Method for integrating non-volatile memory with high-voltage and low-voltage logic in a salicide process |
US20050110083A1 (en) * | 2003-11-21 | 2005-05-26 | Gammel Peter L. | Metal-oxide-semiconductor device having improved gate arrangement |
JP2005197308A (en) * | 2003-12-26 | 2005-07-21 | Toshiba Corp | Nonvolatile semiconductor storage device |
KR100564629B1 (en) * | 2004-07-06 | 2006-03-28 | 삼성전자주식회사 | EEPROM device and manufacturing method therefor |
TWI263334B (en) * | 2004-12-13 | 2006-10-01 | United Microelectronics Corp | High voltage devices and method of fabricating the same |
US7691751B2 (en) | 2007-10-26 | 2010-04-06 | Spansion Llc | Selective silicide formation using resist etchback |
US9691750B2 (en) * | 2015-01-30 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and layout method thereof |
US10825522B2 (en) | 2018-10-29 | 2020-11-03 | United Microelectronics Corp. | Method for fabricating low and high/medium voltage transistors on substrate |
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US5283449A (en) * | 1990-08-09 | 1994-02-01 | Nec Corporation | Semiconductor integrated circuit device including two types of MOSFETS having source/drain region different in sheet resistance from each other |
KR960012303B1 (en) * | 1992-08-18 | 1996-09-18 | 삼성전자 주식회사 | Non-volatile semiconductor memory device and manufacturing thereof |
US5472887A (en) * | 1993-11-09 | 1995-12-05 | Texas Instruments Incorporated | Method of fabricating semiconductor device having high-and low-voltage MOS transistors |
JP3238576B2 (en) * | 1994-08-19 | 2001-12-17 | 株式会社東芝 | Nonvolatile semiconductor memory device |
JPH09283643A (en) * | 1996-04-19 | 1997-10-31 | Rohm Co Ltd | Semiconductor device and manufacture of semiconductor device |
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JPH10270571A (en) * | 1997-03-26 | 1998-10-09 | Seiko Epson Corp | Semiconductor device and its manufacture |
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EP0975022A1 (en) * | 1998-07-22 | 2000-01-26 | STMicroelectronics S.r.l. | Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors, with salicided junctions |
TW428311B (en) * | 1998-08-25 | 2001-04-01 | United Microelectronics Corp | Manufacturing method for embedded DRAM |
US6110782A (en) * | 1998-11-19 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Method to combine high voltage device and salicide process |
US6258648B1 (en) * | 1999-02-08 | 2001-07-10 | Chartered Semiconductor Manufacturing Ltd. | Selective salicide process by reformation of silicon nitride sidewall spacers |
US6096595A (en) * | 1999-05-12 | 2000-08-01 | Taiwan Semiconductor Manufacturing Company | Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices |
-
1998
- 1998-10-22 EP EP98120033A patent/EP0975020B1/en not_active Expired - Lifetime
- 1998-10-22 EP EP08021768A patent/EP2034518A3/en not_active Ceased
-
1999
- 1999-07-22 US US09/359,923 patent/US6251728B1/en not_active Expired - Lifetime
-
2001
- 2001-05-18 US US09/861,404 patent/US6420769B2/en not_active Expired - Lifetime
Cited By (4)
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FR2856519A1 (en) * | 2003-06-20 | 2004-12-24 | Samsung Electronics Co Ltd | DEVICE FOR PROCESSING DATA ONLY A CHIP WITH INTEGRATED REMANENT MEMORY, AND METHOD OF FORMATION |
US20070298571A1 (en) * | 2003-06-20 | 2007-12-27 | Weon-Ho Park | Single chip data processing device with embedded nonvolatile memory and method thereof |
US7323740B2 (en) | 2003-06-20 | 2008-01-29 | Samsung Electronics Co., Ltd | Single chip data processing device with embedded nonvolatile memory and method thereof |
US7598139B2 (en) | 2003-06-20 | 2009-10-06 | Samsung Electronics Co., Ltd. | Single chip data processing device with embedded nonvolatile memory and method thereof |
Also Published As
Publication number | Publication date |
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EP0975020A1 (en) | 2000-01-26 |
US6251728B1 (en) | 2001-06-26 |
EP2034518A2 (en) | 2009-03-11 |
EP2034518A3 (en) | 2009-06-03 |
US6420769B2 (en) | 2002-07-16 |
EP0975020B1 (en) | 2009-02-11 |
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