US20010030352A1 - Method for increasing the capacitance in a storage trench and trench capacitor having increased capacitance - Google Patents
Method for increasing the capacitance in a storage trench and trench capacitor having increased capacitance Download PDFInfo
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- US20010030352A1 US20010030352A1 US09/796,213 US79621301A US2001030352A1 US 20010030352 A1 US20010030352 A1 US 20010030352A1 US 79621301 A US79621301 A US 79621301A US 2001030352 A1 US2001030352 A1 US 2001030352A1
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 238000003860 storage Methods 0.000 title claims abstract description 38
- 239000003990 capacitor Substances 0.000 title claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 18
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 13
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 56
- 238000000151 deposition Methods 0.000 claims description 20
- 229910052719 titanium Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 229910008484 TiSi Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
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- 239000010936 titanium Substances 0.000 description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 11
- 229910052721 tungsten Inorganic materials 0.000 description 10
- 239000010937 tungsten Substances 0.000 description 10
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910001930 tungsten oxide Inorganic materials 0.000 description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 5
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 5
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- 230000003247 decreasing effect Effects 0.000 description 2
- HEHINIICWNIGNO-UHFFFAOYSA-N oxosilicon;titanium Chemical compound [Ti].[Si]=O HEHINIICWNIGNO-UHFFFAOYSA-N 0.000 description 2
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
Definitions
- the invention relates to a method for increasing a capacitance in a storage trench and to a trench capacitor having an increased capacitance.
- the invention can be used in memory circuits, such as, for example, dynamic random access memories (DRAM) and other semiconductor circuits.
- DRAM dynamic random access memories
- a storage of charge is based in a capacitor as a storage element, which is formed in a pot-shaped manner. This entails not only a reduction of the cell area but also, at the same time, a reduction of the probability of alpha particles striking the cell.
- a pot-shaped capacitor is formed in a trench and is also referred to as a trench capacitor.
- the store of the trench cell has a trench that must keep a specific quantity of charge stored for a specific period of time.
- a method for increasing a capacitance in a storage trench includes the steps of depositing a layer of silicon oxide in the storage trench; depositing a layer of silicon over the layer of silicon oxide by a deposition method suitable for sufficient coverage of walls of the storage trench; depositing a layer having an oxidizable metal over the layer of silicon; and oxidizing the layer of silicon and the layer having the oxidizable metal to form a layer having a metal oxide and an silicon oxide.
- the first layer of silicon oxide is deposited in the storage trench.
- the layer of silicon is deposited over the first layer of silicon oxide by a deposition method which yields a sufficient coverage of the side walls of the storage trench.
- the layer having an oxidizable metal is deposited over the layer of silicon.
- the layer of silicon and the layer of oxidizable metal are oxidized to form a layer having metal oxide and silicon oxide.
- the inner wall of the storage trench is covered with the first layer of silicon oxide.
- the first layer of silicon oxide is covered with the layer having a metal oxide.
- the layer having the metal oxide is covered with a second layer of silicon oxide.
- the remainder of the storage trench is filled with silicon.
- Chemical vapor deposition or atomic layer deposition may advantageously be used as the deposition method.
- the second layer of silicon oxide is deposited over the layer having metal oxide and silicon oxide.
- the layer of oxidizable metal has Ti, TiN, W, WN, Ta, TaN, Wsi, TiSi or TaSi.
- the oxidation is advantageously carried out in an oxygen-containing atmosphere. This achieves intensified oxidation of the respective metal.
- the storage trench has a width of less than 140 nm.
- the first layer of silicon oxide has a thickness of approximately 0.3 nm.
- the second layer of silicon oxide has a thickness of approximately 0.3 nm.
- first and the second layer of silicon oxide are deposited by a chemical vapor deposition process.
- the layer of silicon has a thickness of approximately 0.5 nm.
- the silicon used is particularly suitable for coverage of the side wall.
- the layer of oxidizable metal has a thickness of approximately 10 nm.
- the layer having the oxidizable metal is deposited by a chemical vapor deposition process.
- a trench capacitor having an increased capacitance.
- the trench capacitor contains a substrate having a storage trench formed therein and the storage trench is defined by side walls and a bottom.
- a first layer of silicon oxide covers the side walls and the bottom of the storage trench.
- a layer having a metal oxide covers the first layer of silicon oxide.
- a second layer of silicon oxide covers the layer having the metal oxide and silicon fills in a remainder of the storage trench.
- FIG. 1 is a diagrammatic, cross-sectional view of a trench capacitor prior to being coated according to the invention
- FIG. 2 is a cross-sectional view of the trench capacitor after being coating with a silicon oxide layer, a silicon layer and a metal layer;
- FIG. 3 is a cross-sectional view of the trench capacitor after oxidation of the silicon layer and of the metal layer;
- FIG. 4 is a cross-sectional view of the trench capacitor with an additional silicon oxide layer
- FIG. 5 is a cross-sectional view of the trench capacitor with a silicon filling
- FIG. 6 is a cross-sectional view of the trench capacitor after an etching-away process
- FIG. 7 is a flow chart showing individual process steps of the method according to the invention in a case where tungsten is used.
- FIG. 8 is a flow chart showing the individual process steps of the method according to the invention in the case where titanium is used.
- FIG. 1 there is shown in cross section a buried n-type zone 1 (buried n-type plate) surrounded by a substrate 2 .
- a storage trench 3 is situated in the substrate 2 and the buried n-type zone 1 .
- FIG. 2 shows the storage trench 3 in cross section. A surface of the substrate 2 and also an inner wall of the storage trench 3 are coated with a first layer of silicon oxide 4 .
- the silicon oxide 4 has a smaller layer thickness on the wall of the trench 3 than on a top side of the substrate 2 .
- the ratio of the layer thickness on the top side of the substrate 2 to the side walls of the trench 3 may be 2:1.
- the silicon oxide deposition on the top side of the substrate 2 is approximately 0.3 nm.
- the silicon oxide 4 is advantageously deposited in a furnace in which the prepared trench store is situated.
- the first layer of silicon oxide 4 is covered with a layer of silicon 5 in a further process step.
- the layer thickness is larger in the horizontal region than in the vertical region.
- the silicon layer 5 can best be achieved in a furnace at 550 degrees Celsius by a low pressure chemical vapor deposition (LPCVD) process.
- ALD atomic layer deposition
- a layer 6 having an oxidizable metal is deposited above the layer of silicon 5 .
- the metal of the layer 6 may optionally have Ti, TiN, W, WN, Ta, TaN, Wsi, TiSi or TaSi.
- the layer 6 covers the silicon layer 5 both in the horizontal region and in the vertical region. In this case, too, the layer thickness of the metal layer 6 is greater in the horizontal region than in the vertical region. In the horizontal region, the layer thickness of the metal layer 6 is approximately 10 nm.
- the layer 6 having the metal is advantageously deposited by a chemical vapor deposition (CVD) process.
- the layer of silicon 5 serves as a wetting layer for the metal layer 6 . This enables or supports the subsequent deposition of the metal and ensures sufficient adhesion of the metal on the side walls.
- the silicon layer 5 additionally increases the capacitance of the dielectric layer through oxidation of the metal layer 6 in the trench capacitor.
- titanium and tungsten are used by way of example for the oxidizable metal layer 6 .
- the trench capacitor After oxidation of the silicon layer 5 and of the titanium or tungsten layer 6 , the trench capacitor has a layer structure as shown in FIG. 3.
- the titanium oxide/titanium silicon oxide layer or tungsten oxide/tungsten silicon oxide layer 7 is produced from the two layers of silicon 5 and titanium or tungsten 6 , respectively. Whether titanium oxide or titanium silicon oxide or both are produced in the layer 7 depends on the process control. However, a process control in which titanium oxide is produced is preferred, since the latter has a higher dielectric constant than titanium silicon oxide. The production of silicon oxide should be avoided by a suitable process control.
- tungsten oxide or tungsten silicon oxide.
- tungsten oxide is preferred since tungsten oxide has a higher dielectric constant than tungsten silicon oxide. This makes it possible to increase the storage capacitance of the trench capacitor.
- the resulting layer 7 grows, as a result of the additionally incorporated oxygen, to a layer thickness of approximately 15 nm in the horizontal region.
- a layer thickness of the layer 7 of approximately 10 to 20 nm can be assumed in the vertical region. In this case, the aim is to allow the layer 7 to become as thick as possible in the vertical region of the trench 3 .
- a surface of the titanium oxide/titanium silicon oxide layer or tungsten oxide/tungsten silicon oxide layer 7 is covered by a second layer of silicon oxide or silicon nitride 8 .
- the second layer of silicon oxide or silicon nitride 8 is thinner in the vertical region than in the horizontal region.
- the horizontal layer thickness of the second silicon oxide layer 8 is approximately 0.3 nm.
- the storage trench 3 is subsequently filled with silicon 9 in a further process step.
- the entire layer structure is removed again until a structure as shown in FIG. 6 is produced. This can be effected by dry chemical etching and subsequent wet cleaning. The material removal process is stopped below the upper edge of the buried plate region.
- FIG. 7 illustrates the fabrication method in the form of a structogram.
- step 100 wet cleaning of the trench 3 is carried out, step 110 .
- silicon oxide 4 is deposited with a layer thickness of approximately 0.3 nm (as shown in FIG. 2).
- the silicon oxide 4 used is also referred to as a furnace silicon oxide, step 120 .
- a furnace silicon 5 is deposited, which has the property of covering the side walls of the trench 3 well.
- tungsten 6 (layer thickness 10 nm) is deposited by a chemical vapor deposition process, step 140 .
- step 150 the silicon layer 5 and the tungsten layer 6 are oxidized to produce tungsten oxide 7 .
- the second silicon oxide layer or silicon nitride 8 is deposited in a furnace, step 160 .
- FIG. 8 shows a structogram to specify the method for increasing the capacitance in the storage trench using titanium. As described above, first the etching of the trench 3 and the buried plate process are carried out, step 200 .
- furnace silicon is deposited in a furnace at 550 degrees Celsius by a low pressure chemical vapor deposition process.
- titanium 6 layer thickness 10 nm
- step 250 the silicon layer 5 and the titanium layer 6 are oxidized to form the titanium oxide layer 7 .
- thw second furnace silicon oxide layer or silicon nitride 8 is deposited above that, step 260 .
- the buried plate process serves for insulating the trench capacitor from a transistor that is necessary for the DRAM memory module.
- the silicon layer 5 supports the nucleation and also the adhesion of the desired metal layer (titanium or tungsten) and can be oxidized in conjunction with the subsequently deposited metal layer 6 .
- the desired metal layer titanium or tungsten
- the layer thicknesses specified above merely represent guide values. In the case of further reduction of the trench width, the individual layer thicknesses should be adapted accordingly.
Abstract
In a method for forming a trench capacitor a first layer of silicon oxide is deposited in a storage trench and a layer of silicon is deposited over the first layer by a chemical vapor deposition process. A layer of an oxidizable metal is deposited over the layer of silicon. The layer of silicon and the layer of the oxidizable metal are subsequently oxidized to form a layer of silicon oxide and metal oxide.
Description
- 1.
- Field of the Invention
- The invention relates to a method for increasing a capacitance in a storage trench and to a trench capacitor having an increased capacitance.
- The invention can be used in memory circuits, such as, for example, dynamic random access memories (DRAM) and other semiconductor circuits.
- In trench DRAM modules, a storage of charge is based in a capacitor as a storage element, which is formed in a pot-shaped manner. This entails not only a reduction of the cell area but also, at the same time, a reduction of the probability of alpha particles striking the cell. Such a pot-shaped capacitor is formed in a trench and is also referred to as a trench capacitor. The store of the trench cell has a trench that must keep a specific quantity of charge stored for a specific period of time.
- In order to maintain and increase international competitiveness, it is necessary to continually reduce the costs that have to be expended to realize a specific electronic function, in order to increase productivity. The guarantee for increasing productivity in recent years has been and still is CMOS technology or DRAM technology. Trench DRAM technology owes its outstanding position principally to the small space requirement of the trench capacitors themselves and also to the possibility of disposing the trench capacitors in an integrated circuit with an extremely high packing density.
- The continually progressing miniaturization of the structures is accompanied by a decrease in the diameter of the trench and hence its surface area, with the result that less charge can be stored in the case of conventional technology.
- The prior art disclosed in U.S. Pat. No. 5,876,788 teaches a method for fabricating a dielectric for the DRAM cells. In this case, Si3N4 is used, on account of its relatively high dielectric constant, as a dielectric for increasing the storage capacitance. The use of this dielectric causes a number of problems principally in the case of decreasing lateral dimensions. In order to avoid the loss of charge associated with a decreasing diameter in DRAM cells, it has been proposed to etch the trench more deeply or to reduce the thickness of the silicon nitride layer. However, etching a deeper trench would disadvantageously increase the process time and the costs for fabrication. Reducing the layer thickness of the silicon nitride film can bring about an increase in the loss due to the tunnel effect.
- It is accordingly an object of the invention to provide a method for increasing the capacitance in a storage trench and a trench capacitor having an increased capacitance which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which, despite an increased packing density, sufficient charge can be stored so that the functionality of a memory cell continues to be ensured.
- With the foregoing and other objects in view there is provided, in accordance with the invention, a method for increasing a capacitance in a storage trench. The method includes the steps of depositing a layer of silicon oxide in the storage trench; depositing a layer of silicon over the layer of silicon oxide by a deposition method suitable for sufficient coverage of walls of the storage trench; depositing a layer having an oxidizable metal over the layer of silicon; and oxidizing the layer of silicon and the layer having the oxidizable metal to form a layer having a metal oxide and an silicon oxide.
- In the method for increasing the capacitance in the storage trench, the first layer of silicon oxide is deposited in the storage trench. The layer of silicon is deposited over the first layer of silicon oxide by a deposition method which yields a sufficient coverage of the side walls of the storage trench. The layer having an oxidizable metal is deposited over the layer of silicon. The layer of silicon and the layer of oxidizable metal are oxidized to form a layer having metal oxide and silicon oxide.
- In the trench capacitor having the increased capacitance, the inner wall of the storage trench is covered with the first layer of silicon oxide. The first layer of silicon oxide is covered with the layer having a metal oxide. The layer having the metal oxide is covered with a second layer of silicon oxide. The remainder of the storage trench is filled with silicon.
- Chemical vapor deposition or atomic layer deposition may advantageously be used as the deposition method.
- In the method according to the invention, it is advantageous if the second layer of silicon oxide is deposited over the layer having metal oxide and silicon oxide.
- It is also advantageous if the layer of oxidizable metal has Ti, TiN, W, WN, Ta, TaN, Wsi, TiSi or TaSi.
- The oxidation is advantageously carried out in an oxygen-containing atmosphere. This achieves intensified oxidation of the respective metal.
- Furthermore, it is advantageous to fill the storage trench with silicon.
- For the method according to the invention, it is advantageous if the storage trench has a width of less than 140 nm.
- In the method according to the invention, it is particularly preferred if the first layer of silicon oxide has a thickness of approximately 0.3 nm.
- In the method according to the invention, it is likewise particularly preferred if the second layer of silicon oxide has a thickness of approximately 0.3 nm.
- Furthermore, it is preferred if the first and the second layer of silicon oxide are deposited by a chemical vapor deposition process.
- In the method according to the invention, it is particularly preferred if the layer of silicon has a thickness of approximately 0.5 nm.
- In the method according to the invention, it is particularly preferred if the silicon used is particularly suitable for coverage of the side wall.
- It is advantageous for the method according to the invention that the layer of oxidizable metal has a thickness of approximately 10 nm.
- Furthermore, it is advantageous for the method according to the invention if the layer having the oxidizable metal is deposited by a chemical vapor deposition process.
- With the foregoing and other objects in view there is further provided, in accordance with the invention, a trench capacitor having an increased capacitance. The trench capacitor contains a substrate having a storage trench formed therein and the storage trench is defined by side walls and a bottom. A first layer of silicon oxide covers the side walls and the bottom of the storage trench. A layer having a metal oxide covers the first layer of silicon oxide. A second layer of silicon oxide covers the layer having the metal oxide and silicon fills in a remainder of the storage trench.
- Other features which are considered as characteristic for the invention are set forth in the appended claims.
- Although the invention is illustrated and described herein as embodied in a method for increasing the capacitance in a storage trench and a trench capacitor having an increased capacitance, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
- The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
- FIG. 1 is a diagrammatic, cross-sectional view of a trench capacitor prior to being coated according to the invention;
- FIG. 2 is a cross-sectional view of the trench capacitor after being coating with a silicon oxide layer, a silicon layer and a metal layer;
- FIG. 3 is a cross-sectional view of the trench capacitor after oxidation of the silicon layer and of the metal layer;
- FIG. 4 is a cross-sectional view of the trench capacitor with an additional silicon oxide layer;
- FIG. 5 is a cross-sectional view of the trench capacitor with a silicon filling;
- FIG. 6 is a cross-sectional view of the trench capacitor after an etching-away process;
- FIG. 7 is a flow chart showing individual process steps of the method according to the invention in a case where tungsten is used; and
- FIG. 8 is a flow chart showing the individual process steps of the method according to the invention in the case where titanium is used.
- In all the figures of the drawing, sub-features and integral parts that correspond to one another bear the same reference symbol in each case. Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is shown in cross section a buried n-type zone1 (buried n-type plate) surrounded by a
substrate 2. Astorage trench 3 is situated in thesubstrate 2 and the buried n-type zone 1. - FIG. 2 shows the
storage trench 3 in cross section. A surface of thesubstrate 2 and also an inner wall of thestorage trench 3 are coated with a first layer ofsilicon oxide 4. - The
silicon oxide 4 has a smaller layer thickness on the wall of thetrench 3 than on a top side of thesubstrate 2. The ratio of the layer thickness on the top side of thesubstrate 2 to the side walls of thetrench 3 may be 2:1. The silicon oxide deposition on the top side of thesubstrate 2 is approximately 0.3 nm. Thesilicon oxide 4 is advantageously deposited in a furnace in which the prepared trench store is situated. - The first layer of
silicon oxide 4 is covered with a layer ofsilicon 5 in a further process step. In the case of the layer ofsilicon 5, too, the layer thickness is larger in the horizontal region than in the vertical region. Thesilicon layer 5 can best be achieved in a furnace at 550 degrees Celsius by a low pressure chemical vapor deposition (LPCVD) process. - For depositing the layer of
silicon 5, a so-called atomic layer deposition (ALD) method can also be used instead of the CVD method. This involves a deposition method for fabricating an extremely thin silicon layer, preferably having a thickness of just a few atomic layers. In the ALD method, unlike in the CVD method, use is made essentially of the chemical affinity of the surface for the individual molecules or radicals. These are added from a vapor phase to a surface to be coated, until all free valences are saturated. As a result, the deposition is self-limiting and closed. - A
layer 6 having an oxidizable metal is deposited above the layer ofsilicon 5. The metal of thelayer 6 may optionally have Ti, TiN, W, WN, Ta, TaN, Wsi, TiSi or TaSi. Thelayer 6 covers thesilicon layer 5 both in the horizontal region and in the vertical region. In this case, too, the layer thickness of themetal layer 6 is greater in the horizontal region than in the vertical region. In the horizontal region, the layer thickness of themetal layer 6 is approximately 10 nm. Thelayer 6 having the metal is advantageously deposited by a chemical vapor deposition (CVD) process. - The layer of
silicon 5 serves as a wetting layer for themetal layer 6. This enables or supports the subsequent deposition of the metal and ensures sufficient adhesion of the metal on the side walls. Thesilicon layer 5 additionally increases the capacitance of the dielectric layer through oxidation of themetal layer 6 in the trench capacitor. - In the text below, titanium and tungsten are used by way of example for the
oxidizable metal layer 6. - After oxidation of the
silicon layer 5 and of the titanium ortungsten layer 6, the trench capacitor has a layer structure as shown in FIG. 3. The titanium oxide/titanium silicon oxide layer or tungsten oxide/tungstensilicon oxide layer 7 is produced from the two layers ofsilicon 5 and titanium ortungsten 6, respectively. Whether titanium oxide or titanium silicon oxide or both are produced in thelayer 7 depends on the process control. However, a process control in which titanium oxide is produced is preferred, since the latter has a higher dielectric constant than titanium silicon oxide. The production of silicon oxide should be avoided by a suitable process control. - The same applies to the production of tungsten oxide or tungsten silicon oxide. In this case, too, tungsten oxide is preferred since tungsten oxide has a higher dielectric constant than tungsten silicon oxide. This makes it possible to increase the storage capacitance of the trench capacitor. During the oxidation of the
silicon layer 5 and of the titanium ortungsten layer 6, the resultinglayer 7 grows, as a result of the additionally incorporated oxygen, to a layer thickness of approximately 15 nm in the horizontal region. A layer thickness of thelayer 7 of approximately 10 to 20 nm can be assumed in the vertical region. In this case, the aim is to allow thelayer 7 to become as thick as possible in the vertical region of thetrench 3. - As shown in FIG. 4, a surface of the titanium oxide/titanium silicon oxide layer or tungsten oxide/tungsten
silicon oxide layer 7 is covered by a second layer of silicon oxide orsilicon nitride 8. The second layer of silicon oxide orsilicon nitride 8 is thinner in the vertical region than in the horizontal region. The horizontal layer thickness of the secondsilicon oxide layer 8 is approximately 0.3 nm. - As shown in FIG. 5, the
storage trench 3 is subsequently filled withsilicon 9 in a further process step. - Finally, in further process steps, the entire layer structure is removed again until a structure as shown in FIG. 6 is produced. This can be effected by dry chemical etching and subsequent wet cleaning. The material removal process is stopped below the upper edge of the buried plate region.
- FIG. 7 illustrates the fabrication method in the form of a structogram. After the etching of the
trench 3 and the buried plate process, step 100, wet cleaning of thetrench 3 is carried out, step 110. Afterward,silicon oxide 4 is deposited with a layer thickness of approximately 0.3 nm (as shown in FIG. 2). Thesilicon oxide 4 used is also referred to as a furnace silicon oxide,step 120. In afurther process step 130, afurnace silicon 5 is deposited, which has the property of covering the side walls of thetrench 3 well. Afterward, tungsten 6 (layer thickness 10 nm) is deposited by a chemical vapor deposition process,step 140. In thenext process step 150, thesilicon layer 5 and thetungsten layer 6 are oxidized to producetungsten oxide 7. Finally, the second silicon oxide layer orsilicon nitride 8 is deposited in a furnace,step 160. - FIG. 8 shows a structogram to specify the method for increasing the capacitance in the storage trench using titanium. As described above, first the etching of the
trench 3 and the buried plate process are carried out,step 200. - Afterward, the wet cleaning of the trench is carried out in
step 210 and, in afurther step 220, the deposition of furnace silicon oxide is carried out. In afurther process step 230, furnace silicon is deposited in a furnace at 550 degrees Celsius by a low pressure chemical vapor deposition process. Afterward, titanium 6 (layer thickness 10 nm) is deposited by a chemical vapor deposition process,step 240. In thenext process step 250, thesilicon layer 5 and thetitanium layer 6 are oxidized to form thetitanium oxide layer 7. Finally, thw second furnace silicon oxide layer orsilicon nitride 8 is deposited above that,step 260. - The buried plate process serves for insulating the trench capacitor from a transistor that is necessary for the DRAM memory module.
- The
silicon layer 5 supports the nucleation and also the adhesion of the desired metal layer (titanium or tungsten) and can be oxidized in conjunction with the subsequently depositedmetal layer 6. - The layer thicknesses specified above merely represent guide values. In the case of further reduction of the trench width, the individual layer thicknesses should be adapted accordingly.
Claims (16)
1. A method for increasing a capacitance in a storage trench, which comprises the steps of:
depositing a layer of silicon oxide in the storage trench;
depositing a layer of silicon over the layer of silicon oxide by a deposition method suitable for sufficient coverage of walls of the storage trench;
depositing a layer having an oxidizable metal over the layer of silicon; and
oxidizing the layer of silicon and the layer having the oxidizable metal to form a layer having a metal oxide and an silicon oxide.
2. The method according to , which comprises using one of a chemical vapor deposition process and an atomic layer deposition process as the deposition method.
claim 1
3. The method according to , which comprises depositing a further layer formed of a material selected from the group consisting of silicon oxide and silicon nitride over the layer having the metal oxide and the silicon oxide.
claim 2
4. The method according to , which comprises using a metal selected from the group consisting of Ti, TiN, W, WN, Ta, TaN, Wsi, TiSi and TaSi as the oxidizable metal of the layer having the oxidizable metal.
claim 1
5. The method according to , which comprises carrying out the oxidizing step in an oxygen-containing atmosphere.
claim 1
6. The method according to , which comprises filling the storage trench with silicon.
claim 1
7. The method according to , which comprises forming the storage trench to have a width of less than 140 nm.
claim 1
8. The method according to , which comprises forming the layer of silicon oxide to have a thickness of approximately 0.3 nm.
claim 1
9. The method according to , which comprise which comprises forming the further layer to have a thickness of approximately 0.3 nm.
claim 3
10. The method according to , which comprises depositing the layer of silicon oxide and the further layer by a chemical vapor deposition process.
claim 3
11. The method according to , which comprises forming the layer of silicon to have a thickness of approximately 0.5 nm.
claim 1
12. The method according to , which comprises using silicon in the layer of silicon which is particularly suitable for covering side walls of the storage trench.
claim 1
13. The method according to , which comprises forming the layer having the oxidizable metal to a thickness of approximately 10 nm.
claim 1
14. The method according to , which comprises depositing the layer having the oxidizable metal by a chemical vapor deposition process.
claim 1
15. A trench capacitor having an increased capacitance, comprising:
a substrate having a storage trench formed therein and said storage trench defined by side walls and a bottom;
a first layer of silicon oxide covering said side walls and said bottom of said storage trench;
a layer having a metal oxide covering said first layer of silicon oxide;
a second layer of silicon oxide covering said layer having said metal oxide; and
silicon filling in a remainder of the storage trench.
16. The trench capacitor having the increased capacitance according to , wherein said metal oxide is selected from the group consisting of Ti, TiN, W, WN, Ta, TaN, Wsi, TiSi and TaSi.
claim 15
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DE10010821A DE10010821A1 (en) | 2000-02-29 | 2000-02-29 | Increasing capacity in a storage trench comprises depositing a first silicon oxide layer in the trench, depositing a silicon layer over the first layer to sufficiently |
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US6979855B2 (en) | 2001-12-20 | 2005-12-27 | Micron Technology, Inc. | High-quality praseodymium gate dielectrics |
US7026694B2 (en) | 2002-08-15 | 2006-04-11 | Micron Technology, Inc. | Lanthanide doped TiOx dielectric films by plasma oxidation |
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US7709402B2 (en) | 2006-02-16 | 2010-05-04 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride films |
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US7728626B2 (en) | 2002-07-08 | 2010-06-01 | Micron Technology, Inc. | Memory utilizing oxide nanolaminates |
US7727905B2 (en) | 2004-08-02 | 2010-06-01 | Micron Technology, Inc. | Zirconium-doped tantalum oxide films |
US7863667B2 (en) | 2003-04-22 | 2011-01-04 | Micron Technology, Inc. | Zirconium titanium oxide films |
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US8093638B2 (en) | 2002-06-05 | 2012-01-10 | Micron Technology, Inc. | Systems with a gate dielectric having multiple lanthanide oxide layers |
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Publication number | Priority date | Publication date | Assignee | Title |
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Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4557036A (en) * | 1982-03-31 | 1985-12-10 | Nippon Telegraph & Telephone Public Corp. | Semiconductor device and process for manufacturing the same |
US4432035A (en) * | 1982-06-11 | 1984-02-14 | International Business Machines Corp. | Method of making high dielectric constant insulators and capacitors using same |
US4453199A (en) * | 1983-06-17 | 1984-06-05 | Avx Corporation | Low cost thin film capacitor |
EP0169938B1 (en) | 1983-12-15 | 1989-03-29 | Kabushiki Kaisha Toshiba | Semiconductor memory device having trenched capacitor |
US4918502A (en) | 1986-11-28 | 1990-04-17 | Hitachi, Ltd. | Semiconductor memory having trench capacitor formed with sheath electrode |
US5276343A (en) | 1990-04-21 | 1994-01-04 | Kabushiki Kaisha Toshiba | Semiconductor memory device having a bit line constituted by a semiconductor layer |
KR930012120B1 (en) * | 1991-07-03 | 1993-12-24 | 삼성전자 주식회사 | Semicondcutor device and fabricating method thereof |
JPH0685187A (en) | 1992-09-07 | 1994-03-25 | Nec Corp | Semiconductor storage device |
KR960005681B1 (en) | 1992-11-07 | 1996-04-30 | 금성일렉트론주식회사 | Method for manufacturing a capacitor of semiconductor memory device |
JP3128364B2 (en) * | 1992-11-13 | 2001-01-29 | 新日本製鐵株式会社 | Semiconductor device and manufacturing method thereof |
TW248612B (en) * | 1993-03-31 | 1995-06-01 | Siemens Ag | |
US5876788A (en) | 1997-01-16 | 1999-03-02 | International Business Machines Corporation | High dielectric TiO2 -SiN composite films for memory applications |
US5936831A (en) * | 1997-03-06 | 1999-08-10 | Lucent Technologies Inc. | Thin film tantalum oxide capacitors and resulting product |
US6153491A (en) | 1997-05-29 | 2000-11-28 | International Business Machines Corporation | Overhanging separator for self-defining discontinuous film |
JPH10335652A (en) * | 1997-05-30 | 1998-12-18 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
JP3137044B2 (en) * | 1997-08-20 | 2001-02-19 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US6020609A (en) | 1997-10-31 | 2000-02-01 | Texas Instruments - Acer Incorporated | DRAM cell with a rugged stacked trench (RST) capacitor |
JP3421230B2 (en) | 1997-11-04 | 2003-06-30 | 株式会社日立製作所 | Semiconductor storage device and method of manufacturing the same |
US6191443B1 (en) | 1998-02-28 | 2001-02-20 | Micron Technology, Inc. | Capacitors, methods of forming capacitors, and DRAM memory cells |
US6177699B1 (en) | 1998-03-19 | 2001-01-23 | Lsi Logic Corporation | DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation |
US6261895B1 (en) | 1999-01-04 | 2001-07-17 | International Business Machines Corporation | Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor |
US6323078B1 (en) | 1999-10-14 | 2001-11-27 | Agere Systems Guardian Corp. | Method of forming metal oxide metal capacitors using multi-step rapid thermal process and a device formed thereby |
US6203613B1 (en) | 1999-10-19 | 2001-03-20 | International Business Machines Corporation | Atomic layer deposition with nitrate containing precursors |
US6373087B1 (en) | 2000-08-31 | 2002-04-16 | Agere Systems Guardian Corp. | Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses |
US20020119622A1 (en) * | 2001-02-27 | 2002-08-29 | Steigerwald Michael L. | Capacitor having a blended interface and a method of manufacture thereof |
-
2000
- 2000-02-29 DE DE10010821A patent/DE10010821A1/en not_active Withdrawn
-
2001
- 2001-01-24 EP EP01101486A patent/EP1130640A3/en not_active Ceased
- 2001-02-27 TW TW090104539A patent/TW492161B/en not_active IP Right Cessation
- 2001-02-28 US US09/796,213 patent/US20010030352A1/en not_active Abandoned
-
2002
- 2002-11-18 US US10/298,394 patent/US6699747B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
EP1130640A3 (en) | 2003-08-20 |
US6699747B2 (en) | 2004-03-02 |
EP1130640A2 (en) | 2001-09-05 |
DE10010821A1 (en) | 2001-09-13 |
US20030073283A1 (en) | 2003-04-17 |
TW492161B (en) | 2002-06-21 |
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