US20010031510A1 - Liquid crystal display and method of manufacturing the same - Google Patents

Liquid crystal display and method of manufacturing the same Download PDF

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US20010031510A1
US20010031510A1 US09/880,829 US88082901A US2001031510A1 US 20010031510 A1 US20010031510 A1 US 20010031510A1 US 88082901 A US88082901 A US 88082901A US 2001031510 A1 US2001031510 A1 US 2001031510A1
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Prior art keywords
layer
semiconductor device
etching
pad
etching rate
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US09/880,829
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US6344377B2 (en
Inventor
Byung Ahn
Hyung Seo
Hoe Soh
Chang Kim
Jae Choi
Duk Yun
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LG Display Co Ltd
Original Assignee
Ahn Byung Chul
Seo Hyung Sik
Soh Hoe Sup
Kim Chang Dong
Choi Jae Beom
Yun Duk Chul
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Priority claimed from US08/993,195 external-priority patent/US6288414B1/en
Application filed by Ahn Byung Chul, Seo Hyung Sik, Soh Hoe Sup, Kim Chang Dong, Choi Jae Beom, Yun Duk Chul filed Critical Ahn Byung Chul
Priority to US09/880,829 priority Critical patent/US6344377B2/en
Publication of US20010031510A1 publication Critical patent/US20010031510A1/en
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Assigned to LG DISPLAY CO., LTD. reassignment LG DISPLAY CO., LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: LG.PHILIPS LCD CO., LTD.
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Definitions

  • the present invention relates to a method for manufacturing a pad terminal for inputting or outputting electrical signals. More particularly, the present invention relates to a structure of the pad terminal in an electrical circuit board or a liquid crystal display device, and a method of manufacturing of the pad terminal.
  • an LCD display comprising thin film transistors (TFT's) or other electrical elements has pad terminals similar to ordinary electric circuit boards.
  • the LCD comprises a color filter panel for representing the color of a picture, and an active panel driving a pixel array by applying a data signal corresponding to the picture. These two panels are joined to each other with a narrow gap in between, and a liquid crystal material is injected into the gap.
  • driving signals are applied to the pad terminals of the active panel, the TFT's of the active panel drive the liquid crystal, thus displaying an image.
  • the color filter panel comprises a red color filter, a green color filter, and a blue color filter which are arrayed in sequence.
  • a black matrix is located between the color filters in a mesh pattern.
  • a common electrode is formed on the black matrix.
  • the active panel comprises pixel electrodes at the pixels arrayed on the transparent substrate in a matrix pattern.
  • a scan line is formed along the horizontal direction of the pixel array, and a data line is formed along the vertical direction of the pixel array.
  • a thin film transistor is formed for driving the pixel electrode.
  • the gate electrode is connected to the scan line (sometimes referred to as a ‘gate line’), and the source electrode is connected to the data line (sometimes referred to as a ‘source line’).
  • a pad terminal is formed at the end portion of each line.
  • the scan signal and the data signal are applied to the active panel through the pad terminals.
  • the scan signal is used for selecting the horizontal scan line and has a frequency from 30 Hz to 60 Hz.
  • the data signal normally represents an image. By selecting one scan line using the scan signal, the data signal of the scan line can be displayed an the LCD panel.
  • the signal applied to the pad terminal is an electrical signal. If there are particles or contaminants between the pad terminal and the output terminal of the outer device, or if the electrical contact between them is poor, then the quality of the image on the LCD screen may degrade. Therefore, the process of forming a pad terminal is very important for maintaining the quality of the image.
  • the conventional method for manufacturing the pad terminal and the structure of the LCD will now be described.
  • FIG. 1 shows a plan view of the conventional structure of an LCD.
  • FIGS. 2 a - 2 f are cross-sectional views showing the conventional process for manufacturing the TFT, the gate line, and the gate pad of an LCD along the line II-II.
  • a metal layer having low resistance such as aluminum or an aluminum alloy is deposited on a transparent substrate 11 .
  • a gate electrode 13 , a gate line 15 , a gate pad 17 , and a source pad 37 are formed by patterning the metal layer using a photolithographic method, as shown in FIG. 2 a .
  • the gate electrode 13 is formed at one corner of the pixel.
  • the gate line 15 connects the gate electrodes 13 arrayed in a row direction.
  • the gate pad 17 is formed later at an end portion of the gate line 15 .
  • the source pad 37 is formed at an end portion of a source line 35 .
  • a gate insulation layer 19 is formed by depositing an insulation material such as silicon nitride or silicon oxide on the substrate having the gate electrode 13 , the gate line 15 , and the gate pad 17 .
  • An intrinsic semiconductor material and a doped semiconductor material are sequentially deposited on the gate insulation layer 19 . By patterning them, a semiconductor layer 21 and a doped semiconductor layer 23 are formed, as shown in FIG. 2 b.
  • a first gate pad contact hole 61 and a first source pad contact hole 71 are formed by patterning the gate insulation layer 19 , as shown in FIG. 2 c .
  • the first gate pad contact hole 61 exposes the gate pad 17 by etching the gate insulation layer 19 covering the gate pad 17 .
  • the first source pad contact hole 71 exposes the source pad 37 by etching the gate insulation layer 19 covering the source pad 37 .
  • a metal such as chromium or a chromium alloy is deposited on the substrate having the doped semiconductor layer 23 .
  • a source electrode 33 , a drain electrode 43 , a source pad intermediate electrode 77 , and a gate pad intermediate electrode 67 are formed by patterning the metal layer, as shown in FIG. 2 d .
  • the source electrode 33 contacts one side of the semiconductor layer 21 and the doped semiconductor layer 23 , which acts as a source region.
  • the source line 35 connects to the source electrodes 33 arrayed in a column direction.
  • the drain electrode 43 is on the other side of the doped semiconductor layer 23 from the source electrode 33 , and connects to the other side of the semiconductor layer 21 and the doped semiconductor layer 23 , which acts as a drain region.
  • the source pad intermediate electrode 77 is formed at the end of the source line 35 and connects to the source pad 37 through the first source pad contact hole 71 .
  • the gate pad intermediate electrode 67 connects to the gate pad 17 through the first gate pad contact hole
  • a protection layer 39 is formed by depositing an insulation material such as silicon oxide or silicon nitride on the substrate having the source electrode 33 .
  • a drain contact hole 81 , a second gate pad contact hole 87 , and a second source pad contact hole 97 are formed by patterning the protection layer 39 , as shown in FIG. 2 e .
  • the drain contact hole 81 exposes the drain electrode 43 by removing a portion of the protection layer 39 covering the drain electrode 43 .
  • the second gate pad contact hole 87 exposes the gate pad intermediate electrode 67 by removing a portion of the protection layer 39 covering the gate intermediate electrode 67 .
  • the source pad contact hole exposes the source intermediate electrode 77 by removing a portion of the protection layer 39 covering the source intermediate electrode 77 .
  • a pixel electrode 53 , a gate pad terminal 65 , and a source pad terminal 75 are formed by depositing and patterning indium tin oxide (ITO) on the protection layer 39 , as shown in FIG. 2 f .
  • the pixel electrode 53 connects to the drain electrode 43 through the drain contact hole 81 .
  • the gate pad terminal 65 connects to the gate pad intermediate terminal 67 through the second gate pad contact hole 87 .
  • the source pad terminal 75 connects to the source pad intermediate electrode 77 through the second source pad contact hole 97 .
  • the gate pad 17 and the source pad 37 comprise aluminum
  • the gate and source pad intermediate electrodes 67 and 77 comprise chromium
  • the gate source pad terminals 65 and 75 comprise ITO.
  • ITO is deposited by a sputtering method on the intermediate electrodes 67 and 77 , it is sputtered in an oxygen atmosphere.
  • chromium oxide can form on the surface of the intermediate electrodes 67 and 77 .
  • the gate insulation layer or the protection layer comprising the silicon oxide or silicon nitride are formed on the pads or on the intermediate electrodes and patterned to form contact holes.
  • silicon oxide or silicon nitride is deposited on the surface of the metal layer, a thin metal oxide layer or a thin metal nitride layer can form, resulting in a contact resistance between chromium and ITO that is higher than desired.
  • the present invention is directed to a liquid crystal display and method of manufacturing the same that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
  • One object of the present invention is to keep contact resistance of a pad terminal surface of an active panel at a low level.
  • Another object of the present invention is to maintain the scan and data signals in their original state by keeping contact resistance of the pad terminal at a low level.
  • Another object of the present invention is to enhance the quality of a displayed image by maintaining the signals of the active panel in their original state.
  • a further object of the present invention is to provide a hillock-free gate structure.
  • a method for manufacturing a semiconductor device comprises the steps of forming a first layer of a first conductive material on a substrate; forming a second layer of a second conductive material on the first layer; etching the first and the second layer simultaneously to form a pad; forming an insulating layer on the pad and the substrate; and etching the insulating layer and the second layer simultaneously.
  • a method for manufacturing a semiconductor device comprises the steps of forming a first layer of a first conductive material on a substrate, the first layer having a first etching rate; forming a second layer of a second conductive material on the first layer, the second layer having a second etching rate, the second etching rate of the second layer being higher than the first etching rate of the first layer; forming a third layer between the first and second layers, the third layer including a combination of the first and second layers, the third layer having a third etching rate lower than the second etching rate of the second layer; etching the first and the second layer simultaneously to form a pad; forming an insulating layer having a fourth etching rate on the pad and the substrate, the fourth etching rate being higher than the first etching rate of the first layer; and etching the insulating layer and the second layer simultaneously using a single mask to expose a portion of the third layer.
  • a semiconductor device comprises a substrate; a first layer of a first conductive material on the substrate; a second layer of a second conductive material having a first hole on a portion of the first layer; a third layer of conductive material between the first and the second layers; an insulating layer having a second hole on the third layer; and a transparent conductive layer on the third layer through the first and second holes.
  • a semiconductor device comprises a substrate; a first layer of a first conductive material on the substrate, the first layer having a first etching rate; a second layer of a second conductive material having a first hole on a portion of the first layer, the second layer having a second etching rate higher than the first etching rate; a third layer including a combination of the first and second layers between the first and the second layers, the third layer having a third etching rate lower than the second etching rate; an insulating layer having a second hole on the third layer, the insulating layer having a fourth etching rate higher than the first etching rate; and a transparent conductive layer on the third layer through the first and second holes.
  • FIG. 1 shows a plan view of the conventional structure of a liquid crystal display device
  • FIGS. 2 a - 2 f are cross-sectional views showing the manufacturing process of a conventional active panel of an LCD
  • FIG. 3 shows a plan view of a structure of an LCD of the present invention
  • FIGS. 4 a - 4 f are cross-sectional views showing an example of a manufacturing process of an active panel of the present invention.
  • FIGS. 5 shows an analysis using Auger Electron Spectroscopy (AES) of the ohmic contact layer between ITO/AL layers of the present invention
  • FIG. 6 shows a plan view of a pad of the present invention.
  • FIGS. 8 a - 8 b show another example of a pad structure of the present invention.
  • the present invention therefore discloses a manufacturing method of an active panel where the pad terminal surface does not have a thin layer of particles which increase contact resistance.
  • the manufacturing method includes a step of forming a pad by depositing and patterning a first and a second metal layer on a substrate; forming a pad protection layer by depositing silicon oxide or silicon nitride on the pad; forming a pad contact hole by patterning the pad protection layer by using a dry etching method; removing by wet etching an exposed portion of the second metal layer through the pad contact hole; forming a pad terminal in contact with the pad through the pad contact hole by depositing and patterning an indium tin oxide layer on the pad protection layer.
  • the surface of the pad including the first metal does not have an oxide or a nitride layer. If a thin layer of oxide or nitride layer is formed on the second metal layer, then it is removed at the step of wet etchings the second metal layer. So, the contact between the ITO and the pad remains satisfactory after removing the photoresist pattern to expose the surface on the gate electrode.
  • FIG. 3 showing a plan view of an active panel of the present invention
  • FIGS. 4 a - 4 f showing cross-sectional views of the active panel along the line IV-IV in FIG. 3, this embodiment will now be described.
  • a first metal layer including aluminum is deposited on a transparent substrate 111 to form an aluminum layer.
  • the aluminum layer is patterned to form a low resistance gate electrode 113 a , a low resistance gate line 115 a , and a low resistance gate pad 117 a , as shown in FIG. 4 a.
  • a second metal layer including preferably molybdenum or chromium is deposited on the substrate 111 , the low resistance gate electrode 113 a , the low resistance gate line 115 a , and the low resistance gate pad 117 a .
  • the second metal layer is patterned to form a second-metal gate electrode 113 , a second-metal gate line 115 , and a second-metal gate pad 117 , as shown in FIG. 4 a .
  • the second-metal gate electrode 113 is formed at one corner of a pixel.
  • the second-metal gate line 115 connects the second-metal gate electrodes 113 arrayed in a row direction.
  • the second-metal gate pad 117 is located at the end portion of the second-metal gate line 115 .
  • the second-metal gate electrode 113 , the second-metal gate line 115 , and the second-metal gate pad 117 cover portions of the low resistance gate electrode 113 a , the low resistance gate line 115 a and the low resistance gate pad 117 a , respectively.
  • the covered portion of the aluminum metal layer is defined such that the hillock problem does not occur.
  • An insulation material such as silicon oxide or silicon nitride is deposited on the substrate 111 , the second-metal gate electrode 113 , the second-metal gate line 115 , and the second-metal gate pad 117 .
  • the layer including the insulation material becomes a gate insulation layer 119 .
  • An intrinsic semiconductor material and a doped semiconductor material are sequentially deposited thereon. The intrinsic semiconductor material and the doped semiconductor material are patterned to form a semiconductor layer 121 and a doped semiconductor layer 123 , respectively, as shown in FIG. 4 b.
  • a third metal layer including molybdenum or chromium is deposited on the substrate 111 , the semiconductor layer 121 and the doped semiconductor layer 123 .
  • the third metal layer is patterned to form a source electrode 133 , a source line 135 , a source pad 137 , and a drain electrode 143 .
  • the source electrode 133 is formed in contact with a source region of the TFT
  • the drain electrode 143 is formed in contact with a drain region of the TFT.
  • the source electrode 133 and the drain electrode 143 are separated by a gap in the doped semiconductor layer 123 .
  • the exposed part of the doped semiconductor layer 123 between the source electrode 133 and the drain electrode 143 is removed by etching, using the source electrode 133 and the drain electrode 143 as a mask so the doped semiconductor layer 123 is divided into two parts, as shown in FIG. 4 c .
  • the source line 135 connects the source electrodes 133 arrayed in a column direction.
  • the source pad 137 is located at an end portion of the source line 135 .
  • a protection layer 139 is formed by depositing an insulation material such as silicon nitride or silicon oxide on the substrate 111 , the source electrode 133 , the source line 135 , the source pad 137 , and drain electrode 143 .
  • the protection layer 139 is patterned to form a drain contact hole 181 , a gate pad contact hole 187 , and a source pad contact hole 197 , as shown in FIG. 4 d .
  • the drain contact hole 181 exposes the drain electrode 143 by etching the protection layer 139 covering the drain electrode 143 .
  • the gate pad contact hole 187 exposes the second-metal gate pad 117 by removing the protection layer 139 and the gate insulation layer 119 covering the second-metal gate pad 117 .
  • the source pad contact hole 197 exposes the source pad 137 by etching the protection layer 139 covering the source pad 137 .
  • the source pad contact hole 197 may also be formed by removing the protection layer 139 covering the source pad 137 . Then, the exposed part of the second-metal gate pad 117 is removed by an etching method using the gate pad contact hole 187 as a mask, as shown in FIG. 4 d.
  • An indium tin oxide layer is deposited on the protection layer 139 , and is patterned to form a pixel electrode 153 , a gate pad terminal 165 , and a source pad terminal 175 .
  • the pixel electrode 153 connects to the drain electrode 143 through the drain contact hole 181 .
  • the gate pad terminal 165 is connected to the low resistance gate pad 117 a through the gate pad contact hole 187 .
  • the source pad terminal 175 is connected to the source pad 137 through the source pad contact hole 197 , as shown in FIG. 4 e.
  • the low resistance gate pad 117 a includes a first metal layer including aluminum
  • the second-metal gate pad 117 includes a first metal layer including aluminum and a second metal layer including chromium or molybdenum.
  • the second metal layer may cover the first metal layer entirely. So, the hillock problem which occurs on an aluminum surface is prevented by the second metal layer.
  • a portion of the second-metal gate pad 117 exposed through the gate pad contact hole 187 is removed by a wet etching method.
  • the gate pad terminal 165 is formed by depositing an ITO layer over it, and patterning the ITO layer. Therefore, the exposed surface of the second-metal gate pad 117 is clear, and there are no contaminants such as molybdenum oxide, molybdenum nitride, chromium oxide, or chromium nitride between the second-metal gate pad 117 and the gate pad terminal 165 .
  • the embodiment describes another example of a pad structure of an LCD and the manufacturing method for the same.
  • the surface of a pad is a plane structure, as shown in FIG. 4 e .
  • This embodiment describes a pad structure where contact resistance between the pad and a pad terminal is reduced and the adhesion between them is enhanced.
  • an ITO/MoAlx/Al structure was used as the pixel electrode/intermetallic layer/gate, respectively.
  • the hillock-free structure of the present invention is discussed with reference to the ITO/MoAlx/Al structure, other suitable materials may be used according to the present invention as discussed below.
  • the semiconductor device in accordance with the present embodiment includes a semiconductor device having a substrate and a first layer of a first conductive material on the substrate.
  • the first layer preferably includes aluminum.
  • the first layer may also include Cu or Au.
  • a second layer of a second conductive material having a first hole is on a portion of the first layer.
  • the second layer preferably includes molybdenum or an alloy including Mo.
  • the second layer may also act as an etch stop layer.
  • the first and second layers have a step structure.
  • a spacing between an edge of the first layer to an edge of the second layer is preferably about 0.5 to 2 um.
  • the first layer is preferably made of a material exhibiting a tensile stress and the second layer is made of a material exhibiting a compressive stress.
  • a third layer of conductive material is between the first and the second layers.
  • the third layer preferably includes a combination of the first and the second layers of conductive material such as MoAlx.
  • the third layer has an etching rate lower than the etching rate of the second layer.
  • An insulating layer having a second hole is on the third layer.
  • the insulating layer preferably includes a first pad insulating layer and a passivation layer over the first pad insulating layer.
  • the insulating layer and the second layer preferably have etching rates higher than the first layer.
  • the insulating layer and the second layer may have substantially the same etching rate.
  • the insulating layer and the third layer includes multiple holes.
  • a transparent conductive layer is on the third layer through the first and second holes.
  • a low electrically resistive gate material such as Al and its alloy
  • TFT-LCD thin film transistor liquid crystal displays
  • Al is likely to form hillocks during a high temperature process such as PECVD or annealing process.
  • PECVD plasma chemical vapor deposition
  • annealing process a high temperature process
  • Many researches have been focused on preventing the Al hillocks, and some structures such as clad or Al/AlTa buffered structure, have been proposed as hillock-free gate structures.
  • the Al metal is covered by refractory metals such as Cr, Mo, Ta, and Ti
  • refractory metals such as Cr, Mo, Ta, and Ti
  • two separated photolithography and wet etching processes are required to complete the gate bus line.
  • the Al/AlTa buffered structure needs only one photolithography step for the gate bus line by etching the two metals simultaneously.
  • this structure has a contact problem at the pad region where the ITO/Al contact is formed because of Al oxidation during ITO deposition and annealing process.
  • the Al oxide layer causes the contact resistance to increase.
  • the present inventors have shown that Al oxide layer is formed after 300° C. annealing processes analyzed by Electron Spectroscopy for Chemical Analysis (ESCA).
  • a diffusion barrier metal can be inserted to prevent the Al oxidation.
  • the present inventors have investigated Mo/Al and AlTa/Al double layers for hillock-free Al gate metallization and ohmic contact in the pad region [ITO/(Cr, Mo, AlTa)/Al].
  • the double metals were deposited continuously without breaking the vacuum and patterned by wet etching with only one photolithography process. The internal stress of the double metal layers and the etched profile of the metals were changed to clarify the hillock prevention mechanism.
  • Al hillocks were found in the Cr/Al and the AlTa/Al double layers but not in the Mo/Al. This result can be explained by the stress balance between the upper refractory metals and the bottom Al. While the Al, AlTa and Cr layers have a tensile stress, the Mo layer has a compressive stress. Therefore, as the processing temperature increases, Al hillocks could be suppressed by stress compensation between Mo and Al layers.
  • the Mo layer at the pad region was not etched off during the dry etching process of a gate insulator. As a result, ITO/Mo/Al contact was successfully formed.
  • the inserted Mo layer prevented the Al oxidation during the ITO deposition and the annealing process by blocking the diffusing oxygen atoms into the Al surface.
  • the inserted Mo layer was etched off during the gate insulator dry etching process as shown in FIG. 7 a , for example. There was no contract problem because an MoAlx intermetallic compound was formed at the Al surface.
  • a 12.1′′ SVGA TFT-LCD was manufactured by a simple process.
  • the contact area can be enlarged.
  • the surface of the pad has a raised part and a depressed part.
  • the pad contact hole has many small holes, rather than a single hole, as shown in FIG. 6.
  • FIG. 6 shows a pad structure in which the pad has many small contact holes.
  • FIG. 7 a shows a cross-sectional view of a pad having one contact hole
  • FIG. 7 b shows the cross sectional view of a pad having several small contact holes.
  • an intermetallic layer 199 is formed between the low resistance gate pad 117 a and a second metal gate pad 117 .
  • the intermetallic layer 199 is preferably formed of MoAlx from the Al layer below the Mo layer. MoAlx is formed during the gate insulator dry etching process, for example, which also etches off the portion of the Mo layer 117 corresponding to the MoAlx layer.
  • the ITO layer which will become a pad terminal, is usually sputtered in an oxygen atmosphere.
  • a thin aluminum oxide layer will be formed on the exposed pad surface that includes aluminum.
  • Aluminum oxide has high resistance to electrical current. Therefore, the existence of the aluminum oxide layer hinders electrical contact.
  • the gate pad contact hole 187 includes many small holes and the second-metal gate pad 117 is patterned by an etching method using the small holes as a mask.
  • the gate pad terminal 165 is also in contact with side portions of the etched second-metal gate pad 117 which includes molybdenum or chromium. The contact area is enlarged because of the uneven surface shape, and contact resistance between the second-metal gate pad 117 and the gate pad terminal 165 is reduced.
  • the small holes may have any shape, as shown in FIGS. 8 a and 8 b .
  • the small holes may be formed over the entire pad part or some part of the pad.

Abstract

A semiconductor device includes a substrate and a first layer of a first conductive material on the substrate, the first layer having a first etching rate. A second layer of a second conductive material has a first hole on a portion of the first layer, the second layer having a second etching rate higher than the first etching rate. A third layer includes a combination of the first and second layers between the first and the second layers, the third layer having a third etching rate lower than the second etching rate. An insulating layer has a second hole on the third layer, the insulating layer having a fourth etching rate higher than the first etching rate. A transparent conductive layer is on the third layer through the first and second holes.

Description

  • This application is a continuation-in-part application of U.S. application Ser. No. ______ filed on Dec. 18, 1997, entitled “LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME” by Byung Chul AHN, which is hereby incorporated by reference.[0001]
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention relates to a method for manufacturing a pad terminal for inputting or outputting electrical signals. More particularly, the present invention relates to a structure of the pad terminal in an electrical circuit board or a liquid crystal display device, and a method of manufacturing of the pad terminal. [0003]
  • 2. Discussion of the Related Art [0004]
  • Generally, most electrical circuit boards have pad terminals for inputting or outputting electrical signals. These pad terminals are usually made simultaneously with the rest of the circuit board. Also, an LCD display comprising thin film transistors (TFT's) or other electrical elements has pad terminals similar to ordinary electric circuit boards. The LCD comprises a color filter panel for representing the color of a picture, and an active panel driving a pixel array by applying a data signal corresponding to the picture. These two panels are joined to each other with a narrow gap in between, and a liquid crystal material is injected into the gap. When driving signals are applied to the pad terminals of the active panel, the TFT's of the active panel drive the liquid crystal, thus displaying an image. [0005]
  • The color filter panel comprises a red color filter, a green color filter, and a blue color filter which are arrayed in sequence. A black matrix is located between the color filters in a mesh pattern. A common electrode is formed on the black matrix. The active panel comprises pixel electrodes at the pixels arrayed on the transparent substrate in a matrix pattern. A scan line is formed along the horizontal direction of the pixel array, and a data line is formed along the vertical direction of the pixel array. At one corner of the pixel, a thin film transistor is formed for driving the pixel electrode. The gate electrode is connected to the scan line (sometimes referred to as a ‘gate line’), and the source electrode is connected to the data line (sometimes referred to as a ‘source line’). A pad terminal is formed at the end portion of each line. [0006]
  • The scan signal and the data signal are applied to the active panel through the pad terminals. The scan signal is used for selecting the horizontal scan line and has a frequency from 30 Hz to 60 Hz. The data signal normally represents an image. By selecting one scan line using the scan signal, the data signal of the scan line can be displayed an the LCD panel. [0007]
  • The signal applied to the pad terminal is an electrical signal. If there are particles or contaminants between the pad terminal and the output terminal of the outer device, or if the electrical contact between them is poor, then the quality of the image on the LCD screen may degrade. Therefore, the process of forming a pad terminal is very important for maintaining the quality of the image. The conventional method for manufacturing the pad terminal and the structure of the LCD will now be described. [0008]
  • FIG. 1 shows a plan view of the conventional structure of an LCD. FIGS. 2[0009] a-2 f are cross-sectional views showing the conventional process for manufacturing the TFT, the gate line, and the gate pad of an LCD along the line II-II.
  • A metal layer having low resistance such as aluminum or an aluminum alloy is deposited on a [0010] transparent substrate 11. A gate electrode 13, a gate line 15, a gate pad 17, and a source pad 37 are formed by patterning the metal layer using a photolithographic method, as shown in FIG. 2a. The gate electrode 13 is formed at one corner of the pixel. The gate line 15 connects the gate electrodes 13 arrayed in a row direction. The gate pad 17 is formed later at an end portion of the gate line 15. The source pad 37 is formed at an end portion of a source line 35.
  • A [0011] gate insulation layer 19 is formed by depositing an insulation material such as silicon nitride or silicon oxide on the substrate having the gate electrode 13, the gate line 15, and the gate pad 17. An intrinsic semiconductor material and a doped semiconductor material are sequentially deposited on the gate insulation layer 19. By patterning them, a semiconductor layer 21 and a doped semiconductor layer 23 are formed, as shown in FIG. 2b.
  • A first gate [0012] pad contact hole 61 and a first source pad contact hole 71 are formed by patterning the gate insulation layer 19, as shown in FIG. 2c. The first gate pad contact hole 61 exposes the gate pad 17 by etching the gate insulation layer 19 covering the gate pad 17. The first source pad contact hole 71 exposes the source pad 37 by etching the gate insulation layer 19 covering the source pad 37.
  • A metal such as chromium or a chromium alloy is deposited on the substrate having the [0013] doped semiconductor layer 23. A source electrode 33, a drain electrode 43, a source pad intermediate electrode 77, and a gate pad intermediate electrode 67 are formed by patterning the metal layer, as shown in FIG. 2d. The source electrode 33 contacts one side of the semiconductor layer 21 and the doped semiconductor layer 23, which acts as a source region. The source line 35 connects to the source electrodes 33 arrayed in a column direction. The drain electrode 43 is on the other side of the doped semiconductor layer 23 from the source electrode 33, and connects to the other side of the semiconductor layer 21 and the doped semiconductor layer 23, which acts as a drain region. The source pad intermediate electrode 77 is formed at the end of the source line 35 and connects to the source pad 37 through the first source pad contact hole 71. The gate pad intermediate electrode 67 connects to the gate pad 17 through the first gate pad contact hole 61.
  • A [0014] protection layer 39 is formed by depositing an insulation material such as silicon oxide or silicon nitride on the substrate having the source electrode 33. A drain contact hole 81, a second gate pad contact hole 87, and a second source pad contact hole 97 are formed by patterning the protection layer 39, as shown in FIG. 2e. The drain contact hole 81 exposes the drain electrode 43 by removing a portion of the protection layer 39 covering the drain electrode 43. The second gate pad contact hole 87 exposes the gate pad intermediate electrode 67 by removing a portion of the protection layer 39 covering the gate intermediate electrode 67. The source pad contact hole exposes the source intermediate electrode 77 by removing a portion of the protection layer 39 covering the source intermediate electrode 77.
  • A [0015] pixel electrode 53, a gate pad terminal 65, and a source pad terminal 75 are formed by depositing and patterning indium tin oxide (ITO) on the protection layer 39, as shown in FIG. 2f. The pixel electrode 53 connects to the drain electrode 43 through the drain contact hole 81. The gate pad terminal 65 connects to the gate pad intermediate terminal 67 through the second gate pad contact hole 87. The source pad terminal 75 connects to the source pad intermediate electrode 77 through the second source pad contact hole 97.
  • According to the conventional method, the [0016] gate pad 17 and the source pad 37 comprise aluminum, the gate and source pad intermediate electrodes 67 and 77 comprise chromium, and the gate source pad terminals 65 and 75 comprise ITO. Generally, when ITO is deposited by a sputtering method on the intermediate electrodes 67 and 77, it is sputtered in an oxygen atmosphere. At that time, chromium oxide can form on the surface of the intermediate electrodes 67 and 77. Also, the gate insulation layer or the protection layer comprising the silicon oxide or silicon nitride are formed on the pads or on the intermediate electrodes and patterned to form contact holes. When silicon oxide or silicon nitride is deposited on the surface of the metal layer, a thin metal oxide layer or a thin metal nitride layer can form, resulting in a contact resistance between chromium and ITO that is higher than desired.
    • SUMMARY OF THE INVENTION
  • Accordingly, the present invention is directed to a liquid crystal display and method of manufacturing the same that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art. [0017]
  • One object of the present invention is to keep contact resistance of a pad terminal surface of an active panel at a low level. [0018]
  • Another object of the present invention is to maintain the scan and data signals in their original state by keeping contact resistance of the pad terminal at a low level. [0019]
  • Another object of the present invention is to enhance the quality of a displayed image by maintaining the signals of the active panel in their original state. [0020]
  • A further object of the present invention is to provide a hillock-free gate structure. [0021]
  • Additional features and advantages of the present invention will be set forth in the description which follows, and will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure and process particularly pointed out in the written description as well as in the appended claims. [0022]
  • To achieve these an other advantages, and in accordance with the purpose of the present invention, as embodied and broadly described, in a first aspect of the present invention there is provided a method for manufacturing a semiconductor device comprises the steps of forming a first layer of a first conductive material on a substrate; forming a second layer of a second conductive material on the first layer; etching the first and the second layer simultaneously to form a pad; forming an insulating layer on the pad and the substrate; and etching the insulating layer and the second layer simultaneously. [0023]
  • In another aspect of the present invention, a method for manufacturing a semiconductor device comprises the steps of forming a first layer of a first conductive material on a substrate, the first layer having a first etching rate; forming a second layer of a second conductive material on the first layer, the second layer having a second etching rate, the second etching rate of the second layer being higher than the first etching rate of the first layer; forming a third layer between the first and second layers, the third layer including a combination of the first and second layers, the third layer having a third etching rate lower than the second etching rate of the second layer; etching the first and the second layer simultaneously to form a pad; forming an insulating layer having a fourth etching rate on the pad and the substrate, the fourth etching rate being higher than the first etching rate of the first layer; and etching the insulating layer and the second layer simultaneously using a single mask to expose a portion of the third layer. [0024]
  • In another aspect of the present invention, a semiconductor device comprises a substrate; a first layer of a first conductive material on the substrate; a second layer of a second conductive material having a first hole on a portion of the first layer; a third layer of conductive material between the first and the second layers; an insulating layer having a second hole on the third layer; and a transparent conductive layer on the third layer through the first and second holes. [0025]
  • In a further aspect of the present invention, a semiconductor device comprises a substrate; a first layer of a first conductive material on the substrate, the first layer having a first etching rate; a second layer of a second conductive material having a first hole on a portion of the first layer, the second layer having a second etching rate higher than the first etching rate; a third layer including a combination of the first and second layers between the first and the second layers, the third layer having a third etching rate lower than the second etching rate; an insulating layer having a second hole on the third layer, the insulating layer having a fourth etching rate higher than the first etching rate; and a transparent conductive layer on the third layer through the first and second holes. [0026]
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.[0027]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention that together with the description serve to explain the principles of the invention. [0028]
  • In the drawings: [0029]
  • FIG. 1 shows a plan view of the conventional structure of a liquid crystal display device; [0030]
  • FIGS. 2[0031] a-2 f are cross-sectional views showing the manufacturing process of a conventional active panel of an LCD;
  • FIG. 3 shows a plan view of a structure of an LCD of the present invention; [0032]
  • FIGS. 4[0033] a-4 f are cross-sectional views showing an example of a manufacturing process of an active panel of the present invention;
  • FIGS. [0034] 5 shows an analysis using Auger Electron Spectroscopy (AES) of the ohmic contact layer between ITO/AL layers of the present invention;
  • FIG. 6 shows a plan view of a pad of the present invention. [0035]
  • FIGS. 7[0036] a-7 b are cross-sectional views showing a pad of the present invention; and
  • FIGS. 8[0037] a-8 b show another example of a pad structure of the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. [0038]
  • The present invention relates to a method for maintaining contact resistance of a pad and the structure of the pad. The present invention prevents contamination by foreign materials, such as an oxidation layer or a nitrification layer, of the pad surface during the manufacture of an LCD active panel. Thus, contact resistance does not increase due to the contaminating materials. Also, the pad surface may have a raised part and a depressed part, enlarging the total contact area of the pad. Therefore, contact resistance and adhesion between the pad and the pad terminal are improved. Thus, a high quality LCD panel can be manufactured. [0039]
  • The present invention therefore discloses a manufacturing method of an active panel where the pad terminal surface does not have a thin layer of particles which increase contact resistance. According to the present invention, the manufacturing method includes a step of forming a pad by depositing and patterning a first and a second metal layer on a substrate; forming a pad protection layer by depositing silicon oxide or silicon nitride on the pad; forming a pad contact hole by patterning the pad protection layer by using a dry etching method; removing by wet etching an exposed portion of the second metal layer through the pad contact hole; forming a pad terminal in contact with the pad through the pad contact hole by depositing and patterning an indium tin oxide layer on the pad protection layer. Therefore, the surface of the pad including the first metal does not have an oxide or a nitride layer. If a thin layer of oxide or nitride layer is formed on the second metal layer, then it is removed at the step of wet etchings the second metal layer. So, the contact between the ITO and the pad remains satisfactory after removing the photoresist pattern to expose the surface on the gate electrode. [0040]
  • Referring to FIG. 3 showing a plan view of an active panel of the present invention and FIGS. 4[0041] a-4 f showing cross-sectional views of the active panel along the line IV-IV in FIG. 3, this embodiment will now be described.
  • A first metal layer including aluminum is deposited on a [0042] transparent substrate 111 to form an aluminum layer. The aluminum layer is patterned to form a low resistance gate electrode 113 a, a low resistance gate line 115 a, and a low resistance gate pad 117 a, as shown in FIG. 4a.
  • A second metal layer including preferably molybdenum or chromium is deposited on the [0043] substrate 111, the low resistance gate electrode 113 a, the low resistance gate line 115 a, and the low resistance gate pad 117 a. The second metal layer is patterned to form a second-metal gate electrode 113, a second-metal gate line 115, and a second-metal gate pad 117, as shown in FIG. 4a. The second-metal gate electrode 113 is formed at one corner of a pixel. The second-metal gate line 115 connects the second-metal gate electrodes 113 arrayed in a row direction. The second-metal gate pad 117 is located at the end portion of the second-metal gate line 115. The second-metal gate electrode 113, the second-metal gate line 115, and the second-metal gate pad 117 cover portions of the low resistance gate electrode 113 a, the low resistance gate line 115 a and the low resistance gate pad 117 a, respectively. Here, the covered portion of the aluminum metal layer is defined such that the hillock problem does not occur.
  • An insulation material such as silicon oxide or silicon nitride is deposited on the [0044] substrate 111, the second-metal gate electrode 113, the second-metal gate line 115, and the second-metal gate pad 117. The layer including the insulation material becomes a gate insulation layer 119. An intrinsic semiconductor material and a doped semiconductor material are sequentially deposited thereon. The intrinsic semiconductor material and the doped semiconductor material are patterned to form a semiconductor layer 121 and a doped semiconductor layer 123, respectively, as shown in FIG. 4b.
  • A third metal layer including molybdenum or chromium is deposited on the [0045] substrate 111, the semiconductor layer 121 and the doped semiconductor layer 123. The third metal layer is patterned to form a source electrode 133, a source line 135, a source pad 137, and a drain electrode 143. The source electrode 133 is formed in contact with a source region of the TFT, and the drain electrode 143 is formed in contact with a drain region of the TFT. The source electrode 133 and the drain electrode 143 are separated by a gap in the doped semiconductor layer 123. The exposed part of the doped semiconductor layer 123 between the source electrode 133 and the drain electrode 143 is removed by etching, using the source electrode 133 and the drain electrode 143 as a mask so the doped semiconductor layer 123 is divided into two parts, as shown in FIG. 4c. The source line 135 connects the source electrodes 133 arrayed in a column direction. The source pad 137 is located at an end portion of the source line 135.
  • A [0046] protection layer 139 is formed by depositing an insulation material such as silicon nitride or silicon oxide on the substrate 111, the source electrode 133, the source line 135, the source pad 137, and drain electrode 143. The protection layer 139 is patterned to form a drain contact hole 181, a gate pad contact hole 187, and a source pad contact hole 197, as shown in FIG. 4d. The drain contact hole 181 exposes the drain electrode 143 by etching the protection layer 139 covering the drain electrode 143. The gate pad contact hole 187 exposes the second-metal gate pad 117 by removing the protection layer 139 and the gate insulation layer 119 covering the second-metal gate pad 117. The source pad contact hole 197 exposes the source pad 137 by etching the protection layer 139 covering the source pad 137. When the gate pad contact hole 187 is formed, the source pad contact hole 197 may also be formed by removing the protection layer 139 covering the source pad 137. Then, the exposed part of the second-metal gate pad 117 is removed by an etching method using the gate pad contact hole 187 as a mask, as shown in FIG. 4d.
  • An indium tin oxide layer is deposited on the [0047] protection layer 139, and is patterned to form a pixel electrode 153, a gate pad terminal 165, and a source pad terminal 175. The pixel electrode 153 connects to the drain electrode 143 through the drain contact hole 181. The gate pad terminal 165 is connected to the low resistance gate pad 117 a through the gate pad contact hole 187. The source pad terminal 175 is connected to the source pad 137 through the source pad contact hole 197, as shown in FIG. 4e.
  • According to this embodiment, the low [0048] resistance gate pad 117 a includes a first metal layer including aluminum, and the second-metal gate pad 117 includes a first metal layer including aluminum and a second metal layer including chromium or molybdenum. The second metal layer may cover the first metal layer entirely. So, the hillock problem which occurs on an aluminum surface is prevented by the second metal layer.
  • A portion of the second-[0049] metal gate pad 117 exposed through the gate pad contact hole 187 is removed by a wet etching method. The gate pad terminal 165 is formed by depositing an ITO layer over it, and patterning the ITO layer. Therefore, the exposed surface of the second-metal gate pad 117 is clear, and there are no contaminants such as molybdenum oxide, molybdenum nitride, chromium oxide, or chromium nitride between the second-metal gate pad 117 and the gate pad terminal 165.
  • The embodiment describes another example of a pad structure of an LCD and the manufacturing method for the same. According to the above preferred embodiment, the surface of a pad is a plane structure, as shown in FIG. 4[0050] e. This embodiment describes a pad structure where contact resistance between the pad and a pad terminal is reduced and the adhesion between them is enhanced.
  • In order to further improve and prevent the hillock problem on the aluminum surface, for example, an ITO/MoAlx/Al structure was used as the pixel electrode/intermetallic layer/gate, respectively. Although the hillock-free structure of the present invention is discussed with reference to the ITO/MoAlx/Al structure, other suitable materials may be used according to the present invention as discussed below. [0051]
  • The semiconductor device in accordance with the present embodiment includes a semiconductor device having a substrate and a first layer of a first conductive material on the substrate. The first layer preferably includes aluminum. The first layer may also include Cu or Au. A second layer of a second conductive material having a first hole is on a portion of the first layer. The second layer preferably includes molybdenum or an alloy including Mo. The second layer may also act as an etch stop layer. The first and second layers have a step structure. A spacing between an edge of the first layer to an edge of the second layer is preferably about 0.5 to 2 um. The first layer is preferably made of a material exhibiting a tensile stress and the second layer is made of a material exhibiting a compressive stress. [0052]
  • A third layer of conductive material is between the first and the second layers. The third layer preferably includes a combination of the first and the second layers of conductive material such as MoAlx. The third layer has an etching rate lower than the etching rate of the second layer. An insulating layer having a second hole is on the third layer. The insulating layer preferably includes a first pad insulating layer and a passivation layer over the first pad insulating layer. The insulating layer and the second layer preferably have etching rates higher than the first layer. The insulating layer and the second layer may have substantially the same etching rate. The insulating layer and the third layer includes multiple holes. A transparent conductive layer is on the third layer through the first and second holes. [0053]
    • EXAMPLE
  • As low resistive gate lines in thin film transistors (TFTs), the various structures of aluminum (Al) double layers patterned by one photolithography process have been investigated. For the Mo/Al structure, Al hillocks were not shown during and/or after a plasma enhanced chemical vapor depositions (PECVD) process of about 320° C. The stress of Al film is compensated by the compressive molybdenum (Mo) film. Additionally, this Mo layer prevented the surface of Al layers from oxidization during Indium-Tin-Oxide (ITO) pixel electrode deposition and annealing at the pad open regions. As a result, there was no contact problem in the ITO/Mo/Al structure. A 12.1 inch SVGA TFT-LCD was successfully fabricated by a simple process with the present structure as a gate line. [0054]
  • A low electrically resistive gate material, such as Al and its alloy, is needed in larger and higher quality thin film transistor liquid crystal displays (TFT-LCD). However, Al is likely to form hillocks during a high temperature process such as PECVD or annealing process. Many researches have been focused on preventing the Al hillocks, and some structures such as clad or Al/AlTa buffered structure, have been proposed as hillock-free gate structures. [0055]
  • In the clad structure were the Al metal is covered by refractory metals such as Cr, Mo, Ta, and Ti, two separated photolithography and wet etching processes are required to complete the gate bus line. On the other hand, the Al/AlTa buffered structure needs only one photolithography step for the gate bus line by etching the two metals simultaneously. However, this structure has a contact problem at the pad region where the ITO/Al contact is formed because of Al oxidation during ITO deposition and annealing process. The Al oxide layer causes the contact resistance to increase. The present inventors have shown that Al oxide layer is formed after 300° C. annealing processes analyzed by Electron Spectroscopy for Chemical Analysis (ESCA). A diffusion barrier metal can be inserted to prevent the Al oxidation. [0056]
  • The present inventors have investigated Mo/Al and AlTa/Al double layers for hillock-free Al gate metallization and ohmic contact in the pad region [ITO/(Cr, Mo, AlTa)/Al]. The double metals were deposited continuously without breaking the vacuum and patterned by wet etching with only one photolithography process. The internal stress of the double metal layers and the etched profile of the metals were changed to clarify the hillock prevention mechanism. [0057]
  • Al hillocks were found in the Cr/Al and the AlTa/Al double layers but not in the Mo/Al. This result can be explained by the stress balance between the upper refractory metals and the bottom Al. While the Al, AlTa and Cr layers have a tensile stress, the Mo layer has a compressive stress. Therefore, as the processing temperature increases, Al hillocks could be suppressed by stress compensation between Mo and Al layers. [0058]
  • The stress was measured during the heating and cooling process. As the temperature increased up to 160° C., all the materials deformed elastically. Above 160° C., Al and Al/Mo deformed plastically and the hillocks began to form. However, the Mo/Al layer continued to deform elastically. The thermally induced stress was accumulated at the Mo/Al interface due to the stress balance between the two films. As a result, hillocks were prevented because the critical stress for Al diffusion was not applied to the Al film. [0059]
  • In order to investigate the Al side hillock formation, different etch profiles were made in the Mo/Al structure. The side hillocks did not happen in all the samples. According to these results, not only the side of the etched Al but also the Al would be under the stress compensation effects of the upper Mo layer. These results also provide a large tolerance of the etch profiles for a good step-coverage of the gate insulator which could prevent an electrical short between the gate and the data bus line. [0060]
  • The Mo layer at the pad region was not etched off during the dry etching process of a gate insulator. As a result, ITO/Mo/Al contact was successfully formed. The inserted Mo layer prevented the Al oxidation during the ITO deposition and the annealing process by blocking the diffusing oxygen atoms into the Al surface. [0061]
  • Alternatively, the inserted Mo layer was etched off during the gate insulator dry etching process as shown in FIG. 7[0062] a, for example. There was no contract problem because an MoAlx intermetallic compound was formed at the Al surface.
  • According to the Augur Electron Spectroscopy (AES) analysis shown in FIG. 5, no Al[0063] 2O3 layer was detected between the ITO/ MoAlx/Al interface. After the severe SiNx dry etching process, which does not have the high selectivity between the SiNx and Mo, MoAlx layer acted as a diffusion barrier between the ITO and the Al during thermal annealing and ITO deposition processes. The MoAlx layer may be formed after high temperature PECVD SiNx deposition.
  • Using the above, a 12.1″ SVGA TFT-LCD was manufactured by a simple process. As an example, the transfer characteristics of a —Si TFT with Mo/Al double layer gate metallization showed that on-current was up to 5.04 μ[0064] A (V8=20V, Vd=1OV), off-current was 1.18 pA (V8=10V˜OV) and the mobility was 0.7 cm2/v·sec. There was no gate line delay and no contact problems in the pad open region.
  • Accordingly, hillock-free Al gate metallization of Mo/Al was investigated and the hillock prevention mechanism was studied. The Al hillocks were prevented by the stress compensation effect of the upper Mo layer during the thermal process. This effect enlarged the process tolerance of a wet etching process of the gate material for a good step coverage. [0065]
  • Additionally, the contact problem between the ITO and the Al layer at the pad region was completely solved by the Mo layer between them. As a diffusion barrier of oxygen, the MoAl[0066] x layer prevented the Al oxide formation between the ITO/Al interface.
  • To improve contact resistance in the present invention, the contact area can be enlarged. The surface of the pad has a raised part and a depressed part. In this embodiment, the pad contact hole has many small holes, rather than a single hole, as shown in FIG. 6. FIG. 6 shows a pad structure in which the pad has many small contact holes. FIG. 7[0067] a shows a cross-sectional view of a pad having one contact hole, and FIG. 7b shows the cross sectional view of a pad having several small contact holes. As shown in FIGS. 7a and 7 b, an intermetallic layer 199 is formed between the low resistance gate pad 117 a and a second metal gate pad 117. The intermetallic layer 199 is preferably formed of MoAlx from the Al layer below the Mo layer. MoAlx is formed during the gate insulator dry etching process, for example, which also etches off the portion of the Mo layer 117 corresponding to the MoAlx layer.
  • The ITO layer, which will become a pad terminal, is usually sputtered in an oxygen atmosphere. Here, a thin aluminum oxide layer will be formed on the exposed pad surface that includes aluminum. Aluminum oxide has high resistance to electrical current. Therefore, the existence of the aluminum oxide layer hinders electrical contact. In this embodiment, the gate [0068] pad contact hole 187 includes many small holes and the second-metal gate pad 117 is patterned by an etching method using the small holes as a mask. In spite of the fact that a thin aluminum oxide layer is formed on the exposed low resistance gate pad 117 a which includes aluminum, the gate pad terminal 165 is also in contact with side portions of the etched second-metal gate pad 117 which includes molybdenum or chromium. The contact area is enlarged because of the uneven surface shape, and contact resistance between the second-metal gate pad 117 and the gate pad terminal 165 is reduced.
  • Furthermore, the small holes may have any shape, as shown in FIGS. 8[0069] a and 8 b. The small holes may be formed over the entire pad part or some part of the pad.
  • While the invention on has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. [0070]

Claims (73)

What is claimed is:
1. A method for manufacturing a semiconductor device, the method comprising the steps of:
forming a first layer of a first conductive material on a substrate;
forming a second layer of a second conductive material on the first layer;
etching the first and the second layer simultaneously to form a pad;
forming an insulating layer on the pad and the substrate; and
etching the insulating layer and the second layer simultaneously.
2. The method according to
claim 1
, wherein the first layer includes aluminum
3. The method according to
claim 1
, wherein the second layer includes molybdenum.
4. The method according to
claim 1
, wherein the insulating layer and the second layer have substantially the same etching rate.
5. The method according to
claim 1
, wherein the insulating layer and the second layer have etching rates higher than the first layer.
6. The method according to
claim 1
, wherein the insulating layer includes:
a first pad insulating layer; and
a passivation layer over the first pad insulating layer.
7. The method according to
claim 1
, wherein the step of etching the first and the second layers simultaneously uses only one mask.
8. The method according to
claim 1
, wherein the step of forming the second layer includes the step of forming a third layer between the first and the second layers, the third layer including a combination of the first and the second layers.
9. The method according to
claim 8
, wherein the third layer includes MoAlx.
10. The method according to
claim 8
, wherein the step of etching the insulating layer and the second layer exposes a portion of the third layer.
11. The method according to
claim 8
, wherein the third layer has an etching rate lower than etching rates of the second layer.
12. The method according to
claim 8
, wherein the third layer acts as an etch stop layer.
13. The method according to
claim 1
, wherein the step of etching the insulating layer and the second layer forms multiple holes.
14. The method according to
claim 1
, wherein the second layer has a width smaller than the first layer.
15. The method according to
claim 14
, wherein the first layer is wider than the second layer by about 1 to 4 um.
16. The method according to
claim 1
, wherein the first layer is formed of a material exhibiting a tensile stress and the second layer is formed of a material exhibiting a compressive stress.
17. The method according to
claim 1
, wherein the first layer includes one of Cu and Au.
18. The method according to
claim 1
, wherein the second layer includes an alloy including Mo.
19. The method according to
claim 1
, further comprising a transparent conductive layer over the first layer and contacting a portion of the second layer.
20. The method according to
claim 1
, wherein the transparent conductive layer includes indium tin oxide.
21. The method according to
claim 8
, further comprising a transparent conductive layer on the third layer.
22. The method according to
claim 1
, wherein the step of etching the first and the second layers includes wet etching.
23. The method according to
claim 1
, wherein the step of etching the insulating layer and the second layer includes dry etching.
24. A semiconductor device comprising:
a substrate;
a first layer of a firs conductive material on the substrate;
a second layer of a second conductive material having a first hole on a portion of the first layer;
a third layer of conductive material between the first and the second layers;
an insulating layer having a second hole on the third layer; and
a transparent conductive layer on the third layer through the first and second holes.
25. The semiconductor device according to
claim 24
, wherein the first layer includes aluminum
26. The semiconductor device according to
claim 24
, wherein the second layer includes molybdenum.
27. The semiconductor device according to
claim 24
, wherein the insulating layer and the second layer have substantially the same etching rate.
28. The semiconductor device according to
claim 24
, wherein the insulating layer and the second layer have etching rates higher than the first layer.
29. The semiconductor device according to
claim 24
, wherein the insulating layer includes:
a first pad insulating layer; and
a passivation layer over the first pad insulating layer.
30. The semiconductor device according to
claim 24
, wherein the third layer including a combination of the first and the second layers.
31. The semiconductor device according to
claim 24
, wherein the third layer includes AlMox.
32. The semiconductor device according to
claim 24
, wherein the third layer has an etching rate lower than etching rate of the second layer.
33. The semiconductor device according to
claim 24
, wherein the second layer acts as an etch stop layer.
34. The semiconductor device according to
claim 24
, wherein the insulating layer and the third layer includes multiple holes.
35. The semiconductor device according to
claim 24
, wherein the first and second layers have a step structure.
36. The semiconductor device according to
claim 36
, wherein a spacing between an edge of the first layer to an edge of the second layer is about 0.5 to 2 um.
37. The semiconductor device according to
claim 24
, wherein the first layer is made of a material exhibiting a tensile stress and the second layer is made of a material exhibiting a compressive stress.
38. The semiconductor device according to
claim 24
, wherein the first layer includes one of Cu and Au.
39. The semiconductor device according to
claim 24
, wherein the second layer includes an alloy including Mo.
40. The semiconductor device according to
claim 24
, wherein the transparent conductive layer includes indium tin oxide.
41. The semiconductor device according to
claim 24
, wherein the first and second holes are substantially aligned with each other.
42. A method for manufacturing a semiconductor device, the method comprising the steps of:
forming a first layer of a first conductive material on a substrate, the first layer having a first etching rate;
forming a second layer of a second conductive material on the first layer, the second layer having a second etching rate, the second etching rate of the second layer being higher than the first etching rate of the first layer;
forming a third layer between the first and second layers, the third layer including a combination of the first and second layers, the third layer having a third etching rate lower than the second etching rate of the second layer;
etching the first and the second layer simultaneously to form a pad;
forming an insulating layer having a fourth etching rate on the pad and the substrate, the fourth etching rate being higher than the first etching rate of the first layer; and
etching the insulating layer and the second layer simultaneously using a single mask to expose a portion of the third layer.
43. The method according to
claim 42
, wherein the first layer includes aluminum
44. The method according to
claim 42
, wherein the second layer includes molybdenum.
45. The method according to
claim 42
, wherein the insulating layer and the second layer have substantially the same etching rate.
46. The method according to
claim 42
, wherein the insulating layer includes:
a first pad insulating layer; and
a passivation layer over the first pad insulating layer.
47. The method according to
claim 42
, wherein the third layer includes AlMox.
48. The method according to
claim 42
, wherein the third layer acts as an etch stop layer.
49. The method according to
claim 42
, wherein the step of etching the insulating layer and the second layer forms multiple holes.
50. The method according to
claim 42
, wherein the second layer has a width smaller than the first layer.
51. The method according to
claim 49
, wherein the first layer is wider than the second layer by about 1 to 4 um.
52. The method according to
claim 42
, wherein the first layer is formed of a material exhibiting a tensile stress and the second layer is formed of a material exhibiting a compressive stress.
53. The method according to
claim 42
, wherein the first layer includes one of Cu and Au.
54. The method according to
claim 42
, wherein the second layer includes an alloy including Mo.
55. The method according to
claim 42
, further comprising a transparent conductive layer over the first layer and contacting a portion of the second layer.
56. The method according to
claim 42
, wherein the transparent conductive layer includes indium tin oxide.
57. The method according to
claim 42
, further comprising a transparent conductive layer on the third layer.
58. The method according to
claim 42
, wherein the step of etching the first and the second layers includes wet etching.
59. The method according to
claim 42
, wherein the step of etching the insulating layer and the second layer includes dry etching.
60. A semiconductor device comprising:
a substrate;
a first layer of a first conductive material on the substrate, the first layer having a first etching rate;
a second layer of a second conductive material having a first hole on a portion of the first layer, the second layer having a second etching rate higher than the first etching rate;
a third layer including a combination of the first and second layers between the first and the second layers, the third layer having a third etching rate lower than the second etching rate;
an insulating layer having a second hole on the third layer, the insulating layer having a fourth etching rate higher than the first etching rate; and
a transparent conductive layer on the third layer through the first and second holes.
61. The semiconductor device according to
claim 60
, wherein the first layer includes aluminum
62. The semiconductor device according to
claim 60
, wherein the second layer includes molybdenum.
63. The semiconductor device according to
claim 60
, wherein the insulating layer and the second layer have substantially the same etching rate.
64. The semiconductor device according to
claim 60
, wherein the insulating layer includes:
a first pad insulating layer; and
a passivation layer over the first pad insulating layer.
65. The semiconductor device according to
claim 60
, wherein the third layer includes AlMox.
66. The semiconductor device according to
claim 60
, wherein the second layer acts as an etch stop layer.
67. The semiconductor device according to
claim 60
, wherein the insulating layer and the third layer includes multiple holes.
68. The semiconductor device according to
claim 60
, wherein the first and second layers have a step structure.
69. The semiconductor device according to
claim 60
, wherein a spacing between an edge of the first layer to an edge of the second layer is about 0.5 to 2 um.
70. The semiconductor device according to
claim 60
, wherein the first layer is made of a material exhibiting a tensile stress and the second layer is made of a material exhibiting a compressive stress.
71. The semiconductor device according to
claim 60
, wherein the first layer includes one of Cu and Au.
72. The semiconductor device according to
claim 60
, wherein the second layer includes an alloy including Mo.
73. The semiconductor device according to
claim 60
, wherein the transparent conductive layer includes indium tin oxide.
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