US20010034108A1 - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- US20010034108A1 US20010034108A1 US09/886,705 US88670501A US2001034108A1 US 20010034108 A1 US20010034108 A1 US 20010034108A1 US 88670501 A US88670501 A US 88670501A US 2001034108 A1 US2001034108 A1 US 2001034108A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device and a method for manufacturing it and in particular to a method for manufacturing a box mark for automatic overlay measurement used in a lithography process.
- the lithography process is required to form each of layers of a semiconductor device in a predetermined shape. In this process, it is needed when forming a resist pattern in a certain layer to conduct it while aligning a mask pattern with its underlying layer according to a predetermined standard.
- the predetermined standard concerning the pattern overlay accuracy is becoming strictly as the semiconductor devices become fine.
- FIGS. 1A through 1F are sectional views for description of manufacture processes of the conventional method.
- FIG. 2 is a top view for description of the conventional method.
- Word lines and bit lines are formed on a semiconductor substrate having devices formed thereon. Thereafter, a capacity contact pattern is formed between word lines and bit lines in a lithography process. Here, the lithography process is shown.
- element isolation regions 102 are first formed on a semiconductor substrate 101 .
- word lines 105 each having a polycide structure are formed.
- an integral outside box mark 105 a for automatic misalignment measurement is also formed on a scribe line simultaneously with formation of the word lines 105 .
- pad polysilicon regions 10 are formed on predetermined areas on the word lines 105 .
- an oxide film 103 having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like.
- CVD chemical vapor deposition
- CAP chemical-mechanical polishing
- a resist 107 is applied to the surface of the oxide film 103 .
- a mask for forming a contact hole 109 having an inside box mark 11 for automatic overlay measurement added thereto exposure and development are conducted. Thereafter, a misalignment value from the inside box mark 11 formed over the outside box mark 105 a is read by using an automatic overlay measuring instrument. Thereby, a misalignment value between the word line 105 and the contact hole 109 is measured.
- the misalignment value is inputted as an offset value of an aligner.
- a resist 107 is applied on the surface of the oxide film 103 again, and exposure of the contact hole 109 is conducted.
- a predetermined region of the oxide film 103 is removed, by using the photoresist 107 formed so as to have a predetermined pattern shape, as a mask, and by using anisotropic etching or the like.
- a contact hole 109 is thus formed.
- WSi is buried in the contact hole 109 , and in addition, WSi serving as a bit line 111 is deposited.
- bit lines 111 having an integral outside box mark 111 a for automatic overlay measurement added thereto.
- the bit lines 111 are thus formed, and the outside box mark 111 a is newly formed.
- misalignment of the bit lines 111 is measured by using the box mark 111 a formed at the time of contact described before.
- an oxide film 150 having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like.
- CVD chemical vapor deposition
- CMP chemical-mechanical polishing
- a photoresist film 113 is applied to the surface of the oxide film 150 .
- a mask for forming capacity contacts 114 having an inside box mark 17 for automatic overlay measurement added thereto exposure and development are conducted.
- a misalignment value in the X direction (the lateral direction of FIGS. 1A through 1F) is read from the outside box mark 105 a formed in the process of FIG. 1B, and a misalignment value in the Y direction (the depth direction of FIGS. 1A through 1F) is read from the outside box mark 111 a formed in the process of FIG. 1E.
- the capacity contacts 114 are thus formed.
- An object of the present invention is to provide a method for shortening, in the manufacture processes of a semiconductor device, the time for measuring the overlay between the underlying layer and a mask pattern at the time of lithography, and the time for analyzing the measurement result.
- a semiconductor device has such patterns of a plurality of layers formed on a substrate that respective layers are laminated in predetermined position relations.
- a first mark disposed at the time of first pattern formation and a second mark disposed at the time of second pattern formation form one misalignment measurement mark, and position aligning for third or subsequent pattern formation is conducted with the misalignment measurement mark.
- a semiconductor device includes: a first mark forming a part of a misalignment measurement mark disposed in a predetermined position of a substrate at the time of first pattern formation; and a second mark forming another part of said misalignment measurement mark disposed at the time of second pattern formation, wherein the first mark and the second mark form one of the misalignment measurement mark, and the misalignment measurement mark is used for position aligning with a mark of mask side at the time of third or subsequent pattern formation,
- a manufacture method includes the steps of: forming a first mark in a predetermined position of the substrate at the time of first pattern formation, the first mark forming a part of a misalignment measurement mark used in a subsequent pattern forming step; forming a second mark forming another part of said misalignment measurement mark at the time of second pattern formation; and positioning and adjusting a mark of mask side at the time of third or subsequent pattern formation by using the misalignment measurement mark produced in previous pattern forming process, and conducting third pattern formation or subsequent pattern formation.
- a # shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines, as an outside box mark for automatic overlay measurement formed on a semiconductor substrate.
- a misalignment value from the word line and a misalignment value from the bit line can be measured by using one box mark.
- the measurement accuracy can be further improved.
- FIGS. 1A through 1F are sectional views showing a conventional method for manufacturing a semiconductor device in the order of process
- FIG. 2 is a plan view showing a conventional semiconductor device
- FIGS. 3A through 3F are sectional views showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of process;
- FIG. 4 is a plan view showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
- FIGS. 5A through 5F are sectional views showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention in the order of process.
- FIGS. 3A through 3F are sectional views showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of process.
- FIG. 4 is its plan view.
- a method for manufacturing a semiconductor device having at least three wiring layers laminated on a substrate includes the steps of disposing outside box mark (word lines) 205 a extending in one direction in a predetermined position when forming the word lines 205 , disposing outside box mark (bit lines) 211 a extending in a direction perpendicular to the outside box mark (word lines) when forming the bit lines 211 , thereby forming one misalignment measurement mark 205 a and 211 a , disposing an inside box mark 27 on the substrate by using a mask for forming capacity contacts, measuring misalignment values of the misalignment measurement mark and the inside box mark, inputting the values to the aligner as offset values, and forming a pattern of the capacity contacts 214 .
- the first embodiment shows a lithography process for forming a pattern of capacity contacts 214 arranged between word lines 205 and bit lines 211 , after the word lines and the bit lines 211 have been formed on a semiconductor substrate 201 having elements formed thereon.
- device isolation regions 202 are first formed on the semiconductor substrate 201 .
- word lines 205 each having a polycide structure are formed.
- an outside box mark (word lines) 205 a for automatic misalignment measurement is also formed on scribe lines 204 simultaneously with formation of the word lines 205 .
- pad polysilicon regions 20 are formed on predetermined areas on the word lines 205 .
- an oxide film 203 having a film thickness of, for example, approximately 800 an is deposited by using the chemical vapor deposition (CVD) method or the like.
- CVD chemical vapor deposition
- CMP chemical-mechanical polishing
- a resist 207 is applied to the surface of the oxide film 203 .
- a mask for forming a contact hole 209 having an inside box mark 21 for automatic overlay measurement added thereto exposure and development are conducted. Thereafter, a misalignment value from the inside box mark 21 formed over the outside box mark (word lines) 205 a is read by using an automatic overlay measuring instrument. Thereby, a misalignment value between the word line 205 and the contact hole 209 is measured.
- the misalignment value is inputted as an offset value of an aligner.
- a resist 207 is applied on the surface of the oxide film 203 again, and exposure of the contact hole 209 is conducted.
- a predetermined region of the oxide film 203 is removed, by using the photoresist 207 formed so as to have a predetermined pattern shape, as a mask, and by using anisotropic etching or the like.
- a contact hole 25 is thus formed.
- WSi is buried in the contact hole 25 , and in addition, WSi serving as a bit line 211 is deposited.
- bit lines 211 a for automatic overlay measurement added thereto
- the bit lines 211 are thus formed, and in addition the outside box mark (bit lines) 211 a is formed so as to overlie the outside box mark 205 a formed of word lines.
- misalignment of the bit lines 211 is measured by using the outside box mark (bit lines) 211 a formed at the time of contact described before.
- an oxide film 250 having a film thickness of, for example, approximately 800 nm is deposited by using the Chemical vapor deposition (CVD) method or the like, As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on the oxide film 250 to planarize the oxide film 250 .
- CVD Chemical vapor deposition
- CMP chemical-mechanical polishing
- a photoresist film 213 is applied to the surface of the oxide film 250 .
- a mask for forming capacity contacts having an inside box mark 213 a for automatic overlay measurement added thereto
- exposure and development are conducted by using a mask for forming capacity contacts.
- the automatic overlay measuring instrument the #-shaped outside box mark ( 205 a and 211 a ) formed of the word lines 205 and the bit lines 211 , and the inside box mark 213 a are measured. Thereby, a misalignment value in the X direction (the lateral direction of FIGS.
- FIGS., 5 A through 5 F a second embodiment of the present invention will now be described.
- device isolation regions 302 are formed on a semiconductor substrate 301 in the same way as FIG. 3A, and thereafter an outside box mark (word lines) 305 a of slit type for automatic overlay measurement is formed on scribe lines simultaneously with formation of the word lines 305 as shown in FIG. 5B.
- word lines outside box mark
- pad polysilicon regions 30 and an oxide film 303 are formed in the same way as FIGS. 3C through 3D.
- a predetermined area of the oxide film 303 is removed by anisotropic etching or the like and a contact hole 35 is formed as shown in FIGS. 5D and 5E.
- the oxide film 303 is buried in the outside box mark (word lines) 305 a of slit type for automatic overlay measurement formed on the scribe lines simultaneously with the word lines 305 .
- exposure and development are conducted by using a bit line forming mask having an outside box mark (bit lines) 311 a for automatic overlay measurement added thereto.
- bit lines 311 are formed, and in addition, the outside box mark (bit lines) 311 a is formed so as to overlie the outside box mark (word lines) 305 a of slit type formed of the word lines 305 .
- edges of a #-shaped box mark formed by the outside box mark (word lines) 305 a of slit type and outside box mark (bit lines) 311 a become sharp. And the overlay measurement accuracy of the automatic overlay measuring instrument is improved.
Abstract
As an outside box mark for automatic overlay measurement formed on a semiconductor substrate, a # shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines. Thereby, a misalignment value in the word line direction and a misalignment value in the bit line direction are measured simultaneously by using one box mark. When forming capacity contacts between wiring lines of a #-shaped structure formed of word lines and bit lines, it is conducted by using a box mark for automatic overlay measurement. As a result, it becomes possible to shorten the time required for measuring the misalignment values in the X direction (word lines) and Y direction (bit lines) and analyzing the measurement result.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device and a method for manufacturing it and in particular to a method for manufacturing a box mark for automatic overlay measurement used in a lithography process.
- 2. Description of the Related Art
- In semiconductor device manufacture, the lithography process is required to form each of layers of a semiconductor device in a predetermined shape. In this process, it is needed when forming a resist pattern in a certain layer to conduct it while aligning a mask pattern with its underlying layer according to a predetermined standard. The predetermined standard concerning the pattern overlay accuracy is becoming strictly as the semiconductor devices become fine.
- Hereafter, a box mark for automatic overlay measurement between a mask pattern and its underlying layer used in a conventional lithography process will be described.
- FIGS. 1A through 1F are sectional views for description of manufacture processes of the conventional method. FIG. 2 is a top view for description of the conventional method. Word lines and bit lines are formed on a semiconductor substrate having devices formed thereon. Thereafter, a capacity contact pattern is formed between word lines and bit lines in a lithography process. Here, the lithography process is shown.
- As shown in FIG. 1A,
element isolation regions 102 are first formed on asemiconductor substrate 101. - Subsequently, as shown in FIG. 1B,
word lines 105 each having a polycide structure are formed. At this time, an integraloutside box mark 105 a for automatic misalignment measurement is also formed on a scribe line simultaneously with formation of theword lines 105. - Subsequently, as shown in FIG. 1C,
pad polysilicon regions 10 are formed on predetermined areas on theword lines 105. Thereafter, anoxide film 103 having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CAP), or the like is conducted on theoxide film 103 to planarize theoxide film 103, - As shown in FIG. 1D, a
resist 107 is applied to the surface of theoxide film 103. By using a mask for forming acontact hole 109 having aninside box mark 11 for automatic overlay measurement added thereto, exposure and development are conducted. Thereafter, a misalignment value from theinside box mark 11 formed over theoutside box mark 105 a is read by using an automatic overlay measuring instrument. Thereby, a misalignment value between theword line 105 and thecontact hole 109 is measured. - In succession, the misalignment value is inputted as an offset value of an aligner. A
resist 107 is applied on the surface of theoxide film 103 again, and exposure of thecontact hole 109 is conducted. - Subsequently, as shown in FIG. 1E, a predetermined region of the
oxide film 103 is removed, by using thephotoresist 107 formed so as to have a predetermined pattern shape, as a mask, and by using anisotropic etching or the like. Acontact hole 109 is thus formed. Furthermore, by way of a predetermined process, WSi is buried in thecontact hole 109, and in addition, WSi serving as abit line 111 is deposited. - Thereafter, in the same way as the
word line 105, exposure and development are conducted by using a mask for forming thebit lines 111 having an integraloutside box mark 111 a for automatic overlay measurement added thereto. Thebit lines 111 are thus formed, and theoutside box mark 111 a is newly formed. At this time, misalignment of thebit lines 111 is measured by using thebox mark 111 a formed at the time of contact described before. - Subsequently, as shown in FIG. 1F, an
oxide film 150 having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on theoxide film 150 to planarize theoxide film 150. - Thereafter, a
photoresist film 113 is applied to the surface of theoxide film 150. By using a mask for formingcapacity contacts 114 having aninside box mark 17 for automatic overlay measurement added thereto, exposure and development are conducted. Thereafter, by using the automatic overlay measuring instrument, a misalignment value in the X direction (the lateral direction of FIGS. 1A through 1F) is read from theoutside box mark 105 a formed in the process of FIG. 1B, and a misalignment value in the Y direction (the depth direction of FIGS. 1A through 1F) is read from theoutside box mark 111 a formed in the process of FIG. 1E. Between wiring lines forming the shape of #, thecapacity contacts 114 are thus formed. - In the above described integral outside box mark for automatic overlay measurement, however, two box marks are required to measure the misalignment values in the X direction (word line) and Y direction (bit line) when forming capacity contacts between word lines and between bit lines. Therefore, there is a problem that it takes a time to measure the misalignment values and analyze the measurement results
- An object of the present invention is to provide a method for shortening, in the manufacture processes of a semiconductor device, the time for measuring the overlay between the underlying layer and a mask pattern at the time of lithography, and the time for analyzing the measurement result.
- A semiconductor device according to the present invention has such patterns of a plurality of layers formed on a substrate that respective layers are laminated in predetermined position relations. In the present invention, a first mark disposed at the time of first pattern formation and a second mark disposed at the time of second pattern formation form one misalignment measurement mark, and position aligning for third or subsequent pattern formation is conducted with the misalignment measurement mark.
- In accordance with another aspect of the present invention, a semiconductor device includes: a first mark forming a part of a misalignment measurement mark disposed in a predetermined position of a substrate at the time of first pattern formation; and a second mark forming another part of said misalignment measurement mark disposed at the time of second pattern formation, wherein the first mark and the second mark form one of the misalignment measurement mark, and the misalignment measurement mark is used for position aligning with a mark of mask side at the time of third or subsequent pattern formation,
- A manufacture method according to the present invention, said semiconductor device having such patterns of a plurality of layers formed on a substrate that respective layers are laminated in predetermined position relations, includes the steps of: forming a first mark in a predetermined position of the substrate at the time of first pattern formation, the first mark forming a part of a misalignment measurement mark used in a subsequent pattern forming step; forming a second mark forming another part of said misalignment measurement mark at the time of second pattern formation; and positioning and adjusting a mark of mask side at the time of third or subsequent pattern formation by using the misalignment measurement mark produced in previous pattern forming process, and conducting third pattern formation or subsequent pattern formation.
- In accordance with a method for manufacturing a semiconductor device according to the present invention, a # shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines, as an outside box mark for automatic overlay measurement formed on a semiconductor substrate. Thereby, a misalignment value from the word line and a misalignment value from the bit line can be measured by using one box mark. As a results it becomes also possible to shorten the time required for measuring the misalignment values and analyzing the measurement result. Furthermore, by using a #-shaped box mark of slit type, the measurement accuracy can be further improved.
- FIGS. 1A through 1F are sectional views showing a conventional method for manufacturing a semiconductor device in the order of process;
- FIG. 2 is a plan view showing a conventional semiconductor device;
- FIGS. 3A through 3F are sectional views showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of process;
- FIG. 4 is a plan view showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention; and
- FIGS. 5A through 5F are sectional views showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention in the order of process.
- Hereafter, preferred embodiments of the present invention will be described concretely by referring to accompanying drawing. FIGS. 3A through 3F are sectional views showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of process. FIG. 4 is its plan view. A method for manufacturing a semiconductor device having at least three wiring layers laminated on a substrate includes the steps of disposing outside box mark (word lines)205 a extending in one direction in a predetermined position when forming the word lines 205, disposing outside box mark (bit lines) 211 a extending in a direction perpendicular to the outside box mark (word lines) when forming the
bit lines 211, thereby forming onemisalignment measurement mark inside box mark 27 on the substrate by using a mask for forming capacity contacts, measuring misalignment values of the misalignment measurement mark and the inside box mark, inputting the values to the aligner as offset values, and forming a pattern of thecapacity contacts 214. - In the same way as the conventional example, the first embodiment shows a lithography process for forming a pattern of
capacity contacts 214 arranged betweenword lines 205 andbit lines 211, after the word lines and thebit lines 211 have been formed on asemiconductor substrate 201 having elements formed thereon. - As shown in FIG. 3A,
device isolation regions 202 are first formed on thesemiconductor substrate 201. - Subsequently, as shown in FIG. 3B, word lines205 each having a polycide structure are formed. At this time, an outside box mark (word lines) 205 a for automatic misalignment measurement is also formed on scribe lines 204 simultaneously with formation of the word lines 205.
- Thereafter, as shown in FIG. 3C,
pad polysilicon regions 20 are formed on predetermined areas on the word lines 205. Thereafter, anoxide film 203 having a film thickness of, for example, approximately 800 an is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on theoxide film 203 to planarize theoxide film 203. - As shown in FIG. 3D, a resist207 is applied to the surface of the
oxide film 203. By using a mask for forming acontact hole 209 having aninside box mark 21 for automatic overlay measurement added thereto, exposure and development are conducted. Thereafter, a misalignment value from theinside box mark 21 formed over the outside box mark (word lines) 205 a is read by using an automatic overlay measuring instrument. Thereby, a misalignment value between theword line 205 and thecontact hole 209 is measured. - In succession, the misalignment value is inputted as an offset value of an aligner. A resist207 is applied on the surface of the
oxide film 203 again, and exposure of thecontact hole 209 is conducted. - Subsequently, as shown in FIG. 3E, a predetermined region of the
oxide film 203 is removed, by using thephotoresist 207 formed so as to have a predetermined pattern shape, as a mask, and by using anisotropic etching or the like. Acontact hole 25 is thus formed. Furthermore, by way of a predetermined process, WSi is buried in thecontact hole 25, and in addition, WSi serving as abit line 211 is deposited. - Thereafter, in the same way as the
word line 205, exposure and development are conducted by using a mask for forming the bit lines having an outside box mark (bit lines) 211 a for automatic overlay measurement added thereto The bit lines 211 are thus formed, and in addition the outside box mark (bit lines) 211 a is formed so as to overlie theoutside box mark 205 a formed of word lines. At this time, misalignment of the bit lines 211 is measured by using the outside box mark (bit lines) 211 a formed at the time of contact described before. - Subsequently, as shown in FIG. 3F, an
oxide film 250 having a film thickness of, for example, approximately 800 nm is deposited by using the Chemical vapor deposition (CVD) method or the like, As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on theoxide film 250 to planarize theoxide film 250. - Thereafter, a
photoresist film 213 is applied to the surface of theoxide film 250. By using a mask for forming capacity contacts having an inside box mark 213 a for automatic overlay measurement added thereto, exposure and development are conducted by using a mask for forming capacity contacts. Thereafter, by using the automatic overlay measuring instrument, the #-shaped outside box mark (205 a and 211 a) formed of the word lines 205 and thebit lines 211, and the inside box mark 213 a are measured. Thereby, a misalignment value in the X direction (the lateral direction of FIGS. 3A through 3F) is read from theoutside box mark 205 a formed of the word lines, and a misalignment value in the Y direction (the depth direction of FIGS, 3A through 3F) is read from theoutside box mark 211 a formed of the bit lines 211. Between wiring lines forming the shape of #, thecapacity contacts 214 are thus formed. - By referring to FIGS.,5A through 5F, a second embodiment of the present invention will now be described.
- Processes in the second embodiment are basically the same as those in the first embodiment. Principally, changed points will now be described.
- In the second embodiment,
device isolation regions 302 are formed on asemiconductor substrate 301 in the same way as FIG. 3A, and thereafter an outside box mark (word lines) 305 a of slit type for automatic overlay measurement is formed on scribe lines simultaneously with formation of the word lines 305 as shown in FIG. 5B. - Thereafter,
pad polysilicon regions 30 and anoxide film 303 are formed in the same way as FIGS. 3C through 3D. - By using a resist307 formed in a predetermined shape, as a mask, a predetermined area of the
oxide film 303 is removed by anisotropic etching or the like and acontact hole 35 is formed as shown in FIGS. 5D and 5E. - At this time, the
oxide film 303 is buried in the outside box mark (word lines) 305 a of slit type for automatic overlay measurement formed on the scribe lines simultaneously with the word lines 305. Thereafter, exposure and development are conducted by using a bit line forming mask having an outside box mark (bit lines) 311 a for automatic overlay measurement added thereto. Thus,bit lines 311 are formed, and in addition, the outside box mark (bit lines) 311 a is formed so as to overlie the outside box mark (word lines) 305 a of slit type formed of the word lines 305. - As a result, edges of a #-shaped box mark formed by the outside box mark (word lines)305 a of slit type and outside box mark (bit lines) 311 a become sharp. And the overlay measurement accuracy of the automatic overlay measuring instrument is improved.
- Furthermore, by changing the outside box mark (bit lines)311 a as well to a box mark of slit type, a further improvement of the measurement accuracy can be expected.
- In the embodiments heretofore described, capacity contacts formed between word lines and between bit lines have been described. However, it can be applied between other processes as well in the same way.
Claims (24)
1. A semiconductor device manufactured by at least three exposure processes each using a mask for pattern formation, said semiconductor device comprising:
a first mark disposed in a predetermined position of a substrate at the time of first pattern formation, said first mark forming a part of a misalignment measurement mark; and
a second mark disposed at the time of second pattern formation, said second mark forming another part of said misalignment measurement mark, wherein
said first mark and said second mark form one of said misalignment measurement mark, and
said misalignment measurement mark is used for position aligning with a mark of mask side at the time of third or subsequent pattern formation.
2. A semiconductor device having such patterns of a plurality of layers formed on a substrate that respective layers are laminated in predetermined position relations, said semiconductor device comprising:
a first mark disposed in a predetermined position of a substrate at the time of first pattern formation, said first mark forming a part of a misalignment measurement mark; and
a second mark disposed at the time of second pattern formation, said second mark forming another part of said misalignment measurement mark, wherein
said first mark and said second mark form one of said misalignment measurement mark, and
said misalignment measurement mark is used for position aligning with a mark of mask side at the time of third or subsequent pattern formation.
3. A semiconductor device having a plurality of wiring layers on a substrate, said semiconductor device comprising:
a first mark disposed in a predetermined position on said substrate at the time of formation of a first wiring layer, said first mark forming a part of a misalignment measurement mark; and
a second mark disposed so as to be close to or cross said first mark at the time of formation of a second wiring layer, said second mark forming another part of said misalignment measurement mark, wherein
said first mark and said second mark form one of said misalignment measurement mark, and
said misalignment measurement mark is used for position aligning with a mark of mask side at the time of pattern formation of a third layer or a subsequent wiring layer.
4. A semiconductor device according to , wherein said first mark is formed of two line patterns extending in one direction, said second mark is formed of two line patterns extending in a direction substantially perpendicular to said first mark, and said misalignment measurement mark takes a shape of # when viewed from top of said substrate.
claim 1
5. A semiconductor device according to , wherein said first mark and said second mark are provided so as to correspond to layers having word lines and bit lines formed thereon.
claim 1
6. A semiconductor device according to , wherein a mark provided in a mask used for forming capacity contacts deposited on said bit lines corresponds to said #-shaped misalignment measurement mark.
claim 1
7. A semiconductor device according to , wherein said first mark is formed of two line patterns extending in one direction, said second mark is formed of two line patterns extending in a direction substantially perpendicular to said first mark, and said misalignment measurement mark takes a shape of # when viewed from top of said substrate.
claim 2
8. A semiconductor device according to , wherein said first mark and said second mark are provided so as to correspond to layers having word lines and bit lines formed thereon.
claim 2
9. A semiconductor device according to , wherein a mark provided in a mask used for forming capacity contacts deposited on said bit lines corresponds to said #-shaped misalignment measurement mark.
claim 2
10. A semiconductor device according to , wherein said first mark is formed of two line patterns extending in one direction, said second mark is formed of two line patterns extending in a direction substantially perpendicular to said first mark, and said misalignment measurement mark takes a shape of # when viewed from top of said substrate.
claim 3
11. A semiconductor device according to , wherein said first mark and said second mark are provided so as to correspond to layers having word lines and bit lines formed thereon.
claim 3
12. A semiconductor device according to , wherein a mark provided in a mask used for forming capacity contacts deposited on said bit lines corresponds to said #-shaped misalignment measurement mark.
claim 3
13. A method for manufacturing a semiconductor device, said semiconductor device having such patterns of a plurality of layers formed on a substrate that respective layers are laminated in predetermined position relations, said method comprising the steps of:
forming a first mark in a predetermined position of said substrate at the time of first pattern formation, said first mark forming a part of a misalignment measurement mark used in a subsequent pattern forming step;
forming a second mark at the time of second pattern formation, Said second mark forming another part of said misalignment measurement mark; and
positioning and adjusting a mark of mask side at the time of third or subsequent pattern formation by using said misalignment measurement mark produced in previous pattern forming process, and conducting third pattern formation or subsequent pattern formation.
14. a method for manufacturing a semiconductor device of conducting resist pattern formation for laminating layers respectively having predetermined position relations, at least three times, said semiconductor device manufacture method comprising the steps of:
(a) disposing a first mark extending in one direction, in a predetermined position at the time of first pattern formation, said first mark forming a part of a misalignment measurement mark;
(b) disposing a second mark extending in a direction different from that of said first mark at the time of second pattern formation, and thereby forming one misalignment measurement mark;
(c) disposing a third mark in such a position as to be housed in said one misalignment measurement mark on a substrate when viewed from above, by using a mask for third pattern forming;
(d) measuring a misalignment value between said misalignment measurement mark and said third mark; and
(e) forming a third pattern when positioning the mask for third pattern forming, with due regard to said misalignment value measured in said step (d).
15. A method for manufacturing a semiconductor device on a substrate, said semiconductor device having at least three wiring layers laminated via insulation films between, said method comprising the steps of:
(a) disposing a first mark extending in one direction, in a predetermined position when forming a first layer, said first mark forming a part of a misalignment measurement mark;
(b) disposing a second mark extending in a direction different from that of said first mark when forming a second layer, and thereby forming one misalignment measurement mark;
(c) disposing a third mark in such a position as to be housed in said one misalignment measurement mark on said substrate when viewed from above, by using a mask for forming a third layer;
(d) measuring a misalignment value between said misalignment measurement mark and said third mark and
(e) forming a third layer when positioning the mask for forming a pattern of said third layer, with due regard to said misalignment value measured in said step (d).
16. A method for manufacturing a semiconductor device according to , wherein said first mark is formed of two line patterns extending in one direction, said second mark is formed of two line patterns extending in a direction substantially perpendicular to said first mark, and said misalignment measurement mark takes a shape of # when viewed from top of said substrate.
claim 13
17. A method for manufacturing a semiconductor device according to , wherein said first mark and said second mark are provided so as to correspond to layers having word lines and bit lines formed thereon.
claim 13
18. A method for manufacturing a semiconductor device according to , wherein a mark provided in a mask used for forming capacity contacts deposited on said bit lines corresponds to said #-shaped misalignment measurement mark.
claim 13
19. A method for manufacturing a semiconductor device according to , wherein said first mark is formed of two line patterns extending in one direction, said second mark is formed of two line patterns extending in a direction substantially perpendicular to said first mark, and said misalignment measurement mark takes a shape of # when viewed from top of said substrate.
claim 14
20. A method for manufacturing a semiconductor device according to , wherein said first mark and said second mark are provided so as to correspond to layers having word lines and bit lines formed thereon.
claim 14
21. A method for manufacturing a semiconductor device according to , wherein a mark provided in a mask used for forming capacity contacts deposited on said bit lines corresponds to said #-shaped misalignment measurement mark.
claim 14
22. A method for manufacturing a semiconductor device according to , wherein said first mark is formed of two line patterns extending in one direction, said second mark is formed of two line patterns extending in a direction substantially perpendicular to said first mark, and said misalignment measurement mark takes a shape of # when viewed from top of said substrate.
claim 15
23. A method for manufacturing a semiconductor device according to , wherein said first mark and said second mark are provided so as to correspond to layers having word lines and bit lines formed thereon.
claim 15
24. A method for manufacturing a semiconductor device according to , wherein a mark provided in a mask used for forming capacity contacts deposited on said bit lines corresponds to said #-shaped misalignment measurement mark.
claim 15
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/886,705 US6448147B2 (en) | 1998-03-27 | 2001-06-21 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10048398A JP3211767B2 (en) | 1998-03-27 | 1998-03-27 | Method for manufacturing semiconductor device |
JP10-100483 | 1998-03-27 | ||
US09/281,111 US6288452B1 (en) | 1998-03-27 | 1999-03-29 | Semiconductor device including registration accuracy marks |
US09/886,705 US6448147B2 (en) | 1998-03-27 | 2001-06-21 | Semiconductor device and method for manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/281,111 Division US6288452B1 (en) | 1998-03-27 | 1999-03-29 | Semiconductor device including registration accuracy marks |
Publications (2)
Publication Number | Publication Date |
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US20010034108A1 true US20010034108A1 (en) | 2001-10-25 |
US6448147B2 US6448147B2 (en) | 2002-09-10 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US09/281,111 Expired - Fee Related US6288452B1 (en) | 1998-03-27 | 1999-03-29 | Semiconductor device including registration accuracy marks |
US09/886,705 Expired - Fee Related US6448147B2 (en) | 1998-03-27 | 2001-06-21 | Semiconductor device and method for manufacturing the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/281,111 Expired - Fee Related US6288452B1 (en) | 1998-03-27 | 1999-03-29 | Semiconductor device including registration accuracy marks |
Country Status (5)
Country | Link |
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US (2) | US6288452B1 (en) |
JP (1) | JP3211767B2 (en) |
KR (1) | KR100306705B1 (en) |
CN (1) | CN1231501A (en) |
TW (1) | TW442844B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6876021B2 (en) | 2002-11-25 | 2005-04-05 | Texas Instruments Incorporated | Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier |
US20210063997A1 (en) * | 2019-08-30 | 2021-03-04 | Micron Technology, Inc. | Methods for aligning a physical layer to a pattern formed via multi-patterning, and associated systems |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6486036B1 (en) * | 2000-06-28 | 2002-11-26 | Advanced Micro Devices, Inc. | Method and apparatus for process control of alignment in dual damascene processes |
JP2002164517A (en) * | 2000-11-28 | 2002-06-07 | Mitsubishi Electric Corp | Semiconductor device having element for test and its manufacturing method |
US7190823B2 (en) | 2002-03-17 | 2007-03-13 | United Microelectronics Corp. | Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same |
DE10345524B4 (en) * | 2003-09-30 | 2005-10-13 | Infineon Technologies Ag | Method for determining a relative offset of two structured circuit patterns on a semiconductor wafer by means of a scanning electron microscope |
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JPS6450529A (en) * | 1987-08-21 | 1989-02-27 | Oki Electric Ind Co Ltd | Wafer alignment |
JPH0247821A (en) * | 1988-08-10 | 1990-02-16 | Nec Corp | Manufacture of semiconductor integrated circuit device |
JP2713500B2 (en) * | 1989-09-28 | 1998-02-16 | 松下電子工業株式会社 | Alignment method, alignment mark, and pattern detection device |
JP2890538B2 (en) | 1989-10-24 | 1999-05-17 | ソニー株式会社 | Semiconductor device |
JP3591872B2 (en) * | 1993-06-10 | 2004-11-24 | キヤノン株式会社 | Semiconductor device |
JP3239976B2 (en) * | 1994-09-30 | 2001-12-17 | 株式会社東芝 | Alignment mark, method of manufacturing semiconductor device, and semiconductor device |
JP3693370B2 (en) * | 1994-10-18 | 2005-09-07 | 株式会社ルネサステクノロジ | Overlap accuracy measurement mark |
JP3617046B2 (en) | 1995-05-29 | 2005-02-02 | 株式会社ニコン | Exposure method |
JP3859764B2 (en) * | 1995-06-27 | 2006-12-20 | 株式会社ルネサステクノロジ | Overlay accuracy measurement mark, defect correction method for the mark, and photomask having the mark |
JPH09244222A (en) * | 1996-03-08 | 1997-09-19 | Mitsubishi Electric Corp | Reticle for measuring superposition error, method for measuring superposition error by using the reticle and mark for measuring superposition error |
JPH10189425A (en) | 1996-12-27 | 1998-07-21 | Matsushita Electron Corp | Alignment method, measuring method for accuracy of alignment and mark for alignment measurement |
JP4187808B2 (en) * | 1997-08-25 | 2008-11-26 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
JP3519579B2 (en) * | 1997-09-09 | 2004-04-19 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
US5869374A (en) * | 1998-04-22 | 1999-02-09 | Texas Instruments-Acer Incorporated | Method to form mosfet with an inverse T-shaped air-gap gate structure |
US6068954A (en) * | 1998-09-01 | 2000-05-30 | Micron Technology, Inc. | Semiconductor wafer alignment methods |
US6184104B1 (en) * | 1998-09-10 | 2001-02-06 | Chartered Semiconductor Manufacturing Ltd. | Alignment mark strategy for oxide CMP |
US6054721A (en) * | 1999-07-14 | 2000-04-25 | Advanced Micro Devices, Inc. | Detection of undesired connection between conductive structures within multiple layers on a semiconductor wafer |
-
1998
- 1998-03-27 JP JP10048398A patent/JP3211767B2/en not_active Expired - Fee Related
-
1999
- 1999-03-26 TW TW088104889A patent/TW442844B/en not_active IP Right Cessation
- 1999-03-26 KR KR1019990010560A patent/KR100306705B1/en not_active IP Right Cessation
- 1999-03-26 CN CN99103223A patent/CN1231501A/en active Pending
- 1999-03-29 US US09/281,111 patent/US6288452B1/en not_active Expired - Fee Related
-
2001
- 2001-06-21 US US09/886,705 patent/US6448147B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6876021B2 (en) | 2002-11-25 | 2005-04-05 | Texas Instruments Incorporated | Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier |
US20210063997A1 (en) * | 2019-08-30 | 2021-03-04 | Micron Technology, Inc. | Methods for aligning a physical layer to a pattern formed via multi-patterning, and associated systems |
US11003164B2 (en) * | 2019-08-30 | 2021-05-11 | Micron Technology, Inc. | Methods for aligning a physical layer to a pattern formed via multi-patterning, and associated systems |
Also Published As
Publication number | Publication date |
---|---|
US6448147B2 (en) | 2002-09-10 |
JP3211767B2 (en) | 2001-09-25 |
JPH11283915A (en) | 1999-10-15 |
US6288452B1 (en) | 2001-09-11 |
KR19990078314A (en) | 1999-10-25 |
CN1231501A (en) | 1999-10-13 |
KR100306705B1 (en) | 2001-09-26 |
TW442844B (en) | 2001-06-23 |
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