US20010041438A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- US20010041438A1 US20010041438A1 US09/908,607 US90860701A US2001041438A1 US 20010041438 A1 US20010041438 A1 US 20010041438A1 US 90860701 A US90860701 A US 90860701A US 2001041438 A1 US2001041438 A1 US 2001041438A1
- Authority
- US
- United States
- Prior art keywords
- insulating film
- semiconductor layer
- interlayer insulating
- gate electrode
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 456
- 238000004519 manufacturing process Methods 0.000 title claims description 59
- 239000012535 impurity Substances 0.000 claims abstract description 91
- 238000003860 storage Methods 0.000 claims abstract description 47
- 239000003990 capacitor Substances 0.000 claims abstract description 46
- 238000009792 diffusion process Methods 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims description 522
- 239000010408 film Substances 0.000 claims description 474
- 239000011229 interlayer Substances 0.000 claims description 249
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 146
- 239000000758 substrate Substances 0.000 claims description 104
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 88
- 229920005591 polysilicon Polymers 0.000 claims description 88
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 79
- 229910052710 silicon Inorganic materials 0.000 claims description 57
- 239000010703 silicon Substances 0.000 claims description 57
- 239000012071 phase Substances 0.000 claims description 25
- 230000000149 penetrating effect Effects 0.000 claims description 21
- 230000002093 peripheral effect Effects 0.000 claims description 19
- 239000010409 thin film Substances 0.000 claims description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 230000010363 phase shift Effects 0.000 claims description 11
- 239000011159 matrix material Substances 0.000 claims description 8
- 239000004973 liquid crystal related substance Substances 0.000 claims description 7
- 239000000969 carrier Substances 0.000 claims description 6
- 239000007790 solid phase Substances 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000003892 spreading Methods 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 86
- 238000000034 method Methods 0.000 description 72
- 229910052681 coesite Inorganic materials 0.000 description 67
- 229910052906 cristobalite Inorganic materials 0.000 description 67
- 239000000377 silicon dioxide Substances 0.000 description 67
- 229910052682 stishovite Inorganic materials 0.000 description 67
- 229910052905 tridymite Inorganic materials 0.000 description 67
- 229910021332 silicide Inorganic materials 0.000 description 51
- 230000008569 process Effects 0.000 description 34
- 238000005530 etching Methods 0.000 description 21
- 229910052581 Si3N4 Inorganic materials 0.000 description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 18
- 238000002513 implantation Methods 0.000 description 14
- 229910052782 aluminium Inorganic materials 0.000 description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 13
- 125000006850 spacer group Chemical group 0.000 description 13
- 230000009467 reduction Effects 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 208000022010 Lhermitte-Duclos disease Diseases 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 230000006872 improvement Effects 0.000 description 7
- 230000015654 memory Effects 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 238000010030 laminating Methods 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910010252 TiO3 Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000001788 irregular Effects 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 229910021341 titanium silicide Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
- H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
Definitions
- the present invention relates in general to a semiconductor device, and in particular to a semiconductor device utilizing a vertical surround gate MOSFET (will be referred to as a “V ⁇ T” hereinafter).
- the invention also relates to a method of manufacturing such a semiconductor device.
- the invention further relates to an improvement of V ⁇ T.
- FIG. 114 shows trend of cell sizes of dynamic random access memories (DRAMs).
- DRAMs dynamic random access memories
- FIG. 114 additionally shows design rules in respective generations.
- Conventional DRAM cells include, as components, bit lines (BL), word lines (WL), bit line contacts (BK), and storage contacts (SK). Therefore, the cell size, which is expressed with F (feature size) of the following formula, is 8F 2.
- F represents a gate width
- r represents a minimum line width
- ⁇ represents a process margin
- the design rule (minimum line width) is simply set to F, and 8F 2 and 4F 2 (hollow and solid circles) are plotted in a superimposed form.
- the cells of 8F 2 can form 256M-DRAM at the most.
- the cell size of 4F 2 can achieve a DRAM of G-bit generation by following the conventional reduction rule.
- the cells of 4F 2 can be formed by arranging vertical transistors at crossings of the bit lines BL and word lines Wl. Based on the above background, various kinds of vertical transistors have been proposed.
- FIG. 115 is a cross section of a first prior art, which is a vertical surround gate transistor disclosed in Japanese Patent Laying-Open No. 5-160408 (1993).
- a gate 3 is formed around a column 5 of silicon forming a channel with a gate insulating film 4 therebetween.
- a source 6 a and a drain 6 b are connected to silicon column 5 .
- FIG. 116 is a cross section of a semiconductor device showing a process of manufacturing the surround gate transistor shown in FIG. 115.
- Gate insulating film 4 is formed to cover silicon column 5 .
- polysilicon ( 3 ) is deposited to cover silicon column 5 with gate insulating film 4 therebetween.
- Anisotropic etching is effected on polysilicon ( 3 ) to form gate electrode 3 on a side wall of silicon column 5 .
- a gate length 1 depends on an anisotropic etching rate of polysilicon ( 3 ). Therefore, a variation v of the gate length 1 is large. According to this method, therefore, it is very difficult to obtain stably the cells of 4F 2 .
- FIGS. 117 and 118 are cross sections showing steps in a process of manufacturing a vertical surround gate transistor disclosed in Japanese Patent Laying-Open No. 4-282865 (1992).
- an SiO 2 layer 2 a , polysilicon, i.e., word line 3 and an SiO 2 layer 2 b are formed in this order on a bit line 26 .
- a contact hole 8 penetrating SiO 2 layer 2 b , polysilicon 3 and SiO 2 layer 2 a is also provided.
- Gate insulating film 4 is formed on the side wall of contact hole 8 .
- the side wall of contact hole 8 is covered with polysilicon 5 .
- Polysilicon 5 is divided into a source 6 a , a channel 7 and a drain 6 b .
- the transistor thus constructed has the following problem. Referring to FIG. 117, variation v of etching quantity is liable to occur when forming gate insulating film 4 , and in some cases, an upper corner 3 c of the gate electrode is exposed, resulting in leak between corner 3 c of the gate and drain 6 b.
- the transistor also has the following problem in connection with its operation.
- the conductivity types of the gate polysilicon and channel polysilicon are opposite to each other, and a difference in their work function is utilized for depleting the channel polysilicon, whereby the off state is achieved between the source and drain.
- a film thickness of the channel polysilicon must be smaller than the maximum width of the depletion layer which depends on concentration of impurity in the channel polysilicon.
- the resistance of source/drain is high, a sufficient on-current cannot be obtained. Therefore, it is necessary to increase the content of impurity in the channel polysilicon for lowering the resistance.
- the content of impurity in the source/drain is 10 20 /cm 3 at the most.
- the maximum width of depletion layer would be approximately 40 ⁇ . Therefore, due to restriction that the film thickness of the channel polysilicon must be smaller than the above value, it would probably be impossible to achieve stable manufacturing of the transistors without sacrificing characteristics.
- V ⁇ T vertical ⁇ -shaped transistor
- FIG. 119 is a perspective view showing a major portion of a V ⁇ T.
- FIG. 120 is a cross section of the V ⁇ T.
- a MOSFET includes a substrate 1 .
- Source region 6 a is formed at a main surface of substrate 1 .
- First interlayer insulating film 2 a is formed on substrate 1 .
- Gate electrode 3 which has a top surface substantially parallel to the surface of substrate, is formed on first interlayer insulating film 2 a .
- Second interlayer insulating film 2 b covering gate electrode 3 is formed on first interlayer insulating film 2 a .
- a surface of source region 6 a is partially exposed through a contact hole 19 which penetrates first interlayer insulating film 2 a , gate electrode 3 and second interlayer insulating film 2 b .
- Gate insulating film 4 covers the side wall of contact hole 19 .
- contact hole 19 there is formed a first semiconductor layer 20 of a P-type, which is in contact with a surface 9 of source region 6 a and extends from the surface of source region 6 a to the same level as a lower surface of gate electrode 3 .
- a channel semiconductor layer 7 which is in contact with a surface of first semiconductor layer 20 and extends from the surface of first semiconductor layer 20 to the same level as an upper surface of gate electrode 3 .
- a second semiconductor layer 5 of the P-type which is in contact with the surface of channel semiconductor layer 7 and forms drain region 6 b , is formed on channel semiconductor layer 7 .
- a third interlayer insulating film 2 c covering drain region 6 b is formed on the substrate.
- Third interlayer insulating film 2 c is provided with a connection hole 11 a exposing a portion of the surface of drain region 6 b .
- An aluminum electrode 10 a is connected to drain region 6 b through connection hole 11 a.
- FIGS. 119 and 120 can overcome the problems of the technique shown in FIGS. 115 and 117, it has such a problem that a capacitance of a bit line can not be reduced below a restricted extent.
- Another object of the invention is to provide a DRAM of a G-bit generation.
- Still another object of the invention is to provide a DRAM having a cell size of 4F 2 .
- Yet another object of the invention is to provide a method of manufacturing such a DRAM.
- Another object of the invention is to improve the V ⁇ T described above.
- an object of the invention to provide an AND circuit using a V ⁇ T.
- a further object of the invention to provide an OR circuit using a V ⁇ T.
- a further object of the invention to provide an inverter circuit using a V ⁇ T.
- a further object of the invention to provide a flip-flop using a V ⁇ T.
- a further object of the invention to provide a gain cell using a V ⁇ T.
- a further object of the invention to provide a matrix of a liquid crystal display using a V ⁇ T.
- a first aspect of the invention relates to a semiconductor device, in which a gate transistor is operable to store information in a capacitor formed of a storage node, which is arranged at a crossing between a bit line and a word line, a capacitor insulating film and a cell plate electrode.
- the semiconductor device includes a substrate on which a dielectric layer and a semiconductor layer are formed successively.
- a first impurity diffusion layer of a second conductivity type is disposed in the semiconductor layer.
- the first impurity diffusion layer contains impurity of the first conductivity type implanted thereinto, and forms one of source/drain regions and the bit line.
- a first interlayer insulating film covering the first impurity diffusion layer is disposed on the substrate.
- a gate electrode which also forms the word line and has upper and lower surfaces is disposed on the first interlayer insulating film.
- a second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film.
- a contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first impurity diffusion layer.
- a side wall of the contact hole is covered with a gate insulating film.
- a first semiconductor layer of the first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first impurity diffusion layer and extends from the surface of the first impurity diffusion layer to the substantially same level as the lower surface of the gate electrode.
- a channel semiconductor layer is formed in the contact hole.
- the channel semiconductor layer is in contact with the surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode.
- a second conductive layer of the first conductivity type is disposed on the channel semiconductor layer.
- the second conductive layer is in contact with a surface of the channel semiconductor layer, and forms the storage node and the other of the source/drain regions.
- a capacitor insulating film is disposed on the second conductive layer.
- a second aspect of the invention relates to a semiconductor device in which contact is to be made at a deep position.
- the device of this aspect includes a substrate on which a dielectric layer and a semiconductor layer are formed successively.
- a first impurity diffusion layer of a first conductivity type is disposed in the semiconductor layer.
- the first impurity diffusion layer forms a bit line and one of source/drain regions.
- a first interlayer insulating film covering the first impurity diffusion layer is disposed on the substrate.
- a gate electrode which also forms the word line and has upper and lower surfaces is disposed on the first interlayer insulating film.
- a second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film.
- a contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first impurity diffusion layer.
- a side wall of the contact hole is covered with a gate insulating film.
- a first semiconductor layer of the first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first impurity diffusion layer and extends from the surface of the first impurity diffusion layer to the substantially same level as the lower surface of the gate electrode.
- a second semiconductor layer of the same first conductivity type as the first semiconductor layer is formed in the contact hole.
- the second semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode.
- a third semiconductor layer of the first conductivity type is formed in the contact hole and is disposed on the second semiconductor layer.
- the third semiconductor layer is in contact with a surface of the second semiconductor layer.
- An interconnection is connected to the third semiconductor layer.
- a third aspect of the invention relates to a semiconductor device, in which a gate transistor is operable to store information in a capacitor formed of a storage node, which is arranged at a crossing between a bit line and a word line, a capacitor insulating film and a cell plate electrode.
- the device of this aspect includes a bit line having upper and lower surfaces.
- a first vertical ⁇ -shaped transistor is disposed on the upper surface of the bit line.
- a capacitor is connected to the first vertical ⁇ -shaped transistor.
- a second vertical ⁇ -shaped transistor is disposed on the lower surface of the bit line.
- a second capacitor is connected to the second vertical ⁇ -shaped transistor.
- a fourth aspect of the invention relates to a semiconductor device in which flow of a large number of carriers is controlled by a voltage applied to a gate.
- the semiconductor device of this aspect includes a substrate having a main surface.
- a first conductive layer of a first conductivity type forming one of source/drain regions is disposed at the main surface of the substrate.
- a first interlayer insulating film is disposed on the substrate.
- a gate electrode having upper and lower surfaces is disposed on the first interlayer insulating film.
- a second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film.
- a contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first conductive layer.
- a side wall of the contact hole is covered with a first gate insulating film.
- the semiconductor device further includes a silicon thin film which is in contact with the first conductive layer and continuously extends to cover an inner wall of the contact hole with the first gate insulating film therebetween.
- the silicon thin film has a concave portion, which located in the contact hole and has a bottom surface located at a level lower than the lower surface of the first gate electrode.
- the silicon thin film is formed of three portions which are a cylindrical channel portion surrounded by the first gate electrode as well as a source region and a drain region located at vertically opposite sides of the channel portion.
- the device further includes a silicon oxide film which is disposed in the concave portion of the silicon thin film and is located at a level lower than an upper end of the channel portion.
- the concave portion of the silicon thin film is filled with polysilicon which is in contact with the channel portion.
- the polysilicon is used as a lead electrode for fixing the potential of the channel portion.
- a fifth aspect of the invention relates to a semiconductor device in which flow of a large number of carriers is controlled by a voltage applied to a gate.
- the semiconductor device of this aspect includes a substrate having a main surface.
- a first conductive layer of a first conductivity type forming one of source/drain regions is disposed at the main surface of the substrate.
- a first interlayer insulating film is disposed on the substrate.
- a gate electrode is disposed on the first interlayer insulating film.
- a second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film.
- a contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first conductive layer.
- a side wall of the contact hole is covered with a conductive member.
- a surface of the conductive member is covered with a gate insulating film.
- a first semiconductor layer of the first conductivity type is disposed in the contact hole and is in contact with the surface of the first conductive layer.
- a channel semiconductor layer is disposed in the contact hole and is in contact with a surface of the first semiconductor layer.
- a second semiconductor layer of the first conductivity type forming the other of the source/drain regions is disposed in the contact hole and is in contact with a surface of the channel semiconductor layer.
- a sixth aspect of the invention relates to a semiconductor device including an OR circuit.
- the semiconductor device of this aspect includes a substrate having a main surface.
- a first conductive layer of a first conductivity type forming one of source/drain regions is disposed at the main surface of the substrate.
- a first interlayer insulating film is disposed on the substrate.
- a first gate electrode and a second gate electrode which adjoin to each other and each have an upper surface and a lower surface are disposed on the first interlayer insulating film.
- a second interlayer insulating film covering the first and second gate electrodes is disposed on the first interlayer insulating film.
- a contact hole which spreads over the first and second gate electrodes, and penetrates the first interlayer insulating film, the first and second gate electrodes and the second interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer.
- a side wall of the contact hole is covered with a gate insulating film.
- a first semiconductor layer of a first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the gate electrode.
- a channel semiconductor layer is formed in the contact hole.
- the channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from a surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode.
- a second semiconductor layer of the first conductivity type forming the other of the source/drain regions is disposed on the channel semiconductor layer and is in contact with the surface of the channel semiconductor layer.
- a seventh aspect of the invention relates to a semiconductor device including an AND circuit.
- the semiconductor device of this aspect includes a substrate, a first conductive layer of a first conductivity type disposed on the substrate, and a first interlayer insulating film disposed on the substrate and covering the first conductive layer.
- a first gate electrode having an upper surface and a lower surface is disposed on the first interlayer insulating film.
- a second interlayer insulating film covering the first gate electrode is disposed on the first interlayer insulating film.
- a second gate electrode having an upper surface and a lower surface is disposed on the second interlayer insulating film.
- a third interlayer insulating film covering the second gate electrode is disposed on the second interlayer insulating film.
- a contact hole which penetrates the first interlayer insulating film, the first gate electrode, the second interlayer insulating film, the second gate electrode and the third interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer. Side walls of the first and second gate electrodes exposed in the contact hole are covered with a gate insulating film.
- a first semiconductor layer of a first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with a surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the first gate electrode.
- a first channel semiconductor layer is formed in the contact hole.
- the first channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the first gate electrode.
- a second channel semiconductor layer of a second conductivity type is formed in the contact hole. The second channel semiconductor layer extends from the lower surface of the second gate electrode to the substantially same level as the upper surface of the second gate electrode.
- a second semiconductor layer of the first conductivity type forming the other of the source/drain regions is disposed on the second channel semiconductor layer and is in contact with a surface of the second channel semiconductor layer.
- An eighth aspect of the invention relates to a semiconductor device including an inverter circuit.
- the semiconductor device of this aspect includes a first n + conductive layer.
- a first interlayer insulating film is disposed on the n + -conductive layer.
- a first gate electrode having an upper surface and a lower surface is disposed on the first interlayer insulating film.
- a second interlayer insulating film covering the first gate electrode is disposed on the first interlayer insulating film.
- a first contact hole, which penetrates the first interlayer insulating film, the first gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first n + -conductive layer.
- a side wall of the first contact hole is covered with a first gate insulating film.
- a first n + semiconductor layer is formed in the first contact hole.
- the first n + -semiconductor layer is in contact with a surface of the first n + -conductive layer and extends from the surface of the first n + -conductive layer to the substantially same level as the lower surface of the first gate electrode.
- a p ⁇ -semiconductor layer is formed in the first contact hole. The p ⁇ -semiconductor layer is in contact with a surface of the first n + -semiconductor layer and extends from the surface of the first n + -semiconductor layer to the substantially same level as the upper surface of the first gate electrode.
- a second n ⁇ -semiconductor layer is formed in the first contact hole and is disposed on the p ⁇ -semiconductor layer.
- the second n + -semiconductor layer is in contact with a surface of the p ⁇ -semiconductor layer and forms the other of the source/drain regions.
- a second n + -conductive layer is disposed on the second interlayer insulating film and is in contact with the second n + -conductive layer.
- a first p + -conductive layer is disposed on the second n + -conductive layer.
- a third interlayer insulating film is disposed on the first p + -conductive layer.
- a second gate electrode is disposed on the third interlayer insulating film.
- a fourth interlayer insulating film covering the second gate electrode is disposed on the third interlayer insulating film.
- a second contact hole penetrating the fourth interlayer insulating film, the second gate electrode and the third interlayer insulating film is provided for exposing a portion of a surface of the first p + -conductive layer.
- a side wall of the second contact hole is covered with a second gate insulating film.
- a first p + -semiconductor layer is formed in the second contact hole. The first p semiconductor layer is in contact with a surface of the first p + -conductive layer and extends from the surface of the first p + -conductive layer to the substantially same level as the lower surface of the second gate electrode.
- n ⁇ -semiconductor layer is formed in the contact hole.
- the n ⁇ -semiconductor layer is in contact with the surface of the first p + -semiconductor layer and extends from the surface of the first p + -semiconductor layer to the substantially same level as the upper surface of the second gate electrode.
- a second p + -semiconductor layer forming the other of the source/drain regions is disposed in the contact hole.
- the second p + -semiconductor layer is disposed on the n ⁇ -semiconductor layer and is in contact with the surface of the n ⁇ -semiconductor layer.
- a second p + -conductive layer is disposed on the fourth interlayer insulating film and is in contact with the second p + -semiconductor layer.
- a ninth aspect of the invention relates to a semiconductor device including a flip-flop circuit.
- the semiconductor device of this aspect includes a substrate and a first conductive layer of a first conductivity type disposed on the substrate.
- a first interlayer insulating film covering the first conductive layer is disposed on the substrate.
- a first gate electrode of the first conductivity type having an upper surface and a lower surface is disposed on the first interlayer insulating film.
- a second interlayer insulating film covering the first gate electrode is disposed on the first interlayer insulating film.
- a first contact hole, which penetrates the first interlayer insulating film, the first gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer.
- a side wall of the first contact hole is covered with a first gate insulating film.
- a first semiconductor layer of a first conductivity type is formed in the first contact hole.
- the first semiconductor layer is in contact with the surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the first gate electrode.
- a first channel semiconductor layer of a second conductivity type is formed in the first contact hole.
- the first channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the first gate electrode.
- a second semiconductor layer of the first conductivity type forming the other of the source/drain regions is formed in the first contact hole.
- the second semiconductor layer is disposed on the first channel semiconductor layer and is in contact with the surface of the first channel semiconductor layer.
- a second gate electrode of the first conductivity type is disposed on the second interlayer insulating film and is in contact with the second semiconductor layer.
- a third interlayer insulating film covering the second gate electrode is disposed on the second interlayer insulating film.
- a second contact hole, which penetrates the third interlayer insulating film, the second gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first gate electrode.
- a side wall of the second contact hole is covered with a second gate insulating film.
- a third semiconductor layer of the first conductivity type is formed in the second contact hole.
- the third semiconductor layer is in contact with the surface of the first gate electrode and extends from the surface of the first gate electrode to the substantially same level as a lower surface of the second gate electrode.
- a second channel semiconductor layer of the second conductivity type is formed in the second contact hole.
- the second channel semiconductor layer is in contact with a surface of the third semiconductor layer and extends from the surface of the third semiconductor layer to the substantially same level as an upper surface of the second gate electrode.
- a fourth semiconductor layer of the first conductivity type forming the other of the source/drain regions is formed in the second contact hole.
- the fourth semiconductor layer is disposed on the second channel semiconductor layer and is in contact with the surface of the second channel semiconductor layer.
- a second conductive layer of the first conductivity type is disposed on the third interlayer insulating film and is connected to the fourth semiconductor layer.
- a tenth aspect of the invention relates to a semiconductor device including a gain cell.
- the semiconductor device of this aspect includes a substrate, and a first gate electrode of a second conductivity type disposed on the substrate. Source/drain regions of a first conductivity type are disposed at a main surface of the substrate and are located at opposite sides of the first gate electrode.
- a first interlayer insulating film covering the first gate electrode is disposed on the substrate.
- a second gate electrode is formed on the first interlayer insulating film.
- a second interlayer insulating film covering the second gate electrode is formed on the first interlayer insulating film.
- a contact hole, which penetrates the second gate electrode and the first interlayer insulating film, is provided for exposing a portion of a surface of the first gate electrode.
- a side wall of the contact hole is covered with a gate insulating film.
- a first semiconductor layer of a second conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first gate electrode and extends from the surface of the first gate electrode to the substantially same level as a lower surface of the second gate electrode.
- a channel semiconductor layer of the first conductivity type is formed in the contact hole. The first channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the second gate electrode.
- a third semiconductor layer of the second conductivity type forming the other of the source/drain regions is formed in the contact hole. The third semiconductor layer is disposed on the channel semiconductor layer and is in contact with the surface of the channel semiconductor layer.
- a conductive layer of the second conductivity type is formed on the second interlayer insulating film and is in contact with the third semiconductor layer.
- An eleventh aspect of the invention relates to a semiconductor device including a matrix of a liquid crystal display.
- the semiconductor device of this aspect includes a first conductive layer of a first conductivity type which is disposed on a substrate and forms one of source/drain regions.
- a first interlayer insulating film is disposed on the substrate.
- a gate electrode having an upper surface and a lower surface is disposed on the first interlayer insulating film.
- a second interlayer insulating film covering the gate electrode is formed on the first interlayer insulating film.
- a contact hole, which penetrates the first interlayer insulating film, the gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer.
- a side wall of the contact hole is covered with a gate insulating film.
- a first semiconductor layer of a first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the gate electrode.
- a channel semiconductor layer is formed in the contact hole. The channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode.
- a second semiconductor layer of the first conductivity type forming the other of the source/drain regions is formed in the contact hole. The second semiconductor layer is disposed on the channel semiconductor layer and is in contact with a surface of the channel semiconductor layer.
- a pixel electrode is connected to the second semiconductor layer.
- a twelfth aspect of the invention relates to a method of manufacturing a semiconductor device in which a gate transistor is operable to store information in a capacitor formed of a storage node, which is arranged at a crossing between a bit line and a word line, a capacitor insulating film and a cell plate electrode.
- the method includes the step of preparing a substrate on which a dielectric member and a semiconductor layer are formed successively.
- a first conductive layer containing impurity of a first conductivity type is formed at a surface of the semiconductor layer.
- the first conductive layer forms one of source/drain regions and also forms the bit line.
- a first interlayer insulating film is formed on the substrate.
- a gate electrode which forms the word line and has upper and lower surfaces, is formed on the first interlayer insulating film.
- a second interlayer insulating film is formed on the substrate to cover the gate electrode.
- a contact hole is formed. The contact hole penetrates the first interlayer insulating film, the gate electrode and the second interlayer insulating film, and reaches a surface of the first conductive layer. A side wall of the contact hole is covered with a gate insulating film.
- a second semiconductor layer is formed on the substrate. The second semiconductor layer is in contact with the surface of the first conductive layer, and fills the contact hole. Impurity of the first conductivity type is implanted into a surface of the second semiconductor layer.
- the impurity implanted into the surface of the second semiconductor layer is diffused into the second semiconductor layer, and the impurity contained in the first conductive layer is diffused from the first conductive layer into the second semiconductor layer, whereby a region, which forms the other of the source/drain regions and also forms the storage node, and a channel region, which is located between the other of the source/drain regions and the one of the source/drain regions, are formed at the second semiconductor layer.
- a capacitor insulating film is formed on the other of the source/drain regions.
- a cell plate is formed on the storage node with the capacitor insulating film therebetween.
- the semiconductor device of the first aspect of the invention since the semiconductor layer formed on the dielectric layer is used as the bit line, the capacitance of the bit line is reduced and a dynamic random access memory can operate at a high speed.
- bit line is commonly used by the upper and lower V ⁇ T-DRAMs, the bit line can be formed only by one step, so that the number of manufacturing steps and thus a manufacturing cost can be reduce.
- the semiconductor device of the fourth aspect of the invention since the polysilicon, which fills the concave portion of the silicon thin film and is in contact with the channel portion, is used as the lead electrode, the potential of the channel portion can be fixed.
- the semiconductor device of the fifth aspect of the invention since there is provided the conductive member covering the side wall of the contact hole, it is possible to form a V ⁇ T having a body of which a diameter is smaller than a minimum hole diameter attainable with a lithography technique. As a result, the body can be depleted completely.
- the circuit can be formed within a very small area.
- the semiconductor device of the seventh aspect of the invention including the AND circuit, since the V ⁇ T is used as a component of the AND circuit, the area occupied by the device can be small.
- the occupied area can be small.
- the occupied area can be small.
- the occupied area can be small.
- the occupied area can be small.
- the capacitance of the bit line can be reduced.
- FIG. 1 is a perspective view of a V ⁇ T of an embodiment 1 of the invention
- FIG. 2 is a cross section taken along line II-II in FIG. 1;
- FIG. 3 shows a layout of a cell array of a DRAM using V ⁇ Ts
- FIGS. 4 to 15 are cross sections showing 1st to 12th steps in a process of manufacturing the DRAM using the V ⁇ T of embodiment 1, respectively;
- FIG. 16 is an equivalent circuit diagram of a DRAM array of embodiment 1;
- FIG. 17 is a cross section of a major portion of a DRAM cell using V ⁇ Ts of an embodiment 2;
- FIG. 18 is a cross section of a major portion of a DRAM cell of an embodiment 3;
- FIG. 19 is a cross section of a major portion of a DRAM cell of an embodiment 4.
- FIG. 20 is a cross section of a major portion of another DRAM cell of embodiment 4.
- FIG. 21 is a cross section of a major portion of still another DRAM cell of embodiment 4.
- FIG. 22 is a perspective view of a major portion of a DRAM cell array of an embodiment 5;
- FIGS. 23 to 27 are cross sections of a semiconductor device at 1st to 5th steps in a process of manufacturing the DRAM cell array of embodiment 5, respectively;
- FIGS. 28 and 29 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing a semiconductor device of an embodiment 6, respectively;
- FIG. 30 is a cross section of a semiconductor device of an embodiment 7;
- FIG. 31 is a cross section of another semiconductor device of embodiment 7;
- FIGS. 32 and 33 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing a semiconductor device of an embodiment 8, respectively;
- FIG. 34 shows a process of manufacturing a semiconductor device of an embodiment 9
- FIGS. 35 and 36 are cross sections of the semiconductor device at 1st and 2nd steps in a process of manufacturing the semiconductor device of embodiment 9, respectively;
- FIG. 37 is a cross section of a semiconductor device of an embodiment 10;
- FIG. 38 is a cross section of another semiconductor device of embodiment 10;
- FIG. 39 is a cross section of a semiconductor device of an embodiment 11;
- FIG. 40 is a cross section of a semiconductor device of an embodiment 12;
- FIG. 41 shows purposes of embodiments 13 to 16
- FIG. 42 is a cross section of a semiconductor device of an embodiment 13;
- FIGS. 43 to 45 are cross sections of a semiconductor device at 1st to 3rd steps in a process of manufacturing the semiconductor device of an embodiment 14, respectively;
- FIGS. 46 and 47 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing the semiconductor device of an embodiment 15, respectively;
- FIG. 48 is a cross section of a semiconductor device of an embodiment 16;
- FIG. 49 is a cross section of another semiconductor device of embodiment 16;
- FIGS. 50 to 52 are cross sections of a semiconductor device at 1st to 3rd steps in a process of manufacturing the semiconductor device of an embodiment 17, respectively;
- FIG. 53 is another cross section of the semiconductor device at the 3rd step in a process of manufacturing the semiconductor device of embodiment 17;
- FIG. 54 is a plan of a photomask used in an embodiment 18A;
- FIG. 55 is a plan of a V ⁇ T-DRAIM cell of embodiment 18A;
- FIG. 56 is a plan of a photomask used in an embodiment 18B;
- FIG. 57 is a plan of contact holes of V ⁇ Ts of embodiment 18B;
- FIGS. 58 and 59 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing the semiconductor device of an embodiment 19, respectively;
- FIG. 60 is a cross section of a semiconductor device of an embodiment 20;
- FIG. 61 is a cross section of a semiconductor device of an embodiment 21;
- FIG. 62 is a cross section of a V ⁇ T-DRAM of an embodiment 22;
- FIG. 63 is a cross section of a V ⁇ T-DRAM of an embodiment 23;
- FIG. 64 shows a profile of impurity in a V ⁇ T channel plug taken along line C-C′ in FIG. 62;
- FIG. 65 shows a profile of impurity of a channel taken along line C-C′ in FIG. 62;
- FIG. 66 is a cross section of a semiconductor device of an embodiment 26;
- FIGS. 67 to 69 are cross sections of a semiconductor device at 1st to 3rd steps in a process of manufacturing the semiconductor device of an embodiment 27, respectively;
- FIGS. 70 and 71 are cross sections of a conventional semiconductor device
- FIGS. 72 to 74 are cross sections of the semiconductor device at 4th to 6th steps in a process of manufacturing the semiconductor device of embodiment 27, respectively;
- FIG. 75 is a cross section of a semiconductor device of an embodiment 28.
- FIG. 76 shows a layout of contact holes of V ⁇ Ts of an embodiment 29
- FIG. 77 shows a layout of bit lines and word lines of an embodiment 29
- FIG. 78 shows a layout of a peripheral circuitry in semiconductor device of an embodiment 30
- FIG. 79 shows a purpose of an embodiment 31
- FIG. 80 is a cross section of a semiconductor device of an embodiment 31;
- FIGS. 81 to 84 are cross sections of a semiconductor device at 1st to 4th steps in a process of manufacturing the semiconductor device of an embodiment 32;
- FIG. 85 is a cross section of a semiconductor device of an embodiment 33;
- FIG. 86 shows a problem of a transistor of a conventional SOI structure
- FIG. 87 shows a problem arising in the transistor of the conventional SOI structure
- FIG. 88 is a cross section of a semiconductor device of an embodiment 34;
- FIGS. 89 and 90 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing the semiconductor device of an embodiment 34, respectively;
- FIG. 91 is a cross section of a semiconductor device of an embodiment 35;
- FIGS. 92 to 95 are cross sections of a semiconductor device at 1st to 4th steps in a process of manufacturing the semiconductor device of an embodiment 36, respectively;
- FIG. 96 is a cross section of a semiconductor device of an embodiment 37;
- FIG. 97 is a plan of a 2-input OR circuit using V ⁇ Ts of an embodiment 38;
- FIG. 98 is a circuit diagram of the semiconductor device shown in FIG. 97;
- FIG. 99 is a plan of another semiconductor device of embodiment 38.
- FIG. 100 is a circuit diagram of a semiconductor device shown in FIG. 99;
- FIG. 101 is a cross section of a semiconductor device of an embodiment 39;
- FIG. 102 is a cross section of another semiconductor device of embodiment 39;
- FIG. 103 is a circuit diagram of an AND circuit shown in FIG. 101;
- FIG. 104 is a cross section of still another semiconductor device of embodiment 39;
- FIG. 105 is a cross section of a semiconductor device of an embodiment 40
- FIG. 106 is a cross section of a semiconductor device of an embodiment 41;
- FIG. 107 is a circuit diagram of the semiconductor device of embodiment 41.
- FIG. 108 is a circuit diagram of a flip-flop circuit of embodiment 41.
- FIG. 109 is a cross section of a gain cell of an embodiment 42;
- FIG. 110 is a circuit diagram of a circuit using the gain cell of embodiment 42;
- FIG. 111 shows the operation of the semiconductor device of embodiment 42
- FIG. 112 is a cross section of another semiconductor device of embodiment 40;
- FIG. 113 is a plan of a matrix of a liquid crystal display of an embodiment 43;
- FIG. 114 shows trend of DRAM cell sizes
- FIG. 115 is a cross section of a vertical surround gate transistor in the prior art
- FIG. 116 is a cross section showing a process of manufacturing a semiconductor device shown in FIG. 115;
- FIGS. 117 and 118 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing the vertical surround gate transistor in the prior art, respectively;
- FIG. 119 is a perspective view of a vertical ⁇ -shaped transistor already proposed by the inventors.
- FIG. 120 is a cross section of a semiconductor device shown in FIG. 119;
- FIGS. 121 to 126 are cross sections of a substrate at 1st to 6th steps in a process of manufacturing a photomask shown in FIG. 56, respectively;
- FIG. 127 shows another process of manufacturing the photomask shown in FIG. 56;
- FIG. 128 is a cross section of a semiconductor device for showing a problem in another process of manufacturing the semiconductor device including a peripheral circuitry formed of SOI transistors;
- FIG. 129 is a cross section of a semiconductor device showing another improved process of manufacturing the semiconductor device including a peripheral circuitry formed of SOI transistors.
- FIG. 1 is a perspective view of a surround gate transistor (which will be referred to as a “vertical ⁇ -shaped transistor”, and will be also referred to simply as a “V ⁇ T”, hereinafter) of an embodiment 1.
- FIG. 2 is a cross section taken along line II-II in FIG. 1.
- FIG. 3 shows a layout of a cell array of a DRAM using V ⁇ Ts.
- a gate transistor is operable to store information in a capacitor which is disposed at a crossing of a bit line 24 and a word line 25 and is formed of a storage node 26 , a capacitor insulating film 21 and a cell plate electrode 22 .
- a substrate 1 of silicon there is disposed a buried SiO 2 layer (dielectric layer) 201 .
- a first impurity diffusion layer 24 of a first conductivity type which contains impurity of the first conductivity type implanted thereinto and forms one of source/drain regions as well as the bit line.
- First impurity diffusion layer 24 is covered with a first interlayer insulating film 8 disposed on buried SiO 2 layer 201 .
- first interlayer insulating film 8 there is formed a gate electrode 3 which has upper and lower surfaces and also forms the word line.
- Gate electrode 3 is covered with a second interlayer insulating film 9 disposed on first interlayer insulating film 8 .
- Contact holes 10 each of which penetrates first interlayer insulating film 8 , gate electrode 3 and second interlayer insulating film 9 , are provided for exposing portions of a surface of first impurity diffusion layer 24 .
- Side walls of contact holes 10 are covered with gate insulating films 4 .
- each contact hole 10 there is formed a first semiconductor layer 11 of the first conductivity type, which is in contact with the surface of first impurity diffusion layer 24 and extends from the surface of first impurity diffusion layer 24 to the substantially same level as the lower surface of gate electrode 3 .
- a channel semiconductor layer 12 which is in contact with the surface of first semiconductor layer 11 and extends from the surface of first semiconductor layer 11 to the substantially same level as the upper surface of gate electrode 3 .
- a second conductive layer 13 of the first conductivity type which is in contact with the surface of channel semiconductor layer 12 and forms the other of source/drain regions as well as storage node 26 .
- second conductive layer 13 is covered with a capacitor insulating film 21 formed on second interlayer insulating film 9 .
- a cell plate electrode 22 which covers second conductive layer 13 , i.e., storage node 26 with the capacitor insulating film 21 therebetween.
- bit line ( 24 ) is formed on a thick insulating film ( 201 ), and thus the capacitance of bit line can be small. As a result, the DRAM performing high-speed operation is obtained.
- bit line capacitance Since the bit line capacitance is small, the capacitance of storage node can be small. More specifically, a sense amplifier has sensitivity of a fixed value. Therefore, if a ratio of C S (capacitance of storage node) to C 3 (capacitance of bit line) is constant, information can be read. Therefore, if C 3 is reduced, C S can be reduced.
- bit line capacitance is small, the open bit line system shown in an equivalent circuit diagram of FIG. 16 is allowed, and thus cells of 4F 2 can be easily obtained.
- a leak current does not flow between adjacent bit lines 24 . Owing to the fact that the leak current does not flow between the bit lines, it is possible to increase a time period between refreshing operations (rewriting operations).
- the DRAM can have a higher resistance against soft error as compared with the structure using the ordinary silicon substrate.
- V ⁇ T structure of transistor can provide the following advantages.
- a radius of channel semiconductor layer 12 allows depletion of the entire channel. Depletion of the entire channel can suppress a sub-threshold current (leak current at a weakly inverted state), resulting in improvement of circuit characteristics. Also, a sub-threshold coefficient S has a minimum value of 60 mV/dec.
- channel semiconductor layer 12 is surrounded by an electric field applied thereto, punch-through can be suppressed.
- the structure Owing to suppression of the punch-through, the structure has a high resistance against disturb refresh. Since there is no substrate bias effect, high-speed operation is allowed. Since the channel width can be wide, a large current can flow therethrough.
- Channel semiconductor layer 12 can be monocrystallized by the epitaxial growth method. According to the process described above, since the word line is formed, and the contact holes are formed in the word line, the word line can be formed easily. Connection can be made easily between the transistor and the bit line and between the transistor and the capacitor.
- the film thickness of the word line equals the gate length, the gate length can be controlled easily. Since a length of offset of the source depends on the film thickness of first interlayer insulating film 8 , and a length of offset of the drain depends on the film thickness of second interlayer insulating film 9 , these lengths can be controlled easily.
- Impurity of source/drain can be implanted by a simple ion-implanting process. Likewise, ion implantation for the channel can be performed easily. Since the gate insulating film is formed by oxidation, the gate insulating film does not have a thin portion at the edge of gate. Thus, the leak current does not generate at the edge of gate.
- an SOI (Silicon On Insulator) substrate 90 in which buried SiO 2 layer 201 is formed on silicon substrate 1 , and an SOI layer 202 is formed on buried SiO 2 layer 201 .
- SOI substrate 90 is formed by an appropriate method such as an SIMOX (Separation by Implanted Oxygen) method, ZMR method (Zone Melting Recrystallization) method, laser anneal method or laminating method.
- the SOI substrate may be replaced with a substrate such as an SOS (Silicon On Sapphire) which is separated by another dielectric member.
- the SOI substrate may be replaced with a poly-SOI substrate.
- Buried SiO 2 layer 201 has a film thickness of 5000 ⁇ , and SOI layer 202 has a film thickness of 2000 521 . Since SOI layer 202 forms the bit line, impurity 91 is implanted thereinto to reduce its resistance as shown in FIG. 4. If the V ⁇ T is, for example, to be of the P-channel type, the P-type impurity is implanted into SOI layer 202 .
- SiN layer 14 of 1000 ⁇ in thickness is deposited on SOI layer 202 .
- the purpose of SiN layer 14 is to prevent oxidation of the bottom of contact hole at the step of forming the gate insulating film of V ⁇ T.
- SOI layer 202 is patterned to have the configuration of bit lines 24 .
- step of implanting impurity shown in FIG. 4 the step of depositing SiN layer shown in FIG. 5 and the step of patterning bit lines shown in FIG. 6 may be carried out in the different orders described below.
- SiN layer 14 having a higher dielectric constant than SiO 2 is formed between adjacent bit lines 24 , so that a capacitance between the bit lines increases. Therefore, SiN layer 14 must have a small film thickness of about 500 ⁇ .
- first interlayer insulating film 8 of 1000 ⁇ in thickness is deposited on buried SiO 2 layer 201 to cover bit lines 24 .
- Polysilicon of 3000 ⁇ in thickness is deposited on first interlayer insulating film 8 , and then is patterned to form word lines 25 . More specifically, word lines 25 are formed by patterning the polysilicon containing impurity implanted thereinto in order to reduce the resistance.
- the polysilicon containing impurity may be doped polysilicon. Alternatively, impurity may be implanted into non-doped polysilicon.
- FIG. 9 is a cross section showing the semiconductor device at the same step as FIG. 8 and taken along line parallel to the bit line, i.e., taken along line B-B in FIG. 3.
- the film thickness of word line 25 equals the gate length of V ⁇ T. Since the film thickness of word line 25 can be controlled easily, good controllability of the gate length can be achieved.
- second interlayer insulating film 9 is formed on first interlayer insulating film 8 to cover word lines 25 .
- contact holes 10 penetrating second interlayer insulating film 9 , word lines 25 and first interlayer insulating film 8 are formed at crossings of word lines 25 and bit lines 24 .
- oxidation is effected on the side wall of word line 25 exposed in each contact hole 10 to form gate insulating film 4 of V ⁇ T. Since gate insulating film 4 is formed by oxidation, the gate insulating film 4 is thinned at the upper end of gate electrode ( 25 ).
- SiN layer 14 at the bottom of each contact hole 10 is removed by heat phosphoric acid to expose a surface 24 a of bit line 24 .
- contact holes 10 are filled with amorphous silicon 15 .
- Amorphous silicon 15 is epitaxially grown from the surface of bit lines 24 .
- Monocrystal silicon 92 obtained by this epitaxial growth forms the channel of V ⁇ T. Since surface 24 a of bit line 24 serves as a contact to the bit line, contact can be made very easily between the transistor and bit line 24 .
- ion implantation is performed to form the drain and channel of V ⁇ T. Thereafter, the implanted ion diffuses owing to heat treatment during the process, so that source 6 a and drain 6 b are formed. Since impurity is introduced into source 6 a , drain 6 b and channel 12 by the implantation method, concentration of impurity in these portions can be controlled easily. By controlling the film thicknesses of first interlayer insulating film 8 and second interlayer insulating film 9 , the lengths of offset portions 204 a and 204 b can be controlled easily.
- the drain portion of V ⁇ T is patterned to produce storage node 26 .
- Capacitor insulating film 21 is formed on second interlayer insulating film 9 to cover storage node 26 .
- Cell plate electrode 22 is formed on second interlayer insulating film 9 to cover storage node 26 with capacitor insulating film 21 therebetween. In this manner, the DRAM cells using V ⁇ Ts are completed.
- drain 6 b of V ⁇ T also serves as storage node 26 , the transistor and capacitor can be connected very easily.
- the DRAM cells of 4F 2 are obtained as described above.
- Embodiments 2 to 6 which will described below relate to a method for reducing a resistance of the word line.
- Embodiments 7 to 12 relate to a method which reduces the resistance of bit line for enabling high-speed operation of the V ⁇ T-DRAM.
- the word line is made of doped polysilicon
- the bit line is made of the SOI layer. Therefore, if a plurality of V ⁇ Ts are continuously disposed, the word line and bit line have a high resistance. As can be seen from FIG. 3, the width of word line 25 is reduced at portions containing V ⁇ Ts, which further increases the resistance. The high resistance of the word line and bit line reduces the operation speed of DRAM.
- Embodiments 2 to 12 have been developed to overcome the above problem.
- FIG. 17 is a cross section of a major portion of a DRAM cell using V ⁇ T of embodiment 2.
- the DRAM cell of embodiment 2 is the substantially same as the DRAM cell shown in FIG. 2 except for the following points. Therefore, portions equal or corresponding to those in the DRAM cell in FIG. 2 are not shown in the figure. Also, the same or corresponding portions bear the same reference numbers, and will not be described below.
- the word line 25 has a two-layer structure formed of a polysilicon 16 and a silicide 17 disposed on polysilicon 16 .
- the two-layer structure formed of polysilicon 16 and silicide 17 can reduce the resistance of word line 25 , and thus enables the high-speed operation of DRAM.
- Material silicide may be tungsten silicide, titanium silicide, cobalt silicide, platinum silicide, molybdenum silicide or others, and alternatively, material other than silicide may be used provided that it has a similar resistivity.
- FIG. 18 is a cross section of a major portion of a DRAM cell of embodiment 3.
- the DRAM cell of this embodiment differs from the DRAM cell shown in FIG. 17 in that silicide 17 is formed under polysilicon 16 .
- word line 25 since word line 25 has the two-layer structure formed of the polysilicon and silicide, the word line 25 has a low resistance.
- FIG. 19 is a cross section of a major portion of a DRAM cell of the embodiment 4.
- silicide 17 is disposed above and below polysilicon 16 . This structure can further reduce the resistance of word line 25 .
- a threshold voltage V th of a structure including a gate made of metal or silicide is higher than that of a structure including a gate made of polysilicon by the reason related to a work function.
- word line 25 has the layered structure including silicide 17 and polysilicon 16 , the threshold voltage V th of V ⁇ T can be changed locally.
- the channel portion 7 surrounded by silicide 17 has a higher threshold voltage V th than channel portion 7 surrounded by polysilicon 25 , and thus is resistive to inversion. Therefore, punch-through between source 6 a and drain 6 b is advantageously suppressed even if the drain voltage increases.
- word line 25 can have a small resistance at the p-channel 7 , and can effectively prevent the punch-through, if it includes silicide 17 disposed between upper and lower layers of polysilicon 16 .
- FIG. 22 is a perspective view of a major portion of a DRAM cell array of embodiment 5, and specifically shows the structure at a step corresponding to that in FIGS. 8 and 9. Members and portions other than word lines 25 and bit lines 24 are not shown in FIG. 22 for simplicity reason.
- silicide 17 is disposed not only on the upper surface of polysilicon 16 but also on the side surfaces thereof. Thus, three sides of word line 25 are covered with silicide 17 , so that the resistance of word line 25 is further reduced.
- word lines 25 are formed on first interlayer insulating film 8 .
- a sputtering method is performed to cover the surfaces of word lines 25 with a titanium film 19 of 200 ⁇ in thickness.
- Lamp annealing is performed in the atmosphere of N 2 at a temperature of 600 to 700° C. for 30 seconds.
- titanium silicide films 19 a which are compound of titanium and silicon, are produced only on portions of silicon which were in contact with titanium.
- unreacted titanium film 19 is removed.
- titanium has been described as an example.
- other material such as cobalt, platinum or nickel may be used.
- the manner of forming the silicide only on exposed portions of silicon has been referred to as “salicide”.
- FIG. 27 is a cross section showing V ⁇ Ts in which contact holes are formed in word lines 25 covered with titanium silicide films 19 a .
- a margin M between the word line and the contact hole of V ⁇ T can be expressed by the following formula.
- M overlap margin of photolithography+silicide film thickness (t 1 )+film thickness (t 2 ) of portion to be oxidized
- This embodiment 6 relates to a method of forming silicide only on side walls of the word line.
- SiO 2 layer 20 is formed on each word line 25 .
- silicide films 17 are formed on the side walls of word line 25 . Since silicide films 17 are formed at the opposite side walls of word line 25 , the resistance of word line 25 can be reduced.
- the silicide film does not exist on the top surface of word line 25 . Therefore, it is not necessary to perform the etching for piercing the silicide film, which improves the stability of the process.
- Embodiments 7 to 12 are aimed at reduction of the resistance of bit lines and thus increase of the operation speed of V ⁇ T-DRAM.
- FIG. 30 is a cross section showing an SOI layer 30 (BL), silicide 31 and an SiN layer 32 , where are layered in this order and are patterned to have configurations of the bit lines. Implantation of impurity into SOI layer 30 may be carried out at any step as already described in connection with embodiment 1.
- SiN layer 32 may be deposited after patterning SOI layer 30 and silicide 31 , in which case the device has a section shown in FIG. 31.
- FIGS. 30 and 31 correspond to FIGS. 6 and 7 showing embodiment 1, respectively.
- the structure has a section shown in FIG. 32 after the steps of forming the contact holes of V ⁇ Ts, forming gate insulating films 4 by oxidation and then removing the SiN film provided for preventing oxidation of the bit lines.
- the channel of V ⁇ T will not be monocrystallized even if one performs solid phase growth of amorphous silicon filling contact hole 10 in the structure shown in FIG. 32.
- Embodiment 8 described below is an improvement of the above structure.
- etching is effected on silicide 31 at the bottom of contact hole 10 of V ⁇ T. Etching of silicide 31 exposes surface 30 a of SOI layer 30 , so that the channel of V ⁇ T can be monocrystallized by the epitaxial growth.
- This embodiment relates to a structure in which silicide is disposed under the bit line so as to reduce the resistance of bit line.
- silicide 17 is formed on SiO 2 layer 20 .
- Polysilicon 16 which will form bit lines, is formed on silicide 17 .
- This structure reduces the resistance of bit line.
- the channel of V ⁇ T cannot be monocrystallized by the epitaxial growth if V ⁇ T is formed on polysilicon 16 because the bit line is made of polysilicon.
- a laminating method enable formation of the bit line which is provided by disposing monocrystal silicon on silicide.
- a second silicon substrate 34 is laminated to a first silicon substrate 33 on which silicide 17 and SiO 2 layer 201 are formed.
- the laminating is performed by a high temperature heat treatment causing adhesion of them.
- the second silicon substrate 34 is a mere support substrate, so that its material is not significantly restricted.
- first silicon substrate 33 is polished by a chemical mechanical polishing (CMP) method to reduce the thickness.
- CMP chemical mechanical polishing
- bit line is formed on monocrystal silicon layer 30 , so that bit line includes layers of silicide 17 at upper and lower sides of monocrystal silicon layer 30 and thus has a further reduced resistance.
- polysilicon 94 may be interposed between silicide 17 and SiO 2 layer 20 , in which case the bit line can include polysilicon 30 located under silicide 17 as well as monocrystal silicon layer 33 located on silicide 17 . This structure can also reduce the resistance of bit line.
- This embodiment is likewise aimed at reduction of the resistance of bit line.
- bit line processing is effected on SOI layer 30 , which will form the bit line, after patterning the same.
- upper and opposite side (right and left) surfaces of bit line ( 30 ) is covered with silicide 17 . Since the three surfaces of bit line ( 30 ) is covered with silicide 17 , the resistance of bit line can be further reduced.
- This embodiment may be combined with embodiment 9 employing the laminating method, so that four surfaces, i.e., upper, lower and opposite side surfaces of the bit line can be covered with silicide.
- This embodiment is aimed at reduction of the resistance of bit line.
- a film 35 for preventing silicidation is disposed on SOI layer 30 , i.e., bit line.
- silicide 17 can be formed only on the side surfaces of SOI layer 30 , i.e., bit line.
- a resistance of bit line in this structure is higher than that of the structure shown in FIG. 39, the resistance of bit line in this structure can be sufficiently low because the bit line is provided at its opposite sides with silicide.
- Film 35 for preventing silicidation may be an oxide film, and also may be a nitride film formed on the SOI layer similarly to that used in embodiment 1.
- the latter structure eliminates the step of forming a hole in the silicide similarly to embodiment 8 .
- a V ⁇ T-DRAM including bit lines of a low resistance can be obtained only by adding the step of silicidation to those in embodiment 1.
- Embodiments 13 to 16 which will be described below, are aimed at reduction of a capacitance of the bit line.
- the embodiment 13 is aimed at reduction of the capacitance of bit line for attaining high-speed operation of V ⁇ T-DRAM.
- bit line capacitance of V ⁇ T-DRAM is nearly equal to a sum of a capacitance 361 between bit line and silicon substrate, a capacitance 371 between bit line and bit line, and a capacitance 381 between bit line and word line.
- buried SiO 2 layer 20 is located under bit lines 24 , i.e., SOI layer, so that capacitance 36 between bit line 24 and substrate 1 is very small.
- bit lines 24 i.e., SOI layer
- the film thickness of buried SiO 2 layer 20 cannot be determined freely due to the manufacturing method.
- the film thickness of buried SiO 2 layer 20 is about 4000 ⁇ .
- the SOI substrate of the laminated structure is used, the film thickness of the buried SiO 2 layer can be determined freely. Referring to FIG.
- V ⁇ T-DRAM includes the SOI substrate having buried SiO 2 layer 20 of 0.5 ⁇ m or more in thickness, in which case capacitance 36 between bit line 24 and substrate 1 is sufficiently small, so that the operation speed of V ⁇ T-DRAM can be increased further.
- This embodiment is aimed at reduction of the capacitance between bit line and word line.
- a portion 25 a of word line 25 is located in a groove between adjacent bit lines 24 , so that capacitance 38 between word line 25 and bit line 24 is large.
- FIGS. 43 to 45 relate to an improved method of manufacturing a V ⁇ T-DRAM which can reduce the capacitance between bit line and word line.
- grooves 36 are formed at the surface of buried SiO 2 layer 20 .
- a polysilicon layer 37 filling grooves 36 is formed on buried SiO 2 layer 20 .
- etch-back is effected on polysilicon layer 37 to form bit lines 24 filling grooves 36 .
- word lines 25 having flat lower surfaces 25 b are formed, whereby capacitance 38 between bit line 24 and word line 25 can be reduced.
- This embodiment is likewise aimed at reduction of the capacitance between bit line and word line.
- bit lines 24 are formed on buried SiO 2 layer 20 .
- Interlayer SiO 2 film 38 is deposited on buried SiO 2 layer 20 to cover bit lines 24 .
- Interlayer SiO 2 film 38 is etched back to attain an intended height, and V ⁇ T-DRAM is formed on interlayer SiO 2 film 38 as shown in FIG. 37. Since spaces between bit lines 24 are filled with interlayer SiO 2 film 38 , V ⁇ T-DRAM have a small capacitance between bit line 24 and word line 25 . If bit line 24 in this structure is made of monocrystal, the channel 7 of V ⁇ T is made of monocrystal.
- This embodiment is likewise aimed at reduction of capacitance between bit line and word line.
- FIG. 48 is a cross section of a V ⁇ T-DRAM of embodiment 16.
- this embodiment includes bit lines 24 which are isolated from each other by LOCOS oxide films 391 . Since word line 25 is further isolated from bit line 24 by LOCOS oxide film 391 , capacitance 38 between bit line 24 and word line 25 can be reduced.
- Bit lines 24 isolated by LOCOS oxide films 391 can be formed by the following steps. LOCOS oxide films 391 are formed by oxidizing the surface of SOI layer ( 24 ) with a mask formed of a silicon nitride film (not shown) which is patterned into a predetermined configuration. Then, impurity is implanted through the silicon nitride film to form bit lines 24 . The silicon nitride film used in the LOCOS step will be used again in the step of forming the V ⁇ T gate insulating film by oxidation.
- This embodiment relates to a margin between bit line and V ⁇ T contact as well as a margin between word line and V ⁇ T contact.
- bit line 24 is formed on buried SiO 2 layer 20 .
- First interlayer insulating film 8 is formed on buried SiO 2 layer to cover bit line 24 .
- Word line 25 is formed on first interlayer insulating film 8 .
- Second interlayer insulating film 9 is formed on first interlayer insulating film 8 to cover word line 25 .
- An opening 9 a is formed at a position in second interlayer insulating film 9 , where the contact hole of V ⁇ T is to be formed.
- FIG. 50 shows a structure in which an edge 24 a of bit line 24 is coincident with an edge ( 9 a ) of the contact hole of V ⁇ T, they may be slightly shifted from each other due to shift of a mask. However, this shift causes no problem as will be described below.
- bit line 24 having a width of 0.2 ⁇ m which corresponds to the minimum allowable line width.
- an SiO 2 film 42 of 500 ⁇ in thickness is deposited such that it uniformly covers opening 9 a in second interlayer insulating film 9 . Dry etching is effected on SiO 2 film 42 to leave an SiO 2 film 43 in a side wall form as indicated by dotted line.
- FIG. 52 shows a section of contact hole 10 thus formed taken along line parallel to the word line
- FIG. 53 shows a section of the same taken along line parallel to the bit line.
- a margin m 1 between V ⁇ T contact and bit line can be ensured within the minimum line width w.
- a margin m 2 between V ⁇ T contact and word line can be ensured within the minimum line width w.
- the cell size of 4F 2 can be further reduced to 4r 2 .
- This method can further reduce the diameter of channel of V ⁇ T, and thus can produce the V ⁇ -DRAM which operate stably at a high speed and occupies a small area.
- This embodiment relates to a method of producing a V ⁇ T-DRAM having a cell size of 4r 2 .
- FIG. 54 is a plan of a photomask used for forming bit lines or word lines with a phase-shift mask.
- hatched portions 95 represent portions or shifters at which a phase of light shifts by 180°.
- a phase shift of light is 0° at portions 96 between adjacent hatched portions 95 .
- a width W 3 of the shifter and a width W 4 between the shifters each are double the minimum line width.
- FIG. 54 shows intensity of light, which is irradiated to the above photomask, on a wafer surface.
- an exposure time can be appropriately adjusted to form a wide bit line (BL) and a narrow space S defined between bit lines BL within a width (W 5 ) of double the minimum line width.
- the word lines may be formed in a similar manner, whereby contact holes of V ⁇ Ts of the minimum line width (minimum size) can be formed at the crossings of word lines and bit lines, and thus V ⁇ T-DRAM of the cell size of 4r 2 can be formed.
- FIG. 56 is a plan showing a photomask used in this embodiment.
- the photomask consists of 0°-phase shifters, 90°-phase shifters, 180°-phase shifters and 270°-phase shifters. 0°, 90°, 180° and 270° represent phases of light shifted by the phase shifters. Since the intensity of light is 0 at a position where the light beams applied from the four kinds of shifters overlap each other. Therefore, small openings are formed only at vicinities of the crossings of boundaries between the shifters.
- contact holes 10 can have a size smaller than the minimum size as shown in FIG. 57.
- m 2 represents a process margin.
- first SiN film 90 a , first SiO 2 film 90 b , second SiN film 90 c , second SiO 2 film 90 d , third SiN film 90 e , third SiO 2 film 90 f and fourth SiN film 90 g are deposited on a crystal substrate 90 in this order.
- a sum of film thicknesses of the SiN films and SiO 2 films are determined to correspond to the phase of light of 90°.
- a resist 90 h is formed on fourth SiN film 90 g .
- Resist 90 h is patterned to form openings 90 i only at portions at which phase shifts of 0°, 90° and 180° are to be set.
- the shifters of 0°, 90°, 180° and 270° are shown as if they are aligned laterally for sake of illustration, the shifters are actually disposed in a matrix form as shown in FIG. 56.
- fourth SiN film 90 g and third SiO 2 film 90 f are etched using resist 90 h as a mask.
- third SiN film 90 e serves as an etching stopper. Therefore, the etching is effected through a constant thickness. After the etching, resist 90 h is removed.
- a resist 90 j is formed on crystal substrate 90 . Openings 90 k are formed only at portions in resist 90 j where phase shifts of 0° and 90° are to be set.
- third SiN film 90 e and second SiO 2 film 90 d are etched with a mask formed of resist 90 j .
- second SiN film 90 c serves as an etching stopper. After the etching, resist 90 j is removed.
- a resist 901 is formed on crystal substrate 90 .
- Resist pattern 901 is patterned so that openings 90 m may be formed only at portions in resist 901 where phase shift of 0° is to be set.
- second SiN film 90 c and first SiO 2 film 90 b are etched with a mask formed of resist 901 .
- first SiN film 90 c serves as an etching stopper. After the etching, resist 90 is removed, whereby the photomask is completed.
- first SiN film 90 a Except for first SiN film 90 a , nothing exists at the portion of the phase shift of 0° on crystal substrate 90 .
- First SiN film 90 a , first SiO 2 film 90 b and second SiN film 90 c exist on the portions of the phase shift of 90°, and the sum of thicknesses of these films corresponds to the phase shift of light equal to 90°.
- the light beams passed through the portions of phase of 90° have the phase difference of 90° with respect to the portion of the phase of 0°.
- the light beams passed through the portions of phases of 180° and 270° have the phase differences of 180° and 270° with respect to the portion of the phase of 0°, respectively.
- the photomask shown in FIG. 56 may be obtained also by a method in which the surface of crystal substrate 90 is shaved by amounts corresponding to respective phase differences by FIB.
- Embodiments 19 to 21 which will be described below are aimed at improvement of the voltage resistance of gate of V ⁇ T.
- Embodiment 19 is aimed at improvement of the voltage resistance of gate of V ⁇ T.
- FIG. 58 is a cross section of the device at a stage after formation of contact hole 10 which penetrates second interlayer insulating film (SiO 2 ) 9 , word line (WL) 3 and first interlayer insulating film (SiO 2 ) film 8 and is provided for exposing the surface of bit line (BL).
- bit line On the surface of bit line (BL), there is formed a silicon nitride film (SiN) for preventing oxidation of the surface of bit line.
- gate insulating film 4 is formed by a dry O 2 oxidation method at 1100° C., whereby word line (WL) can have a round edge 45 .
- the round shape of edge 45 of word line (WL) can suppress concentration of electric field at edge 45 , and thus can improve the voltage resistance of the gate.
- This embodiment is likewise aimed at improvement of the voltage resistance of the gate of V ⁇ T.
- FIG. 60 shows this embodiment.
- Bit line (BL) is formed on buried SiO 2 layer 20 .
- the silicon nitride film (SiN) is formed on bit line (BL).
- First interlayer insulating film (SiO 2 ) 8 is formed on buried SiO 2 layer 20 to cover bit line (BL).
- Word line (WL) made of doped polysilicon is disposed on first interlayer insulating film 8 .
- Second interlayer insulating film 9 is formed on first interlayer insulating film 8 to cover word line (WL).
- Contact hole 10 penetrates second interlayer insulating film 9 , word line (WL) and first interlayer insulating film 8 .
- gate insulating film 4 Side surfaces of word line (WL) made of doped polysilicon are oxidized to form gate insulating film 4 .
- the doped polysilicon is made of fine or small grains, irregularities are formed on the surface of gate insulating film 4 in accordance with the face orientation of grains of doped polysilicon, resulting in reduction of the voltage resistance of gate.
- doped amorphous silicon is deposited for depositing the film of word line (WL).
- anneal is effected at about 600° to grow this doped amorphous polysilicon by solid phase growth into polysilicon formed of grains of a large diameter.
- gate insulating film 4 having a high voltage resistance can be formed without irregularities.
- a film for the word line is deposited in the form of doped amorphous silicon. Then, the contact hole of V ⁇ T is formed while maintaining the form of amorphous silicon. Thereafter, solid phase growth of the amorphous silicon is performed simultaneously with oxidation of gate insulating film.
- the device including the gate insulating film which is formed in this manner can achieve an effect similarly to embodiment 20 , and has the same structure as that shown in FIG. 61.
- Embodiments 22 to 25 are aimed at further improvement of the voltage resistance against punch-through of V ⁇ T for achieving a V ⁇ T-DRAM which is further resistive to the disturb refresh.
- FIG. 62 is a cross section of a V ⁇ T-DRAM of embodiment 22. If a voltage has been applied to bit line 24 or storage node 26 has stored electric charges, a depletion layer extends from the source or drain of V ⁇ T. The state where the depletion layer connects the source and drain together is the punch-through state. Assuming that a voltage V R is applied to the drain and the impurity concentration of channel is N A the extension X dmax of the depletion layer can be expressed by the following formula.
- K S represents a relative dielectric constant of silicon
- ⁇ 0 represents a dielectric constant of vacuum
- q represents an elementary quantity of charges
- ⁇ FP represents quasi Fermi level which is represented by the following formula.
- ⁇ FP ( kT/q ) ⁇ ln ⁇ ( N A /n i )
- k represents a Boltzmann's constant
- T represents an absolute temperature
- n i represents a true carrier concentration
- thicknesses (t 1 and t 2 ) of the interlayer insulating films located above and below the gate of V ⁇ T are changed in accordance with extension X dmax of the depletion layer. More specifically, the film thicknesses of first and second interlayer insulating films can be determined to satisfy the following formula.
- Thicknesses (t 1 and t 2 ) of interlayer insulating films X dmax +impurity diffusion lengths (l 1 and l 2 ).
- N A is 1 ⁇ 10 17 /cm 3
- X dmax goes to 2200 ⁇ .
- the interlayer insulating films in the above case have the film thicknesses of 1000 ⁇ and 2500 ⁇ , respectively.
- Interlayer insulating films ( 8 and 9 ) may be deposited by an appropriate method such as CVD, in which case the offset region can be formed with significantly good controllability.
- FIG. 63 is a cross section of a V ⁇ T-DRAM of embodiment 23.
- the DRAM shown in FIG. 63 is the same as the DRAM shown in FIG. 2 except for the following point. Therefore, the same or corresponding portions bear the same reference numbers and will not be described below.
- the device shown in FIG. 63 is provided with LDD portions 46 a and 46 b instead of offsets in FIG. 62.
- the LDDs can improve the voltage resistance against punch-through similarly to the offsets.
- the LDDs are formed as disclosed in the Japanese Patent Application No. 5-345126 (1993), and more specifically, by implanting impurity ions into bit line 24 , LDD portion 46 a , channel region 7 , LDD portion 46 b and storage node 26 with various implantation voltages and implantation doses.
- They may be formed also by implanting impurity into the LDD portions during the epitaxial growth.
- This embodiment relates to a method of forming the LDDs utilizing abnormal diffusion of phosphorus.
- FIG. 64 is an impurity profile in the V ⁇ T channel plug taken along line C-C′ in FIG. 62.
- arsenic (As) or phosphorus (P) is generally used as impurity in source and drain, and its distribution forms Gaussian distribution.
- phosphorus forms the distribution curve having an extended tail at a low concentration region as shown in the figure.
- Embodiment 25 relates to a structure in which impurity profile of the channel is changed to improve the voltage resistance against punch-through.
- FIG. 65 shows an impurity profile of the channel taken along line C-C′ in FIG. 62. As shown in FIG. 65, the channel profile having peaks at opposite ends of the channel is formed by two channel implanting operations ( 1 ) and ( 2 ) with different implanting depths.
- dotted line ( 3 ) shows the curve for comparison which is obtained by only one channel implanting operation.
- Embodiment 26 is aimed at suppression of the parasitic bipolar effect.
- the channel potential of V ⁇ T is electrically floated. Therefore, a large number of carriers are accelerated at a high electric field portion between the channel and drain, and impinge against the lattice of silicon. A small number of carriers generated by this impingement are confined in the channel. This is referred to as an impact ionization phenomenon.
- impact ionization caused by acceleration of electrons generates holes, and they are confined in the channel, so that the potential of channel lowers.
- V ⁇ T of P-channel may be used in the memory cell of V ⁇ T-DRAM.
- the impact ionization efficiency of holes is smaller than that of electrons, the parasitic bipolar effect can be suppressed.
- Embodiments 27 and 28 are aimed at increase of the capacitor capacitance of V ⁇ T-DRAM.
- FIG. 67 shows an upper portion of the contact hole of V ⁇ T filled with amorphous silicon.
- FIG. 67 does not show components of the V ⁇ T-DRAM other than the capacitor.
- Contact hole 10 of V ⁇ T is formed in second interlayer insulating film 9 .
- Contact hole 10 is filled with amorphous silicon 15 .
- Amorphous silicon 15 is monocrystallized by epitaxial growth.
- the monocrystal is etched back to expose the surface of second interlayer insulating film 9 .
- polysilicon 47 made of grains of a minute diameter is deposited on second interlayer insulating film 9 .
- polysilicon having a significantly irregular surface is used at a storage node for increasing a surface area thereof so as to increase the capacitor capacitance.
- polysilicon having a significantly irregular surface may be deposited as shown in FIG. 70 and may be processed into a storage node form as shown in FIG. 71.
- Storage node 26 thus formed has an irregular upper surface, so that the capacitance of capacitor increases.
- This method cannot increase the surface area of a side surface 26 a because the side surface 26 a exposed by the etching is flat.
- storage node 26 is formed by patterning polysilicon 47 as shown in FIGS. 69 and 72. Referring to FIGS. 72 and 73, the surface of storage node 26 is oxidized. Grain boundaries of polysilicon is oxidized at a higher speed than the gains, so that the gain boundaries of polysilicon are oxidized more rapidly than the others. As a result, irregularities corresponding to the sizes of grains are formed at the upper and side surfaces of storage node 26 .
- An SiO 2 film 99 formed at the surface of storage node 26 can be used as the capacitor insulating film as it is.
- the SiO 2 film may be removed, and then film 49 having a high dielectric constant such as double layer of SiN and SiO 2 may be formed.
- the capacitance of capacitor can be sufficiently increased.
- the storage node described above may be applied to DRAMs other than the V ⁇ T-DRAM.
- This embodiment relates to a structure in which highly dielectric material is used for increasing the capacitor capacitance.
- a titanium nitride film 50 is deposited after the etch-back of amorphous silicon, and a first platinum film 51 is deposited thereon. Then, these films are processed into a form of storage node 26 . Then, a highly dielectric film (Ba, Sr) TiO 3 film 52 is deposited on second interlayer insulating film 9 . A second platinum film 53 is deposited on (Ba, Sr) TiO 3 film 52 . Cell plate 22 of polysilicon is formed on second platinum film 53 .
- This embodiment relates to increase of the degree of integration above 4F 2 or 4r 2 .
- contact holes 10 of V ⁇ Ts are disposed at apexes of triangles with sides, each of which has a length equal to twice the minimum line width. This disposition attains the highest disposition density of contact holes 10 of V ⁇ Ts.
- An area 100 of one cell in this structure is equal to 2(3) 1 ⁇ 2 r 2 , i.e., nearly 3.5r 2 , so that the degree of integration of cells are much higher than 4r 2 in embodiments 17 and 18.
- a width W4 of (3) 1 ⁇ 2 r, i.e., nearly 1.73r can be used for forming word line (WL) and bit line (BL).
- bit line (BL) a minimum required width is generally 2r which is a sum of the width (r) of bit line and a width (r) between the bit lines, and thus 1.73r is insufficient.
- word line (WL) a minimum required width is generally 2r which is a sum of the width (r) of word line and a width (r) between the word lines, and thus 1.73r is insufficient.
- the cell of 3.5r 2 cannot be obtained.
- the word lines and bit lines are pattered with a mask which is provided with phase shifters enabling shift of the phase by 180° with a space of 1.73r, the bit lines and word lines can be formed as shown in FIG. 77, and thus the cell of 3.5r 2 can be obtained.
- Embodiments 30 and 31 relate to a layout of a peripheral circuitry.
- the cell array of 4F can generally provide only a small space for a peripheral circuitry.
- sense amplifiers may be disposed at vertically opposite sides of the memory cells such that the sense amplifiers disposed at the same side (i.e., upper or lower side) are connected to alternate bit lines BL.
- decoders may be disposed at laterally opposite sides of the memory cells such that the decoders disposed at the same side (i.e., right or left side) are connected to alternate word lines WL. This disposition increases the space for the peripheral circuitry. The above manner of disposition may be applied only to the sense amplifiers or the decoders.
- This embodiment relates to a manner of connection in the case where contact must be made at a very deep position between adjacent V ⁇ Ts in the DRAM cell array or peripheral circuitry.
- a dummy V ⁇ T 57 is disposed between a first V ⁇ T 55 and a second V ⁇ T 56 , so that the contact of aluminum interconnection 54 can be made easily.
- channel portion 7 of the dummy V ⁇ T must contain impurity of the same conductivity type as the source and drain at a high concentration as shown in FIG. 80.
- Embodiment 32 relates to a process of producing the peripheral circuitry of V ⁇ T-DRAM formed of SOI transistors.
- SOI layer 30 is patterned to form simultaneously an active region 58 of SOI transistor and bit line BL of the cell array of V ⁇ T-DRAM.
- dry etching is effected to pattern SOI layer 30 for isolating active region 58 and bit line BL from each other.
- they may be isolated by an LOCOS oxide film as is done in embodiment 16.
- a gate insulating film 59 and a gate electrode 60 of SOI transistor are formed.
- side wall spacers 101 are formed at respective side walls of active region 58 , gate electrode 60 and bit line BL. Ions are implanted into source/drain regions 102 a and 102 b of SOI transistor, and simultaneously, ions are implanted into bit line BL. This simultaneous implantation also simplifies the steps.
- silicidation is simultaneously effected on the surfaces of source 102 a , gate electrode 60 and drain 102 b of SOI transistor as well as the surface of bit line BL to form silicide films 62 on the respective surfaces. Simultaneous silicidation of the respective surfaces simplifies the steps. Thereafter, the V ⁇ T-DRAM is formed on bit line BL.
- a buried SiO 2 film 80 a is disposed on a substrate 80 .
- a source 80 b , a channel 80 c and a drain 80 d of an SOI transistor as well as a source 80 e of V ⁇ T are disposed on buried SiO 2 film 80 a .
- a gate 80 f of V ⁇ T is disposed on source 80 e of V ⁇ T.
- Channel 80 g of V ⁇ T is formed by crystallization of filled amorphous silicon. Then, channel implantation 80 h for V ⁇ T is performed. If channel implantation 80 h for V ⁇ T were performed on the whole surface, impurity used in channel implantation for V ⁇ T would be introduced even into channel 80 c of SOI transistor, resulting erroneous change of the threshold of SOI transistor. This may be avoided by performing the channel implantation for V ⁇ T with a photoresist covering the SOI transistor portion. However, this requires an additional mask, resulting in increase of the manufacturing cost.
- a dummy pattern 80 i of the gate of V ⁇ T is disposed above channel 80 c of SOI transistor as shown in FIG. 129. Owing to dummy pattern 80 i of the gate of V ⁇ T, the impurity is not introduced into channel 80 c of SOI transistor even if channel implantation for V ⁇ T is effected on the whole surface. Since this method does not use a mask, the manufacturing cost does not increase.
- FIG. 85 is a cross section of the V ⁇ T-DRAMs of embodiment 33 .
- a first V ⁇ T 63 is formed above bit line 24 , and a capacitor 64 of a trench type is connected to the upper side of the first V ⁇ T.
- a second V ⁇ T 65 is connected to the lower side of bit line 24 .
- a second capacitor 65 of the trench type is connected to the second V ⁇ T.
- This layer structure is formed by laminating memory cells 1 and 2 to each other. The structure of V ⁇ T is the same as that shown in FIGS. 1 and 2.
- the channel can be monocrystallized.
- a curve (a) represents electrical characteristics of an ordinary bulk Si transistor.
- a curve (b) represents electrical characteristics of a transistor of the SOI structure.
- a drain current rapidly increases after a gate voltage increases to and above a certain value, which is different from the characteristics (a) of the ordinary bulk Si transistor. This phenomenon is probably caused by the following reason.
- Embodiment 34 has been developed to overcome the above problem.
- FIG. 88 is a cross section of V ⁇ T of embodiment 34.
- Substrate 1 is provided at its main surface with first impurity diffusion layer 6 a forming one of source/drain regions.
- First interlayer insulating film 2 a is disposed on substrate 1 .
- Gate electrode 3 is disposed on first interlayer insulating film 2 a .
- Second interlayer insulating film 2 b covering gate electrode 3 is disposed on first interlayer insulating film 2 a .
- contact hole 19 which penetrates first interlayer insulating film 2 a , gate electrode 3 and second interlayer insulating film 2 b , and exposes a portion of the surface of first impurity diffusion layer 6 a .
- Gate insulating film 4 covers the side wall of contact hole 19 .
- the device is provided with a silicon thin film 39 which is contact with first impurity diffusion layer 6 a .
- Silicon thin film 39 continuously covers the side wall of contact hole 19 with the gate insulating film therebetween and has a concave portion at contact hole portion 19 .
- Silicon thin film 39 is divided into three regions, i.e., cylindrical channel region 7 surrounded by gate electrode 3 as well as source region 6 aa and drain region 6 b , which are located above and below channel region 7 , respectively.
- a silicon oxide film 32 fills a portion of the concavity of silicon thin film 39 lower than the upper end of channel region 7 .
- Body polysilicon 66 fills a portion of the concavity of silicon thin film 39 located above silicon oxide film 32 .
- Body polysilicon 66 is in contact with channel region 7 .
- body silicon 66 As a lead electrode, the potential of channel region 7 is fixed.
- Body polysilicon 66 is in contact with an aluminum electrode 68 via a body contact 67 disposed in a silicon oxide film 103 .
- a P + -layer 69 is formed at the surface of body polysilicon 66 .
- Ohmic connection is made between aluminum electrode 68 and body polysilicon 66 via P + -layer 69 .
- the device shown in FIG. 88 is manufactured as follows.
- the interior of contact portion 19 is filled with silicon oxide film 32 , and the surface of silicon oxide film 32 is shaved off by etching to expose the top end of channel region 7 .
- body polysilicon 66 to which P-type impurity is added is deposited on the entire surface by the LPCVD method. Body polysilicon 66 has at least such a film thickness that it completely fills contact hole 19 . Body polysilicon 66 is etched to an extent that exposes drain region 6 b . Thereby, body polysilicon 66 is correctly located in contact hole 19 .
- silicon oxide film 103 is deposited, and body contact 67 is opened. Arsenic is implanted into the opening to form P + -layer 69 on the surface of body contact in a self-alignment manner. Aluminum electrode 68 is connected to P + -layer 69 .
- FIG. 91 is a cross section of V ⁇ T of embodiment 35.
- This embodiment differs from embodiment 34 in that polysilicon 66 does not completely fill contact hole 19 . Even this structure can fix the potential of channel region 7 .
- connection between the aluminum electrode and body polysilicon 66 cannot be made above the transistor, and thus connection of aluminum must be made at a position other than the transistor.
- deposited body polysilicon must be thick.
- embodiment 35 has an advantage that it can be thin.
- the drain region is formed above the channel region, and the source region is formed under the channel region. However, they may be located in the opposite manner. If the drain is located at the upper side, a junction area between the drain and the body polysilicon increases, so that the leak current from the drain may increase and the voltage resistance of the drain may decrease. Accordingly, the source is preferably located at the upper side in the structure of the embodiment.
- the body potential of channel region is fixed by the body polysilicon, so that it is possible to prevent latch, which may be caused by parasitic bipolar effect, and thus to suppress generation of an abnormal drain current.
- V ⁇ T disclosed in Japanese Patent Application No. 5-345126
- the diameter of cylindrical or columnar body of V ⁇ T directly depends on the inner diameter of contact hole. Therefore, V ⁇ T cannot have the body of a diameter smaller than the minimum hole diameter attainable by the lithography technique. If the diameter of body is large, the drain end has a large junction area, so that a large leak current flows in proportion to the junction area. If the body is thick, it is difficult to achieve complete depletion of the same, so that the drain current cannot be increased sufficiently.
- silicon nitride film 12 of 500 ⁇ . in thickness is deposited on n ⁇ -type substrate 1 .
- Silicon nitride film 12 is patterned into a predetermined configuration. Portions not covered with silicon nitride film 12 are oxidized to form isolating oxide film 13 at the main surface of substrate 1 .
- Impurity is implanted into the main surface of substrate 1 through silicon nitride film 12 to form source/drain region 6 .
- First interlayer insulating film 2 a of 200 ⁇ in thickness is formed on substrate 1 to cover silicon nitride film 12 and isolating oxide film 13 .
- Polysilicon of 500 ⁇ in thickness is deposited on first interlayer insulating film 2 a and is patterned to form gate electrode 3 .
- Second interlayer insulating film 2 b of 2000 ⁇ in thickness is deposited on substrate 1 to cover gate electrode 3 .
- Contact hole 8 which penetrates first interlayer insulating film 2 a , gate electrode 3 and second interlayer insulating film 2 b , is formed for exposing surface 9 a of silicon nitride film 12 .
- Polysilicon 70 containing n-type impurity added thereto and having a thickness of 200 nm is deposited by the LP-CVD method.
- the entire surface of polysilicon 70 is etched by the anisotropic dry etching method, so that a side wall 71 of polysilicon having a thickness of 200 nm is formed on the inner wall of contact hole 8 .
- the inner diameter of contact hole 8 is 600 nm, a space remaining in the contact hole has the inner diameter of 200 nm.
- the surface of side wall spacer 71 is oxidized by the thermal oxidation method at 800° C. to 1000° C., so that gate insulating film 4 made of a silicon oxide film is formed.
- the surface of silicon substrate 1 at the bottom of contact hole 8 is not covered with silicon nitride film 12 , and thus is not oxidized.
- silicon nitride film 12 exposed at the bottom of contact hole is removed with phosphoric acid solution.
- etching progresses also in the lateral direction. Therefore, excessive etching may remove silicon nitride film 12 located under side wall spacer 71 , so that the side wall spacer 71 will be in contact with channel polysilicon which will be deposited in a later step. Therefore, it is important not to perform the excessive etching with phosphoric acid. If any problem may arise, it is preferable to employ the anisotropic dry etching. In this case, however, gate insulating film 4 is also etched, so that this etching must be performed under the conditions that the etching select ratio of silicon oxide film and silicon nitride film is large and damage is suppressed.
- silicon 103 which will form the body of transistor is deposited by the LP-CVD method to fill contact hole 8 . Thereafter, silicon 103 is crystallized by solid-phase growth method (anneal at 600° C.). Thereafter, impurity is introduced into the surface of silicon to form drain region 6 b .
- P-channel P-type impurity such as boron is implanted with the implantation energy of 8 keV and concentration of 5 ⁇ 10 15 /cm 3 . The heat treatment is effected at 850° C. for 30 seconds, so that impurity diffuses from source region 6 into silicon 103 , and also diffuses from drain region 6 b into silicon 103 .
- V ⁇ T is completed.
- side wall spacer 71 of polysilicon is formed at the inner wall of contact hole 8 , the diameter of cylindrical or columnar channel 7 is smaller than the inner diameter of contact hole 8 by twice the sum of the thickness of side wall spacer 71 and the thickness of gate insulating film 4 . Since side wall spacer 71 of polysilicon is in contact with gate electrode 3 , it is side wall spacer 71 that functions as the gate of transistor, and no problem arises in connection with the operation.
- FIG. 96 is a cross section of V ⁇ T of embodiment 37.
- side wall spacer 71 has an upper end at the same level as the upper surface of second interlayer insulating film 2 b .
- drain portion 6 b and the gate (side wall spacer 71 ) overlap each other through a large area, so that capacitance increases and thus such problems may arise that the operation speed of circuit decreases and that the leak current induced by the drain voltage increases.
- This embodiment has been developed to over come these problems.
- the upper end of side wall spacer 71 i.e., second gate is positioned at the level lower than the upper surface of second interlayer insulating film 2 b .
- This structure eliminates the overlapping of drain portion 6 b and gate (side wall spacer 71 ), so that the above problems are overcome.
- the junction area of drain 6 b and channel 7 directly depends on the inner diameter of contact hole 8 and thus increases as described previously.
- the side wall spacer of silicon is formed at the inner wall of contact hole and is used as the gate electrode, the diameter of the channel portion of body can be small. As a result, the leak current can be reduced, and the drain current in the on-state can be large.
- This embodiment relates to a 2-input OR circuit using V ⁇ T.
- FIG. 97 if a contact hole of V ⁇ T is formed over two gates, i.e., first and second gates 72 and 73 , a circuit surrounded by dotted line in FIG. 98 can be formed within a very small area. As shown in FIG. 98, by adding a load such as a resistance to this circuit, the 2-input OR circuit can be completed easily. This OR circuit is remarkably affected by a mask. For example, if a contact hole 97 of V ⁇ T shifts upward in FIG. 97, a first channel 104 becomes wide, and a second channel 105 becomes narrow. If it shifts oppositely, first channel 104 becomes narrow, and second channel 105 becomes wide.
- an amount of shift or displacement of the mask can be electrically determined by comparison between values of current which flow between V CC and GND when only first gate 72 is turned on and when only second gate 73 is turned on. If the circuit is used for detecting the shift of mask, the load is not required in FIG. 98. If the contact hole of V ⁇ T has another shape, the channel width changes in a different manner in accordance with the change of shift, so that the sensitivity can be changed.
- the contact hole of V ⁇ T is disposed at the crossing of gates which are patterned into a cross shape as shown in FIG. 99. Thereby, a 4-input OR circuit is completed as shown in FIG. 100.
- the contact hole of V ⁇ T may have another shape to form an OR circuit having more inputs.
- This embodiment relates to formation of a 2-input AND circuit using V ⁇ T.
- FIG. 101 is a cross section of an AND circuit using V ⁇ T of embodiment 39.
- a first SiO 2 film 75 covering GND.
- a first gate 76 is disposed on first SiO 2 film 75 .
- a second SiO 2 film 77 covering first gate 76 is disposed on first SiO 2 film 75 .
- a second gate electrode 78 is disposed on second SiO 2 film 77 .
- a third SiO 2 film 79 covering second gate electrode 78 is disposed on second SiO 2 film 77 .
- Contact hole 10 which penetrates third SiO 2 film 79 , second gate electrode 78 , second SiO 2 film 77 , first gate electrode 76 and first SiO 2 film 75 , is provided for exposing the surface of GND.
- N + -semiconductor layer 106 an N ⁇ -semiconductor layer 107 and an N + -semiconductor layer 108 are formed successively in contact hole 10 .
- a p 31 -semiconductor layer surrounded by first gate electrode 76 is a first channel
- a p ⁇ -semiconductor layer surrounded by second gate electrode 78 is a second channel.
- the 2-input AND circuit is formed as shown in FIG. 103.
- An additional gate(s) which the contact hole of V ⁇ T penetrates may be overlaid, so that the number of inputs can be increased.
- second SiO 2 film 77 If the interlayer film (second SiO 2 film 77 ) between two gates is thin as shown in FIG. 101, it is not necessary to introduce impurity of the same conductivity type as the source/drain into a portion between channels of V ⁇ Ts with a high concentration. If second SiO 2 film 77 is thick as shown in FIG. 102, it is necessary to introduce impurity of the same conductivity type as the source/drain into the portion between two channels.
- the impurity may be introduced by ion implantation or epitaxial growth.
- a second V ⁇ T 81 may be formed on a first V ⁇ T 80 .
- P-type and N-type may be replaced with each other.
- FIG. 105 is a cross section of a semiconductor device of embodiment 40 , in which a V ⁇ T of P-channel and a V ⁇ T of N-channel are vertically aligned to form an inverter circuit. In order to eliminate P-N junction formed between these V ⁇ T, silicide 82 is interposed between them.
- an opening 82 a is formed at a portion of silicide 82 .
- it is not necessary to monocrystallize the channel of P-channel V ⁇ T it is not necessary to provide opening 82 a at silicide 82 .
- FIG. 106 is a cross section of a semiconductor device of embodiment 41.
- two V ⁇ T has such a structure that a gate of a first V ⁇ T is commonly used as a source of a second V ⁇ T, and that a drain of the first V ⁇ T is commonly used as a gate of the second V ⁇ T.
- a circuit shown in FIG. 107 is completed.
- a flip-flop can be formed, if the above structure is formed of a P-channel V ⁇ Ts and an N-channel V ⁇ Ts in this manner and is connected as shown in FIG. 108.
- the gate of first V ⁇ T must be made of monocrystal in order to provide the channel of second V ⁇ T made of monocrystal.
- the gate of first V ⁇ T made of monocrystal is laminated to the SiO 2 film from the layer on the source of first V ⁇ T, so that the gate of first V ⁇ T made of monocrystal is obtained.
- This embodiment relates to a gain cell using V ⁇ T.
- a V ⁇ T is formed on a gate electrode of an MOS transistor of bulk, so that a circuit shown in FIG. 110 is formed to complete a gain cell, in which electric charges stored in the storage node can be amplified for reading out.
- the write operation is performed with the word line and the write bit line similarly to a DRAM.
- a word line voltage and a write bit line voltage are changed as shown in FIG. 111. If the storage node has been charged, the MOS transistor is immediately turned on, and a current immediately flows to the read bit line. However, if the storage node has not stored electric charges, it is necessary to supply electric charges enough for turning on the MOS transistor from the write bit line, so that the current does not immediately flow through the read bit line.
- the threshold voltage V th of MOS transistor is set at a high value in order to prevent flow of leak current through the MOS transistor when the cell is not accessed. In the MOS transistor, the current is significantly amplified and changed even if the quantity of electric charges in gate changes slightly, so that the detection sensitivity to the quantity of gate electric charges is very high.
- the gain cell must periodically repeat the read operation for refreshing data because the leak current of V ⁇ T causes leak of charges from the storage node.
- This circuit operation may be performed by a circuit shown in FIG. 101 or other structures equivalent to the same.
- the MOS transistor may use an SOI transistor.
- FIG. 112 As shown in FIG. 112, a structure, which is upside-down with respect to that in FIG. 109, may be employed.
- the channel of V ⁇ T cannot be monocrystallized by epitaxial growth.
- the MOS transistor at the upper position may be a polysilicon TFT.
- FIG. 113 conceptively shows a device of embodiment 43. As shown in FIG. 113, V ⁇ Ts may be applied to matrix of a liquid crystal display.
- the dynamic random access memory can have the bit lines of a small capacitance and can operate at a high speed.
- bit lines since the bit line is commonly used by the upper and lower V ⁇ Ts, the bit lines can be formed only by one step. This reduces the number of steps and thus can reduce the cost.
- the semiconductor device of the fourth aspect of the invention there is provided the polysilicon which fills the concave portion of the silicon thin film and is in contact with the channel portion, and this polysilicon is used as the lead electrode. Therefore, the potential of channel portion can be fixed.
- the semiconductor device of the fifth aspect of the invention since there is provide the conductive member covering the side wall of contact hole, it is possible to manufacture the V ⁇ T having the body of which diameter is smaller than the minimum hole diameter attainable by the lithography technique. Consequently, the body can be depleted completely.
- the circuit can be formed in a very small area.
- the occupied area can be small.
- the occupied area can be small.
- the occupied area can be small.
- the occupied area can be small.
- the occupied area can be small.
- the capacitance of the bit line can be small.
Abstract
Description
- 1. Field of the Invention
- The present invention relates in general to a semiconductor device, and in particular to a semiconductor device utilizing a vertical surround gate MOSFET (will be referred to as a “VΦT” hereinafter). The invention also relates to a method of manufacturing such a semiconductor device. The invention further relates to an improvement of VΦT.
- 2. Description of the Background Art
- FIG. 114 shows trend of cell sizes of dynamic random access memories (DRAMs). FIG. 114 additionally shows design rules in respective generations. Conventional DRAM cells include, as components, bit lines (BL), word lines (WL), bit line contacts (BK), and storage contacts (SK). Therefore, the cell size, which is expressed with F (feature size) of the following formula, is 8F2.
- F(feature size)=r+α
- wherein F represents a gate width, r represents a minimum line width and α represents a process margin.
- In FIG. 114, the design rule (minimum line width) is simply set to F, and 8F2 and 4F2 (hollow and solid circles) are plotted in a superimposed form. As can be seen therefrom, the cells of 8F2 can form 256M-DRAM at the most. Meanwhile, the cell size of 4F2 can achieve a DRAM of G-bit generation by following the conventional reduction rule.
- The cells of 4F2 can be formed by arranging vertical transistors at crossings of the bit lines BL and word lines Wl. Based on the above background, various kinds of vertical transistors have been proposed.
- FIG. 115 is a cross section of a first prior art, which is a vertical surround gate transistor disclosed in Japanese Patent Laying-Open No. 5-160408 (1993). Referring to FIG. 115, a
gate 3 is formed around acolumn 5 of silicon forming a channel with agate insulating film 4 therebetween. Asource 6 a and adrain 6 b are connected tosilicon column 5. - A significant problem arises in connection with formation of
gate electrode 3 forming the word line if the above transistor is applied to a DRAM. - FIG. 116 is a cross section of a semiconductor device showing a process of manufacturing the surround gate transistor shown in FIG. 115.
Gate insulating film 4 is formed to coversilicon column 5. Then, polysilicon (3) is deposited to coversilicon column 5 withgate insulating film 4 therebetween. Anisotropic etching is effected on polysilicon (3) to formgate electrode 3 on a side wall ofsilicon column 5. According to this method, agate length 1 depends on an anisotropic etching rate of polysilicon (3). Therefore, a variation v of thegate length 1 is large. According to this method, therefore, it is very difficult to obtain stably the cells of 4F2. - FIGS. 117 and 118 are cross sections showing steps in a process of manufacturing a vertical surround gate transistor disclosed in Japanese Patent Laying-Open No. 4-282865 (1992).
- Referring to FIG. 117, an SiO2 layer 2 a, polysilicon, i.e.,
word line 3 and an SiO2 layer 2 b are formed in this order on abit line 26. There is also provided acontact hole 8 penetrating SiO2 layer 2 b,polysilicon 3 and SiO2 layer 2 a.Gate insulating film 4 is formed on the side wall ofcontact hole 8. - Referring to FIGS. 117 and 118, the side wall of
contact hole 8 is covered withpolysilicon 5. Polysilicon 5 is divided into asource 6 a, achannel 7 and adrain 6 b. The transistor thus constructed has the following problem. Referring to FIG. 117, variation v of etching quantity is liable to occur when forminggate insulating film 4, and in some cases, anupper corner 3 c of the gate electrode is exposed, resulting in leak betweencorner 3 c of the gate anddrain 6 b. - The transistor also has the following problem in connection with its operation.
- The conductivity types of the gate polysilicon and channel polysilicon are opposite to each other, and a difference in their work function is utilized for depleting the channel polysilicon, whereby the off state is achieved between the source and drain. For this purpose, a film thickness of the channel polysilicon must be smaller than the maximum width of the depletion layer which depends on concentration of impurity in the channel polysilicon.
- Meanwhile, if the resistance of source/drain is high, a sufficient on-current cannot be obtained. Therefore, it is necessary to increase the content of impurity in the channel polysilicon for lowering the resistance. In an ordinary TFT, the content of impurity in the source/drain is 1020/cm3 at the most. However, if impurity were introduced at the large content of 1020/cm3, the maximum width of depletion layer would be approximately 40 Å. Therefore, due to restriction that the film thickness of the channel polysilicon must be smaller than the above value, it would probably be impossible to achieve stable manufacturing of the transistors without sacrificing characteristics.
- In order to overcome the above problems, the inventors and others have proposed a vertical Φ-shaped transistor (VΦT) as shown in FIG. 119 (Japanese Patent Laying-Open No. 5-345126 (1993)).
- FIG. 119 is a perspective view showing a major portion of a VΦT. FIG. 120 is a cross section of the VΦT.
- Referring to these figures, a MOSFET includes a
substrate 1.Source region 6 a is formed at a main surface ofsubstrate 1. Firstinterlayer insulating film 2 a is formed onsubstrate 1.Gate electrode 3, which has a top surface substantially parallel to the surface of substrate, is formed on firstinterlayer insulating film 2 a. Secondinterlayer insulating film 2 b coveringgate electrode 3 is formed on firstinterlayer insulating film 2 a. A surface ofsource region 6 a is partially exposed through acontact hole 19 which penetrates firstinterlayer insulating film 2 a,gate electrode 3 and second interlayerinsulating film 2 b.Gate insulating film 4 covers the side wall ofcontact hole 19. Incontact hole 19, there is formed afirst semiconductor layer 20 of a P-type, which is in contact with asurface 9 ofsource region 6 a and extends from the surface ofsource region 6 a to the same level as a lower surface ofgate electrode 3. Incontact hole 19, there is also formed achannel semiconductor layer 7, which is in contact with a surface offirst semiconductor layer 20 and extends from the surface offirst semiconductor layer 20 to the same level as an upper surface ofgate electrode 3. Asecond semiconductor layer 5 of the P-type, which is in contact with the surface ofchannel semiconductor layer 7 and formsdrain region 6 b, is formed onchannel semiconductor layer 7. - A third
interlayer insulating film 2 c coveringdrain region 6 b is formed on the substrate. Thirdinterlayer insulating film 2 c is provided with aconnection hole 11 a exposing a portion of the surface ofdrain region 6 b. Analuminum electrode 10 a is connected todrain region 6 b throughconnection hole 11 a. - Although the structure shown in FIGS. 119 and 120 can overcome the problems of the technique shown in FIGS. 115 and 117, it has such a problem that a capacitance of a bit line can not be reduced below a restricted extent.
- Accordingly, it is an object of the invention to provide a semiconductor device which includes a bit line having a reduced capacitance, is improved to enable high-speed operation and utilizes a VΦT.
- Another object of the invention is to provide a DRAM of a G-bit generation.
- Still another object of the invention is to provide a DRAM having a cell size of 4F2.
- Yet another object of the invention is to provide a method of manufacturing such a DRAM.
- Further another object of the invention is to improve the VΦT described above.
- Also, an object of the invention to provide an AND circuit using a VΦT.
- A further object of the invention to provide an OR circuit using a VΦT.
- A further object of the invention to provide an inverter circuit using a VΦT.
- A further object of the invention to provide a flip-flop using a VΦT.
- A further object of the invention to provide a gain cell using a VΦT.
- A further object of the invention to provide a matrix of a liquid crystal display using a VΦT.
- A first aspect of the invention relates to a semiconductor device, in which a gate transistor is operable to store information in a capacitor formed of a storage node, which is arranged at a crossing between a bit line and a word line, a capacitor insulating film and a cell plate electrode. The semiconductor device includes a substrate on which a dielectric layer and a semiconductor layer are formed successively. A first impurity diffusion layer of a second conductivity type is disposed in the semiconductor layer. The first impurity diffusion layer contains impurity of the first conductivity type implanted thereinto, and forms one of source/drain regions and the bit line. A first interlayer insulating film covering the first impurity diffusion layer is disposed on the substrate. A gate electrode which also forms the word line and has upper and lower surfaces is disposed on the first interlayer insulating film. A second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film. A contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first impurity diffusion layer. A side wall of the contact hole is covered with a gate insulating film. A first semiconductor layer of the first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first impurity diffusion layer and extends from the surface of the first impurity diffusion layer to the substantially same level as the lower surface of the gate electrode. A channel semiconductor layer is formed in the contact hole. The channel semiconductor layer is in contact with the surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode. A second conductive layer of the first conductivity type is disposed on the channel semiconductor layer. The second conductive layer is in contact with a surface of the channel semiconductor layer, and forms the storage node and the other of the source/drain regions. A capacitor insulating film is disposed on the second conductive layer.
- A second aspect of the invention relates to a semiconductor device in which contact is to be made at a deep position. The device of this aspect includes a substrate on which a dielectric layer and a semiconductor layer are formed successively. A first impurity diffusion layer of a first conductivity type is disposed in the semiconductor layer. The first impurity diffusion layer forms a bit line and one of source/drain regions. A first interlayer insulating film covering the first impurity diffusion layer is disposed on the substrate. A gate electrode which also forms the word line and has upper and lower surfaces is disposed on the first interlayer insulating film. A second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film. A contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first impurity diffusion layer. A side wall of the contact hole is covered with a gate insulating film. A first semiconductor layer of the first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first impurity diffusion layer and extends from the surface of the first impurity diffusion layer to the substantially same level as the lower surface of the gate electrode. A second semiconductor layer of the same first conductivity type as the first semiconductor layer is formed in the contact hole. The second semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode. A third semiconductor layer of the first conductivity type is formed in the contact hole and is disposed on the second semiconductor layer. The third semiconductor layer is in contact with a surface of the second semiconductor layer. An interconnection is connected to the third semiconductor layer.
- A third aspect of the invention relates to a semiconductor device, in which a gate transistor is operable to store information in a capacitor formed of a storage node, which is arranged at a crossing between a bit line and a word line, a capacitor insulating film and a cell plate electrode. The device of this aspect includes a bit line having upper and lower surfaces. A first vertical Φ-shaped transistor is disposed on the upper surface of the bit line. A capacitor is connected to the first vertical Φ-shaped transistor. A second vertical Φ-shaped transistor is disposed on the lower surface of the bit line. A second capacitor is connected to the second vertical Φ-shaped transistor.
- A fourth aspect of the invention relates to a semiconductor device in which flow of a large number of carriers is controlled by a voltage applied to a gate. The semiconductor device of this aspect includes a substrate having a main surface. A first conductive layer of a first conductivity type forming one of source/drain regions is disposed at the main surface of the substrate. A first interlayer insulating film is disposed on the substrate. A gate electrode having upper and lower surfaces is disposed on the first interlayer insulating film. A second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film. A contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first conductive layer. A side wall of the contact hole is covered with a first gate insulating film. The semiconductor device further includes a silicon thin film which is in contact with the first conductive layer and continuously extends to cover an inner wall of the contact hole with the first gate insulating film therebetween. The silicon thin film has a concave portion, which located in the contact hole and has a bottom surface located at a level lower than the lower surface of the first gate electrode. The silicon thin film is formed of three portions which are a cylindrical channel portion surrounded by the first gate electrode as well as a source region and a drain region located at vertically opposite sides of the channel portion. The device further includes a silicon oxide film which is disposed in the concave portion of the silicon thin film and is located at a level lower than an upper end of the channel portion. The concave portion of the silicon thin film is filled with polysilicon which is in contact with the channel portion. In this semiconductor device, the polysilicon is used as a lead electrode for fixing the potential of the channel portion.
- A fifth aspect of the invention relates to a semiconductor device in which flow of a large number of carriers is controlled by a voltage applied to a gate. The semiconductor device of this aspect includes a substrate having a main surface. A first conductive layer of a first conductivity type forming one of source/drain regions is disposed at the main surface of the substrate. A first interlayer insulating film is disposed on the substrate. A gate electrode is disposed on the first interlayer insulating film. A second interlayer insulating film covering the gate electrode is disposed on the first interlayer insulating film. A contact hole penetrating the first interlayer insulating film, the gate electrode and the second interlayer insulating film is provided for exposing a portion of a surface of the first conductive layer. A side wall of the contact hole is covered with a conductive member. A surface of the conductive member is covered with a gate insulating film. A first semiconductor layer of the first conductivity type is disposed in the contact hole and is in contact with the surface of the first conductive layer. A channel semiconductor layer is disposed in the contact hole and is in contact with a surface of the first semiconductor layer. A second semiconductor layer of the first conductivity type forming the other of the source/drain regions is disposed in the contact hole and is in contact with a surface of the channel semiconductor layer.
- A sixth aspect of the invention relates to a semiconductor device including an OR circuit. The semiconductor device of this aspect includes a substrate having a main surface. A first conductive layer of a first conductivity type forming one of source/drain regions is disposed at the main surface of the substrate. A first interlayer insulating film is disposed on the substrate. A first gate electrode and a second gate electrode which adjoin to each other and each have an upper surface and a lower surface are disposed on the first interlayer insulating film. A second interlayer insulating film covering the first and second gate electrodes is disposed on the first interlayer insulating film. A contact hole, which spreads over the first and second gate electrodes, and penetrates the first interlayer insulating film, the first and second gate electrodes and the second interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer. A side wall of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the gate electrode. A channel semiconductor layer is formed in the contact hole. The channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from a surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode. A second semiconductor layer of the first conductivity type forming the other of the source/drain regions is disposed on the channel semiconductor layer and is in contact with the surface of the channel semiconductor layer.
- A seventh aspect of the invention relates to a semiconductor device including an AND circuit. The semiconductor device of this aspect includes a substrate, a first conductive layer of a first conductivity type disposed on the substrate, and a first interlayer insulating film disposed on the substrate and covering the first conductive layer. A first gate electrode having an upper surface and a lower surface is disposed on the first interlayer insulating film. A second interlayer insulating film covering the first gate electrode is disposed on the first interlayer insulating film. A second gate electrode having an upper surface and a lower surface is disposed on the second interlayer insulating film. A third interlayer insulating film covering the second gate electrode is disposed on the second interlayer insulating film. A contact hole, which penetrates the first interlayer insulating film, the first gate electrode, the second interlayer insulating film, the second gate electrode and the third interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer. Side walls of the first and second gate electrodes exposed in the contact hole are covered with a gate insulating film. A first semiconductor layer of a first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with a surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the first gate electrode. A first channel semiconductor layer is formed in the contact hole. The first channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the first gate electrode. A second channel semiconductor layer of a second conductivity type is formed in the contact hole. The second channel semiconductor layer extends from the lower surface of the second gate electrode to the substantially same level as the upper surface of the second gate electrode. A second semiconductor layer of the first conductivity type forming the other of the source/drain regions is disposed on the second channel semiconductor layer and is in contact with a surface of the second channel semiconductor layer.
- An eighth aspect of the invention relates to a semiconductor device including an inverter circuit. The semiconductor device of this aspect includes a first n+conductive layer. A first interlayer insulating film is disposed on the n+-conductive layer. A first gate electrode having an upper surface and a lower surface is disposed on the first interlayer insulating film. A second interlayer insulating film covering the first gate electrode is disposed on the first interlayer insulating film. A first contact hole, which penetrates the first interlayer insulating film, the first gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first n+-conductive layer. A side wall of the first contact hole is covered with a first gate insulating film. A first n +semiconductor layer is formed in the first contact hole. The first n+-semiconductor layer is in contact with a surface of the first n+-conductive layer and extends from the surface of the first n+-conductive layer to the substantially same level as the lower surface of the first gate electrode. A p−-semiconductor layer is formed in the first contact hole. The p−-semiconductor layer is in contact with a surface of the first n+-semiconductor layer and extends from the surface of the first n+-semiconductor layer to the substantially same level as the upper surface of the first gate electrode. A second n−-semiconductor layer is formed in the first contact hole and is disposed on the p−-semiconductor layer. The second n+-semiconductor layer is in contact with a surface of the p−-semiconductor layer and forms the other of the source/drain regions. A second n+-conductive layer is disposed on the second interlayer insulating film and is in contact with the second n+-conductive layer. A first p+-conductive layer is disposed on the second n+-conductive layer. A third interlayer insulating film is disposed on the first p+-conductive layer. A second gate electrode is disposed on the third interlayer insulating film. A fourth interlayer insulating film covering the second gate electrode is disposed on the third interlayer insulating film. A second contact hole penetrating the fourth interlayer insulating film, the second gate electrode and the third interlayer insulating film is provided for exposing a portion of a surface of the first p+-conductive layer. A side wall of the second contact hole is covered with a second gate insulating film. A first p+-semiconductor layer is formed in the second contact hole. The first p semiconductor layer is in contact with a surface of the first p+-conductive layer and extends from the surface of the first p+-conductive layer to the substantially same level as the lower surface of the second gate electrode. An n−-semiconductor layer is formed in the contact hole. The n−-semiconductor layer is in contact with the surface of the first p+-semiconductor layer and extends from the surface of the first p+-semiconductor layer to the substantially same level as the upper surface of the second gate electrode. A second p+-semiconductor layer forming the other of the source/drain regions is disposed in the contact hole. The second p+-semiconductor layer is disposed on the n−-semiconductor layer and is in contact with the surface of the n−-semiconductor layer. A second p+-conductive layer is disposed on the fourth interlayer insulating film and is in contact with the second p+-semiconductor layer.
- A ninth aspect of the invention relates to a semiconductor device including a flip-flop circuit. The semiconductor device of this aspect includes a substrate and a first conductive layer of a first conductivity type disposed on the substrate. A first interlayer insulating film covering the first conductive layer is disposed on the substrate. A first gate electrode of the first conductivity type having an upper surface and a lower surface is disposed on the first interlayer insulating film. A second interlayer insulating film covering the first gate electrode is disposed on the first interlayer insulating film. A first contact hole, which penetrates the first interlayer insulating film, the first gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer. A side wall of the first contact hole is covered with a first gate insulating film. A first semiconductor layer of a first conductivity type is formed in the first contact hole. The first semiconductor layer is in contact with the surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the first gate electrode. A first channel semiconductor layer of a second conductivity type is formed in the first contact hole. The first channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the first gate electrode. A second semiconductor layer of the first conductivity type forming the other of the source/drain regions is formed in the first contact hole. The second semiconductor layer is disposed on the first channel semiconductor layer and is in contact with the surface of the first channel semiconductor layer. A second gate electrode of the first conductivity type is disposed on the second interlayer insulating film and is in contact with the second semiconductor layer. A third interlayer insulating film covering the second gate electrode is disposed on the second interlayer insulating film. A second contact hole, which penetrates the third interlayer insulating film, the second gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first gate electrode. A side wall of the second contact hole is covered with a second gate insulating film. A third semiconductor layer of the first conductivity type is formed in the second contact hole. The third semiconductor layer is in contact with the surface of the first gate electrode and extends from the surface of the first gate electrode to the substantially same level as a lower surface of the second gate electrode. A second channel semiconductor layer of the second conductivity type is formed in the second contact hole. The second channel semiconductor layer is in contact with a surface of the third semiconductor layer and extends from the surface of the third semiconductor layer to the substantially same level as an upper surface of the second gate electrode. A fourth semiconductor layer of the first conductivity type forming the other of the source/drain regions is formed in the second contact hole. The fourth semiconductor layer is disposed on the second channel semiconductor layer and is in contact with the surface of the second channel semiconductor layer. A second conductive layer of the first conductivity type is disposed on the third interlayer insulating film and is connected to the fourth semiconductor layer.
- A tenth aspect of the invention relates to a semiconductor device including a gain cell. The semiconductor device of this aspect includes a substrate, and a first gate electrode of a second conductivity type disposed on the substrate. Source/drain regions of a first conductivity type are disposed at a main surface of the substrate and are located at opposite sides of the first gate electrode. A first interlayer insulating film covering the first gate electrode is disposed on the substrate. A second gate electrode is formed on the first interlayer insulating film. A second interlayer insulating film covering the second gate electrode is formed on the first interlayer insulating film. A contact hole, which penetrates the second gate electrode and the first interlayer insulating film, is provided for exposing a portion of a surface of the first gate electrode. A side wall of the contact hole is covered with a gate insulating film. A first semiconductor layer of a second conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first gate electrode and extends from the surface of the first gate electrode to the substantially same level as a lower surface of the second gate electrode. A channel semiconductor layer of the first conductivity type is formed in the contact hole. The first channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the second gate electrode. A third semiconductor layer of the second conductivity type forming the other of the source/drain regions is formed in the contact hole. The third semiconductor layer is disposed on the channel semiconductor layer and is in contact with the surface of the channel semiconductor layer. A conductive layer of the second conductivity type is formed on the second interlayer insulating film and is in contact with the third semiconductor layer.
- An eleventh aspect of the invention relates to a semiconductor device including a matrix of a liquid crystal display. The semiconductor device of this aspect includes a first conductive layer of a first conductivity type which is disposed on a substrate and forms one of source/drain regions. A first interlayer insulating film is disposed on the substrate. A gate electrode having an upper surface and a lower surface is disposed on the first interlayer insulating film. A second interlayer insulating film covering the gate electrode is formed on the first interlayer insulating film. A contact hole, which penetrates the first interlayer insulating film, the gate electrode and the second interlayer insulating film, is provided for exposing a portion of a surface of the first conductive layer. A side wall of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is formed in the contact hole. The first semiconductor layer is in contact with the surface of the first conductive layer and extends from the surface of the first conductive layer to the substantially same level as the lower surface of the gate electrode. A channel semiconductor layer is formed in the contact hole. The channel semiconductor layer is in contact with a surface of the first semiconductor layer and extends from the surface of the first semiconductor layer to the substantially same level as the upper surface of the gate electrode. A second semiconductor layer of the first conductivity type forming the other of the source/drain regions is formed in the contact hole. The second semiconductor layer is disposed on the channel semiconductor layer and is in contact with a surface of the channel semiconductor layer. A pixel electrode is connected to the second semiconductor layer.
- A twelfth aspect of the invention relates to a method of manufacturing a semiconductor device in which a gate transistor is operable to store information in a capacitor formed of a storage node, which is arranged at a crossing between a bit line and a word line, a capacitor insulating film and a cell plate electrode. The method includes the step of preparing a substrate on which a dielectric member and a semiconductor layer are formed successively. A first conductive layer containing impurity of a first conductivity type is formed at a surface of the semiconductor layer. The first conductive layer forms one of source/drain regions and also forms the bit line. A first interlayer insulating film is formed on the substrate. A gate electrode, which forms the word line and has upper and lower surfaces, is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the substrate to cover the gate electrode. A contact hole is formed. The contact hole penetrates the first interlayer insulating film, the gate electrode and the second interlayer insulating film, and reaches a surface of the first conductive layer. A side wall of the contact hole is covered with a gate insulating film. A second semiconductor layer is formed on the substrate. The second semiconductor layer is in contact with the surface of the first conductive layer, and fills the contact hole. Impurity of the first conductivity type is implanted into a surface of the second semiconductor layer. The impurity implanted into the surface of the second semiconductor layer is diffused into the second semiconductor layer, and the impurity contained in the first conductive layer is diffused from the first conductive layer into the second semiconductor layer, whereby a region, which forms the other of the source/drain regions and also forms the storage node, and a channel region, which is located between the other of the source/drain regions and the one of the source/drain regions, are formed at the second semiconductor layer. A capacitor insulating film is formed on the other of the source/drain regions. A cell plate is formed on the storage node with the capacitor insulating film therebetween.
- According to the semiconductor device of the first aspect of the invention, since the semiconductor layer formed on the dielectric layer is used as the bit line, the capacitance of the bit line is reduced and a dynamic random access memory can operate at a high speed.
- According to the semiconductor device of the second aspect of the invention, since the dummy VΦT is used, contact of the aluminum interconnection can be made easily.
- According to the semiconductor device of the third aspect of the invention, since the bit line is commonly used by the upper and lower VΦT-DRAMs, the bit line can be formed only by one step, so that the number of manufacturing steps and thus a manufacturing cost can be reduce.
- According to the semiconductor device of the fourth aspect of the invention, since the polysilicon, which fills the concave portion of the silicon thin film and is in contact with the channel portion, is used as the lead electrode, the potential of the channel portion can be fixed.
- According to the semiconductor device of the fifth aspect of the invention, since there is provided the conductive member covering the side wall of the contact hole, it is possible to form a VΦT having a body of which a diameter is smaller than a minimum hole diameter attainable with a lithography technique. As a result, the body can be depleted completely.
- According to the semiconductor device of the sixth aspect of the invention including the OR circuit, since the contact hole of the VΦT spreads over two gates, the circuit can be formed within a very small area.
- According to the semiconductor device of the seventh aspect of the invention including the AND circuit, since the VΦT is used as a component of the AND circuit, the area occupied by the device can be small.
- According to the semiconductor device of the eighth aspect of the invention including the inverter circuit, since the VΦT is used, the occupied area can be small.
- According to the semiconductor device of the ninth aspect of the invention including the flip-flop circuit, since the VΦT is used, the occupied area can be small.
- According to the semiconductor device of the tenth aspect of the invention including the gain cell, since the VΦT is used, the occupied area can be small.
- According to the semiconductor device of the eleventh aspect of the invention including the matrix of the liquid crystal, since the VΦT is used, the occupied area can be small.
- According to the method of manufacturing the semiconductor device of the twelfth aspect of the invention, since the semiconductor layer formed on the dielectric member is used as the bit line, the capacitance of the bit line can be reduced.
- The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
- FIG. 1 is a perspective view of a VΦT of an
embodiment 1 of the invention; - FIG. 2 is a cross section taken along line II-II in FIG. 1;
- FIG. 3 shows a layout of a cell array of a DRAM using VΦTs;
- FIGS.4 to 15 are cross sections showing 1st to 12th steps in a process of manufacturing the DRAM using the VΦT of
embodiment 1, respectively; - FIG. 16 is an equivalent circuit diagram of a DRAM array of
embodiment 1; - FIG. 17 is a cross section of a major portion of a DRAM cell using VΦTs of an
embodiment 2; - FIG. 18 is a cross section of a major portion of a DRAM cell of an
embodiment 3; - FIG. 19 is a cross section of a major portion of a DRAM cell of an
embodiment 4; - FIG. 20 is a cross section of a major portion of another DRAM cell of
embodiment 4; - FIG. 21 is a cross section of a major portion of still another DRAM cell of
embodiment 4; - FIG. 22 is a perspective view of a major portion of a DRAM cell array of an
embodiment 5; - FIGS.23 to 27 are cross sections of a semiconductor device at 1st to 5th steps in a process of manufacturing the DRAM cell array of
embodiment 5, respectively; - FIGS. 28 and 29 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing a semiconductor device of an
embodiment 6, respectively; - FIG. 30 is a cross section of a semiconductor device of an
embodiment 7; - FIG. 31 is a cross section of another semiconductor device of
embodiment 7; - FIGS. 32 and 33 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing a semiconductor device of an
embodiment 8, respectively; - FIG. 34 shows a process of manufacturing a semiconductor device of an
embodiment 9; - FIGS. 35 and 36 are cross sections of the semiconductor device at 1st and 2nd steps in a process of manufacturing the semiconductor device of
embodiment 9, respectively; - FIG. 37 is a cross section of a semiconductor device of an
embodiment 10; - FIG. 38 is a cross section of another semiconductor device of
embodiment 10; - FIG. 39 is a cross section of a semiconductor device of an
embodiment 11; - FIG. 40 is a cross section of a semiconductor device of an
embodiment 12; - FIG. 41 shows purposes of
embodiments 13 to 16; - FIG. 42 is a cross section of a semiconductor device of an
embodiment 13; - FIGS.43 to 45 are cross sections of a semiconductor device at 1st to 3rd steps in a process of manufacturing the semiconductor device of an
embodiment 14, respectively; - FIGS. 46 and 47 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing the semiconductor device of an
embodiment 15, respectively; - FIG. 48 is a cross section of a semiconductor device of an
embodiment 16; - FIG. 49 is a cross section of another semiconductor device of
embodiment 16; - FIGS.50 to 52 are cross sections of a semiconductor device at 1st to 3rd steps in a process of manufacturing the semiconductor device of an
embodiment 17, respectively; - FIG. 53 is another cross section of the semiconductor device at the 3rd step in a process of manufacturing the semiconductor device of
embodiment 17; - FIG. 54 is a plan of a photomask used in an embodiment 18A;
- FIG. 55 is a plan of a VΦT-DRAIM cell of embodiment 18A;
- FIG. 56 is a plan of a photomask used in an embodiment 18B;
- FIG. 57 is a plan of contact holes of VΦTs of embodiment 18B;
- FIGS. 58 and 59 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing the semiconductor device of an
embodiment 19, respectively; - FIG. 60 is a cross section of a semiconductor device of an
embodiment 20; - FIG. 61 is a cross section of a semiconductor device of an
embodiment 21; - FIG. 62 is a cross section of a VΦT-DRAM of an
embodiment 22; - FIG. 63 is a cross section of a VΦT-DRAM of an embodiment 23;
- FIG. 64 shows a profile of impurity in a VΦT channel plug taken along line C-C′ in FIG. 62;
- FIG. 65 shows a profile of impurity of a channel taken along line C-C′ in FIG. 62;
- FIG. 66 is a cross section of a semiconductor device of an
embodiment 26; - FIGS.67 to 69 are cross sections of a semiconductor device at 1st to 3rd steps in a process of manufacturing the semiconductor device of an embodiment 27, respectively;
- FIGS. 70 and 71 are cross sections of a conventional semiconductor device;
- FIGS.72 to 74 are cross sections of the semiconductor device at 4th to 6th steps in a process of manufacturing the semiconductor device of embodiment 27, respectively;
- FIG. 75 is a cross section of a semiconductor device of an embodiment 28;
- FIG. 76 shows a layout of contact holes of VΦTs of an embodiment 29;
- FIG. 77 shows a layout of bit lines and word lines of an embodiment 29;
- FIG. 78 shows a layout of a peripheral circuitry in semiconductor device of an
embodiment 30; - FIG. 79 shows a purpose of an
embodiment 31; - FIG. 80 is a cross section of a semiconductor device of an
embodiment 31; - FIGS.81 to 84 are cross sections of a semiconductor device at 1st to 4th steps in a process of manufacturing the semiconductor device of an
embodiment 32; - FIG. 85 is a cross section of a semiconductor device of an
embodiment 33; - FIG. 86 shows a problem of a transistor of a conventional SOI structure;
- FIG. 87 shows a problem arising in the transistor of the conventional SOI structure;
- FIG. 88 is a cross section of a semiconductor device of an
embodiment 34; - FIGS. 89 and 90 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing the semiconductor device of an
embodiment 34, respectively; - FIG. 91 is a cross section of a semiconductor device of an
embodiment 35; - FIGS.92 to 95 are cross sections of a semiconductor device at 1st to 4th steps in a process of manufacturing the semiconductor device of an
embodiment 36, respectively; - FIG. 96 is a cross section of a semiconductor device of an
embodiment 37; - FIG. 97 is a plan of a 2-input OR circuit using VΦTs of an
embodiment 38; - FIG. 98 is a circuit diagram of the semiconductor device shown in FIG. 97;
- FIG. 99 is a plan of another semiconductor device of
embodiment 38; - FIG. 100 is a circuit diagram of a semiconductor device shown in FIG. 99;
- FIG. 101 is a cross section of a semiconductor device of an
embodiment 39; - FIG. 102 is a cross section of another semiconductor device of
embodiment 39; - FIG. 103 is a circuit diagram of an AND circuit shown in FIG. 101;
- FIG. 104 is a cross section of still another semiconductor device of
embodiment 39; - FIG. 105 is a cross section of a semiconductor device of an
embodiment 40; - FIG. 106 is a cross section of a semiconductor device of an embodiment 41;
- FIG. 107 is a circuit diagram of the semiconductor device of embodiment 41;
- FIG. 108 is a circuit diagram of a flip-flop circuit of embodiment 41;
- FIG. 109 is a cross section of a gain cell of an
embodiment 42; - FIG. 110 is a circuit diagram of a circuit using the gain cell of
embodiment 42; - FIG. 111 shows the operation of the semiconductor device of
embodiment 42; - FIG. 112 is a cross section of another semiconductor device of
embodiment 40; - FIG. 113 is a plan of a matrix of a liquid crystal display of an
embodiment 43; - FIG. 114 shows trend of DRAM cell sizes;
- FIG. 115 is a cross section of a vertical surround gate transistor in the prior art;
- FIG. 116 is a cross section showing a process of manufacturing a semiconductor device shown in FIG. 115;
- FIGS. 117 and 118 are cross sections of a semiconductor device at 1st and 2nd steps in a process of manufacturing the vertical surround gate transistor in the prior art, respectively;
- FIG. 119 is a perspective view of a vertical Φ-shaped transistor already proposed by the inventors;
- FIG. 120 is a cross section of a semiconductor device shown in FIG. 119;
- FIGS.121 to 126 are cross sections of a substrate at 1st to 6th steps in a process of manufacturing a photomask shown in FIG. 56, respectively;
- FIG. 127 shows another process of manufacturing the photomask shown in FIG. 56;
- FIG. 128 is a cross section of a semiconductor device for showing a problem in another process of manufacturing the semiconductor device including a peripheral circuitry formed of SOI transistors; and
- FIG. 129 is a cross section of a semiconductor device showing another improved process of manufacturing the semiconductor device including a peripheral circuitry formed of SOI transistors.
-
Embodiment 1 - FIG. 1 is a perspective view of a surround gate transistor (which will be referred to as a “vertical Φ-shaped transistor”, and will be also referred to simply as a “VΦT”, hereinafter) of an
embodiment 1. FIG. 2 is a cross section taken along line II-II in FIG. 1. FIG. 3 shows a layout of a cell array of a DRAM using VΦTs. In the DRAM ofembodiment 1 shown in these figures, a gate transistor is operable to store information in a capacitor which is disposed at a crossing of abit line 24 and aword line 25 and is formed of astorage node 26, acapacitor insulating film 21 and acell plate electrode 22. - On a
substrate 1 of silicon, there is disposed a buried SiO2 layer (dielectric layer) 201. On buried SiO2 layer 201, there is disposed a firstimpurity diffusion layer 24 of a first conductivity type, which contains impurity of the first conductivity type implanted thereinto and forms one of source/drain regions as well as the bit line. Firstimpurity diffusion layer 24 is covered with a firstinterlayer insulating film 8 disposed on buried SiO2 layer 201. On firstinterlayer insulating film 8, there is formed agate electrode 3 which has upper and lower surfaces and also forms the word line.Gate electrode 3 is covered with a secondinterlayer insulating film 9 disposed on firstinterlayer insulating film 8. Contact holes 10, each of which penetrates firstinterlayer insulating film 8,gate electrode 3 and secondinterlayer insulating film 9, are provided for exposing portions of a surface of firstimpurity diffusion layer 24. Side walls of contact holes 10 are covered withgate insulating films 4. - In each
contact hole 10, there is formed afirst semiconductor layer 11 of the first conductivity type, which is in contact with the surface of firstimpurity diffusion layer 24 and extends from the surface of firstimpurity diffusion layer 24 to the substantially same level as the lower surface ofgate electrode 3. In eachcontact hole 10, there is also formed achannel semiconductor layer 12, which is in contact with the surface offirst semiconductor layer 11 and extends from the surface offirst semiconductor layer 11 to the substantially same level as the upper surface ofgate electrode 3. Onchannel semiconductor layer 12, there is provided a secondconductive layer 13 of the first conductivity type, which is in contact with the surface ofchannel semiconductor layer 12 and forms the other of source/drain regions as well asstorage node 26. The surface of secondconductive layer 13 is covered with acapacitor insulating film 21 formed on secondinterlayer insulating film 9. On secondinterlayer insulating film 9, there is formed acell plate electrode 22 which covers secondconductive layer 13, i.e.,storage node 26 with thecapacitor insulating film 21 therebetween. - Advantages of this embodiment will be described below. Since VΦT is used, the occupied area can be small. Since silicon layer (SOI) or polysilicon layer (poly-SOI) forms bit line (24), bit line (24) is formed on a thick insulating film (201), and thus the capacitance of bit line can be small. As a result, the DRAM performing high-speed operation is obtained.
- Use of SOI achieves such an advantage that channel
semiconductor layer 12 can be formed by epitaxial growth. - Since the bit line capacitance is small, the capacitance of storage node can be small. More specifically, a sense amplifier has sensitivity of a fixed value. Therefore, if a ratio of CS (capacitance of storage node) to C3 (capacitance of bit line) is constant, information can be read. Therefore, if C3 is reduced, CS can be reduced.
- Since the bit line capacitance is small, the open bit line system shown in an equivalent circuit diagram of FIG.16 is allowed, and thus cells of 4F2 can be easily obtained.
- If an ordinary silicon substrate were used, a well would be required to isolate a P-channel and an N-channel from each other. Owing to SOI structure or poly-SOI structure, however, a well is not required, which simplifies a manufacturing process.
- If the ordinary silicon substrate were used, it would be necessary to provide an LOCOS oxide film for isolating adjacent transistors from each other. In the embodiment, however, the adjacent transistors can be isolated from each other only by formation of
bit line 24 as shown in FIG. 2. This also simplifies the manufacturing process. - A leak current does not flow between adjacent bit lines24. Owing to the fact that the leak current does not flow between the bit lines, it is possible to increase a time period between refreshing operations (rewriting operations).
- Owing to the SOI structure, the DRAM can have a higher resistance against soft error as compared with the structure using the ordinary silicon substrate.
- The VΦT structure of transistor can provide the following advantages.
- Referring to FIG. 2, reduction of a radius of
channel semiconductor layer 12 allows depletion of the entire channel. Depletion of the entire channel can suppress a sub-threshold current (leak current at a weakly inverted state), resulting in improvement of circuit characteristics. Also, a sub-threshold coefficient S has a minimum value of 60 mV/dec. - Since
channel semiconductor layer 12 is surrounded by an electric field applied thereto, punch-through can be suppressed. - Owing to suppression of the punch-through, the structure has a high resistance against disturb refresh. Since there is no substrate bias effect, high-speed operation is allowed. Since the channel width can be wide, a large current can flow therethrough.
-
Channel semiconductor layer 12 can be monocrystallized by the epitaxial growth method. According to the process described above, since the word line is formed, and the contact holes are formed in the word line, the word line can be formed easily. Connection can be made easily between the transistor and the bit line and between the transistor and the capacitor. The film thickness of the word line equals the gate length, the gate length can be controlled easily. Since a length of offset of the source depends on the film thickness of firstinterlayer insulating film 8, and a length of offset of the drain depends on the film thickness of secondinterlayer insulating film 9, these lengths can be controlled easily. - Impurity of source/drain can be implanted by a simple ion-implanting process. Likewise, ion implantation for the channel can be performed easily. Since the gate insulating film is formed by oxidation, the gate insulating film does not have a thin portion at the edge of gate. Thus, the leak current does not generate at the edge of gate.
- Description will now be given on a process of manufacturing the DRAM using VΦTs shown in FIG. 2. The manufacturing process will be described with reference to cross sections taken along line A-A in FIG. 3.
- Referring to FIG. 4, one prepares an SOI (Silicon On Insulator)
substrate 90, in which buried SiO2 layer 201 is formed onsilicon substrate 1, and anSOI layer 202 is formed on buried SiO2 layer 201. -
SOI substrate 90 is formed by an appropriate method such as an SIMOX (Separation by Implanted Oxygen) method, ZMR method (Zone Melting Recrystallization) method, laser anneal method or laminating method. The SOI substrate may be replaced with a substrate such as an SOS (Silicon On Sapphire) which is separated by another dielectric member. The SOI substrate may be replaced with a poly-SOI substrate. - Buried SiO2 layer 201 has a film thickness of 5000 Å, and
SOI layer 202 has a film thickness of 2000 521 . SinceSOI layer 202 forms the bit line,impurity 91 is implanted thereinto to reduce its resistance as shown in FIG. 4. If the VΦT is, for example, to be of the P-channel type, the P-type impurity is implanted intoSOI layer 202. - Referring to FIG. 5, an
SiN layer 14 of 1000 Å in thickness is deposited onSOI layer 202. As will be described later, the purpose ofSiN layer 14 is to prevent oxidation of the bottom of contact hole at the step of forming the gate insulating film of VΦT. - Referring to FIG. 6,
SOI layer 202 is patterned to have the configuration of bit lines 24. - The step of implanting impurity shown in FIG. 4, the step of depositing SiN layer shown in FIG. 5 and the step of patterning bit lines shown in FIG. 6 may be carried out in the different orders described below.
- (1) Implantation—SiN—Patterning
- (2) Implantation—Patterning—SiN
- (3) SiN—Implantation—Patterning
- (4) SiN—Patterning—Implantation
- (5) Patterning—Implantation—SiN
- (6) Patterning—SiN—Implantation
- If the steps are performed in accordance with the order (2), (5) or (6) described above, a structure shown in FIG.7 is obtained instead of the structure in FIG. 6. In the structure shown in FIG. 7,
SiN layer 14 having a higher dielectric constant than SiO2 is formed betweenadjacent bit lines 24, so that a capacitance between the bit lines increases. Therefore,SiN layer 14 must have a small film thickness of about 500 Å. - Referring to FIGS. 6 and 8, first
interlayer insulating film 8 of 1000 Å in thickness is deposited on buried SiO2 layer 201 to cover bit lines 24. Polysilicon of 3000 Å in thickness is deposited on firstinterlayer insulating film 8, and then is patterned to form word lines 25. More specifically, word lines 25 are formed by patterning the polysilicon containing impurity implanted thereinto in order to reduce the resistance. The polysilicon containing impurity may be doped polysilicon. Alternatively, impurity may be implanted into non-doped polysilicon. - FIG. 9 is a cross section showing the semiconductor device at the same step as FIG. 8 and taken along line parallel to the bit line, i.e., taken along line B-B in FIG. 3.
- Referring to FIGS. 8 and 9, the film thickness of
word line 25 equals the gate length of VΦT. Since the film thickness ofword line 25 can be controlled easily, good controllability of the gate length can be achieved. - Referring to FIG. 10, second
interlayer insulating film 9 is formed on firstinterlayer insulating film 8 to cover word lines 25. - Then, contact holes10 penetrating second
interlayer insulating film 9, word lines 25 and firstinterlayer insulating film 8 are formed at crossings ofword lines 25 and bit lines 24. - Referring to FIG. 11, oxidation is effected on the side wall of
word line 25 exposed in eachcontact hole 10 to formgate insulating film 4 of VΦT. Sincegate insulating film 4 is formed by oxidation, thegate insulating film 4 is thinned at the upper end of gate electrode (25). - Referring to FIGS. 11 and 12,
SiN layer 14 at the bottom of eachcontact hole 10 is removed by heat phosphoric acid to expose asurface 24 a ofbit line 24. - Referring to FIG. 13, contact holes10 are filled with
amorphous silicon 15.Amorphous silicon 15 is epitaxially grown from the surface of bit lines 24.Monocrystal silicon 92 obtained by this epitaxial growth forms the channel of VΦT. Sincesurface 24 a ofbit line 24 serves as a contact to the bit line, contact can be made very easily between the transistor and bitline 24. - After completion of the epitaxial growth, ion implantation is performed to form the drain and channel of VΦT. Thereafter, the implanted ion diffuses owing to heat treatment during the process, so that
source 6 a anddrain 6 b are formed. Since impurity is introduced intosource 6 a,drain 6 b andchannel 12 by the implantation method, concentration of impurity in these portions can be controlled easily. By controlling the film thicknesses of firstinterlayer insulating film 8 and secondinterlayer insulating film 9, the lengths of offsetportions - Referring to FIG. 15, the drain portion of VΦT is patterned to produce
storage node 26.Capacitor insulating film 21 is formed on secondinterlayer insulating film 9 to coverstorage node 26.Cell plate electrode 22 is formed on secondinterlayer insulating film 9 to coverstorage node 26 withcapacitor insulating film 21 therebetween. In this manner, the DRAM cells using VΦTs are completed. - Since the
drain 6 b of VΦT also serves asstorage node 26, the transistor and capacitor can be connected very easily. The DRAM cells of 4F2 are obtained as described above. - Embodiments 2 to 6 which will described below relate to a method for reducing a resistance of the word line.
Embodiments 7 to 12 relate to a method which reduces the resistance of bit line for enabling high-speed operation of the VΦT-DRAM. - In
embodiment 1, the word line is made of doped polysilicon, and the bit line is made of the SOI layer. Therefore, if a plurality of VΦTs are continuously disposed, the word line and bit line have a high resistance. As can be seen from FIG. 3, the width ofword line 25 is reduced at portions containing VΦTs, which further increases the resistance. The high resistance of the word line and bit line reduces the operation speed of DRAM.Embodiments 2 to 12 have been developed to overcome the above problem. -
Embodiment 2 - FIG. 17 is a cross section of a major portion of a DRAM cell using VΦT of
embodiment 2. The DRAM cell ofembodiment 2 is the substantially same as the DRAM cell shown in FIG. 2 except for the following points. Therefore, portions equal or corresponding to those in the DRAM cell in FIG. 2 are not shown in the figure. Also, the same or corresponding portions bear the same reference numbers, and will not be described below. - In the DRAM cell shown in FIG. 17, the
word line 25 has a two-layer structure formed of apolysilicon 16 and asilicide 17 disposed onpolysilicon 16. The two-layer structure formed ofpolysilicon 16 andsilicide 17 can reduce the resistance ofword line 25, and thus enables the high-speed operation of DRAM. - Material silicide may be tungsten silicide, titanium silicide, cobalt silicide, platinum silicide, molybdenum silicide or others, and alternatively, material other than silicide may be used provided that it has a similar resistivity.
-
Embodiment 3 - FIG. 18 is a cross section of a major portion of a DRAM cell of
embodiment 3. The DRAM cell of this embodiment differs from the DRAM cell shown in FIG. 17 in thatsilicide 17 is formed underpolysilicon 16. Similarly toembodiment 2, sinceword line 25 has the two-layer structure formed of the polysilicon and silicide, theword line 25 has a low resistance. -
Embodiment 4 - FIG. 19 is a cross section of a major portion of a DRAM cell of the
embodiment 4. In this embodiment,silicide 17 is disposed above and belowpolysilicon 16. This structure can further reduce the resistance ofword line 25. - In the case of an n-channel transistor, a threshold voltage Vth of a structure including a gate made of metal or silicide is higher than that of a structure including a gate made of polysilicon by the reason related to a work function. If
word line 25 has the layeredstructure including silicide 17 andpolysilicon 16, the threshold voltage Vth of VΦT can be changed locally. For example, ifsilicide 17 is disposed at the drain side as shown in FIG. 17, thechannel portion 7 surrounded bysilicide 17 has a higher threshold voltage Vth thanchannel portion 7 surrounded bypolysilicon 25, and thus is resistive to inversion. Therefore, punch-through betweensource 6 a anddrain 6 b is advantageously suppressed even if the drain voltage increases. - Conversely, in the case of a p-channel transistor,
channel portion 7 surrounded bysilicide 17 is not sufficiently resistive to the punch-through because its threshold voltage Vth is low. Therefore, as shown in FIG. 20, there is provided aregion 18 containing n-type impurity, which is slightly more than that in an n-channel region 93, so that the punch-through can be prevented. As shown in FIG. 21,word line 25 can have a small resistance at the p-channel 7, and can effectively prevent the punch-through, if it includessilicide 17 disposed between upper and lower layers ofpolysilicon 16. -
Embodiment 5 - FIG. 22 is a perspective view of a major portion of a DRAM cell array of
embodiment 5, and specifically shows the structure at a step corresponding to that in FIGS. 8 and 9. Members and portions other thanword lines 25 andbit lines 24 are not shown in FIG. 22 for simplicity reason. In this embodiment,silicide 17 is disposed not only on the upper surface ofpolysilicon 16 but also on the side surfaces thereof. Thus, three sides ofword line 25 are covered withsilicide 17, so that the resistance ofword line 25 is further reduced. - Then, a method of manufacturing the device shown in FIG. 22 will be described below.
- Referring to FIG. 23, word lines25 are formed on first
interlayer insulating film 8. - Referring to FIG. 24, a sputtering method is performed to cover the surfaces of
word lines 25 with atitanium film 19 of 200 Å in thickness. - Lamp annealing is performed in the atmosphere of N2 at a temperature of 600 to 700° C. for 30 seconds. Referring to FIG. 25,
titanium silicide films 19 a, which are compound of titanium and silicon, are produced only on portions of silicon which were in contact with titanium. Referring to FIGS. 25 and 26,unreacted titanium film 19 is removed. - In this embodiment, titanium has been described as an example. However, other material such as cobalt, platinum or nickel may be used. The manner of forming the silicide only on exposed portions of silicon has been referred to as “salicide”.
- FIG. 27 is a cross section showing VΦTs in which contact holes are formed in
word lines 25 covered withtitanium silicide films 19 a. In this structure, a margin M between the word line and the contact hole of VΦT can be expressed by the following formula. - M=overlap margin of photolithography+silicide film thickness (t1)+film thickness (t2) of portion to be oxidized
- It is necessary to form the contact hole at
word line 25 taking this margin M into consideration. -
Embodiment 6 - This
embodiment 6 relates to a method of forming silicide only on side walls of the word line. - Referring to FIG. 28, SiO2 layer 20 is formed on each
word line 25. Referring to FIG. 29,silicide films 17 are formed on the side walls ofword line 25. Sincesilicide films 17 are formed at the opposite side walls ofword line 25, the resistance ofword line 25 can be reduced. - At the step of forming the contact hole of VΦT, the silicide film does not exist on the top surface of
word line 25. Therefore, it is not necessary to perform the etching for piercing the silicide film, which improves the stability of the process. -
Embodiment 7 - Embodiments 7 to 12 are aimed at reduction of the resistance of bit lines and thus increase of the operation speed of VΦT-DRAM.
- FIG. 30 is a cross section showing an SOI layer30 (BL),
silicide 31 and anSiN layer 32, where are layered in this order and are patterned to have configurations of the bit lines. Implantation of impurity intoSOI layer 30 may be carried out at any step as already described in connection withembodiment 1. -
SiN layer 32 may be deposited after patterningSOI layer 30 andsilicide 31, in which case the device has a section shown in FIG. 31. FIGS. 30 and 31 correspond to FIGS. 6 and 7showing embodiment 1, respectively. - Thereafter, steps similar to those shown in FIGS.8 to 14 are performed to produce a VΦT-DRAM including the bit lines of a low resistance and capable of high-speed operation.
- In this embodiment, the structure has a section shown in FIG. 32 after the steps of forming the contact holes of VΦTs, forming
gate insulating films 4 by oxidation and then removing the SiN film provided for preventing oxidation of the bit lines. In this state, since the upper surface ofSOI layer 30 is covered withsilicide 31, the channel of VΦT will not be monocrystallized even if one performs solid phase growth of amorphous silicon fillingcontact hole 10 in the structure shown in FIG. 32.Embodiment 8 described below is an improvement of the above structure. -
Embodiment 8 - Referring to FIGS. 32 and 33, etching is effected on
silicide 31 at the bottom ofcontact hole 10 of VΦT. Etching ofsilicide 31 exposes surface 30 a ofSOI layer 30, so that the channel of VΦT can be monocrystallized by the epitaxial growth. -
Embodiment 9 - This embodiment relates to a structure in which silicide is disposed under the bit line so as to reduce the resistance of bit line.
- Referring to FIG. 34,
silicide 17 is formed on SiO2 layer 20.Polysilicon 16, which will form bit lines, is formed onsilicide 17. This structure reduces the resistance of bit line. However, the channel of VΦT cannot be monocrystallized by the epitaxial growth if VΦT is formed onpolysilicon 16 because the bit line is made of polysilicon. - In this case, a laminating method enable formation of the bit line which is provided by disposing monocrystal silicon on silicide.
- More specifically, referring to FIG. 35, a
second silicon substrate 34 is laminated to afirst silicon substrate 33 on whichsilicide 17 and SiO2 layer 201 are formed. The laminating is performed by a high temperature heat treatment causing adhesion of them. Thesecond silicon substrate 34 is a mere support substrate, so that its material is not significantly restricted. - Referring to FIGS. 35 and 36, the structure is turned upside down and
first silicon substrate 33 is polished by a chemical mechanical polishing (CMP) method to reduce the thickness. Thereby, a layer (33) for the bit line having the monocrystal silicon layer (SOI layer) is formed onsilicide 17. - Thereafter, the same steps as those in
embodiment 1 are performed, whereby VΦT-DRAM having the channel made of monocrystal is completed, and the resistance of bit line is reduced. -
Embodiment 10 - This embodiment is aimed at further reduction of the resistance of bit line. Referring to FIGS. 36 and 37,
additional silicide 17 is formed onmonocrystal silicon layer 30, so that bit line includes layers ofsilicide 17 at upper and lower sides ofmonocrystal silicon layer 30 and thus has a further reduced resistance. In the device shown in FIG. 35,polysilicon 94 may be interposed betweensilicide 17 and SiO2 layer 20, in which case the bit line can includepolysilicon 30 located undersilicide 17 as well asmonocrystal silicon layer 33 located onsilicide 17. This structure can also reduce the resistance of bit line. -
Embodiment 11 - This embodiment is likewise aimed at reduction of the resistance of bit line.
- Referring to FIG. 39, salicide processing is effected on
SOI layer 30, which will form the bit line, after patterning the same. Thereby, upper and opposite side (right and left) surfaces of bit line (30) is covered withsilicide 17. Since the three surfaces of bit line (30) is covered withsilicide 17, the resistance of bit line can be further reduced. - This embodiment may be combined with
embodiment 9 employing the laminating method, so that four surfaces, i.e., upper, lower and opposite side surfaces of the bit line can be covered with silicide. -
Embodiment 12 - This embodiment is aimed at reduction of the resistance of bit line. Referring to FIG. 40, a
film 35 for preventing silicidation is disposed onSOI layer 30, i.e., bit line. Owing to film 35 disposed onSOI layer 30 for preventing silicidation,silicide 17 can be formed only on the side surfaces ofSOI layer 30, i.e., bit line. Although a resistance of bit line in this structure is higher than that of the structure shown in FIG. 39, the resistance of bit line in this structure can be sufficiently low because the bit line is provided at its opposite sides with silicide. -
Film 35 for preventing silicidation may be an oxide film, and also may be a nitride film formed on the SOI layer similarly to that used inembodiment 1. The latter structure eliminates the step of forming a hole in the silicide similarly toembodiment 8. As a result, a VΦT-DRAM including bit lines of a low resistance can be obtained only by adding the step of silicidation to those inembodiment 1. -
Embodiments 13 to 16, which will be described below, are aimed at reduction of a capacitance of the bit line. -
Embodiment 13 - The
embodiment 13 is aimed at reduction of the capacitance of bit line for attaining high-speed operation of VΦT-DRAM. - Referring to FIG. 41, the bit line capacitance of VΦT-DRAM is nearly equal to a sum of a capacitance361 between bit line and silicon substrate, a capacitance 371 between bit line and bit line, and a capacitance 381 between bit line and word line.
- At the SOI substrate shown in FIG. 41, buried SiO2 layer 20 is located under
bit lines 24, i.e., SOI layer, so thatcapacitance 36 betweenbit line 24 andsubstrate 1 is very small. However, if SIMOX method is used to form the SOI substrate, the film thickness of buried SiO2 layer 20 cannot be determined freely due to the manufacturing method. The film thickness of buried SiO2 layer 20 is about 4000 Å. However, if the SOI substrate of the laminated structure is used, the film thickness of the buried SiO2 layer can be determined freely. Referring to FIG. 42, VΦT-DRAM includes the SOI substrate having buried SiO2 layer 20 of 0.5 μm or more in thickness, in whichcase capacitance 36 betweenbit line 24 andsubstrate 1 is sufficiently small, so that the operation speed of VΦT-DRAM can be increased further. -
Embodiment 14 - This embodiment is aimed at reduction of the capacitance between bit line and word line.
- Referring to FIG. 41, a
portion 25 a ofword line 25 is located in a groove betweenadjacent bit lines 24, so thatcapacitance 38 betweenword line 25 and bitline 24 is large. - FIGS.43 to 45 relate to an improved method of manufacturing a VΦT-DRAM which can reduce the capacitance between bit line and word line.
- Referring to FIG. 43,
grooves 36, each of which is complementary in sectional shape to the bit line, are formed at the surface of buried SiO2 layer 20. Referring to FIG. 44, apolysilicon layer 37 fillinggrooves 36 is formed on buried SiO2 layer 20. Referring to FIGS. 44 and 45, etch-back is effected onpolysilicon layer 37 to formbit lines 24 fillinggrooves 36. By forming VΦT-DRAM onbit lines 24, word lines 25 having flatlower surfaces 25 b are formed, wherebycapacitance 38 betweenbit line 24 andword line 25 can be reduced. -
Embodiment 15 - This embodiment is likewise aimed at reduction of the capacitance between bit line and word line.
- Referring to FIG. 46,
bit lines 24 are formed on buried SiO2 layer 20. Interlayer SiO2 film 38 is deposited on buried SiO2 layer 20 to cover bit lines 24. Interlayer SiO2 film 38 is etched back to attain an intended height, and VΦT-DRAM is formed on interlayer SiO2 film 38 as shown in FIG. 37. Since spaces betweenbit lines 24 are filled with interlayer SiO2 film 38, VΦT-DRAM have a small capacitance betweenbit line 24 andword line 25. Ifbit line 24 in this structure is made of monocrystal, thechannel 7 of VΦT is made of monocrystal. -
Embodiment 16 - This embodiment is likewise aimed at reduction of capacitance between bit line and word line.
- FIG. 48 is a cross section of a VΦT-DRAM of
embodiment 16. Referring to FIG. 48, this embodiment includesbit lines 24 which are isolated from each other by LOCOS oxide films 391. Sinceword line 25 is further isolated frombit line 24 by LOCOS oxide film 391,capacitance 38 betweenbit line 24 andword line 25 can be reduced.Bit lines 24 isolated by LOCOS oxide films 391 can be formed by the following steps. LOCOS oxide films 391 are formed by oxidizing the surface of SOI layer (24) with a mask formed of a silicon nitride film (not shown) which is patterned into a predetermined configuration. Then, impurity is implanted through the silicon nitride film to form bit lines 24. The silicon nitride film used in the LOCOS step will be used again in the step of forming the VΦT gate insulating film by oxidation. - If this embodiment is combined with the structure which includes the bit lines provided with silicide as employed in
embodiment 11, it is necessary to deposit anSiN film 42 again, which is required for forming the gate insulating film of VΦT, after forming silicide layers 40 (TiSi, WSi) on the surface ofbit lines 24 as shown in FIG. 49. -
Embodiment 17 - This embodiment relates to a margin between bit line and VΦT contact as well as a margin between word line and VΦT contact.
- Referring to FIG. 50,
bit line 24 is formed on buried SiO2 layer 20. First interlayer insulatingfilm 8 is formed on buried SiO2 layer to coverbit line 24.Word line 25 is formed on firstinterlayer insulating film 8. Secondinterlayer insulating film 9 is formed on firstinterlayer insulating film 8 to coverword line 25. Anopening 9 a is formed at a position in secondinterlayer insulating film 9, where the contact hole of VΦT is to be formed. Although FIG. 50 shows a structure in which anedge 24 a ofbit line 24 is coincident with an edge (9 a) of the contact hole of VΦT, they may be slightly shifted from each other due to shift of a mask. However, this shift causes no problem as will be described below. - This embodiment will be described below in connection with an example including
bit line 24 having a width of 0.2 μm which corresponds to the minimum allowable line width. - Referring to FIGS. 50 and 51, an SiO2 film 42 of 500 Å in thickness is deposited such that it uniformly covers
opening 9 a in secondinterlayer insulating film 9. Dry etching is effected on SiO2 film 42 to leave an SiO2 film 43 in a side wall form as indicated by dotted line. - Thereafter, the contact hole of VΦT is formed with a mask formed of SiO2 film 43 in the side wall form. FIG. 52 shows a section of
contact hole 10 thus formed taken along line parallel to the word line, and FIG. 53 shows a section of the same taken along line parallel to the bit line. According to this method, as shown in FIG. 52, a margin m1 between VΦT contact and bit line can be ensured within the minimum line width w. Referring to FIG. 53, a margin m2 between VΦT contact and word line can be ensured within the minimum line width w. As a result, the cell size of 4F2 can be further reduced to 4r2 . Here, r represents the minimum line width, and satisfies the relationship of F (feature size)=r+α (process margin). - This method can further reduce the diameter of channel of VΦT, and thus can produce the VΦ-DRAM which operate stably at a high speed and occupies a small area.
-
Embodiment 18 - Embodiment 18A
- This embodiment relates to a method of producing a VΦT-DRAM having a cell size of 4r2.
- FIG. 54 is a plan of a photomask used for forming bit lines or word lines with a phase-shift mask. In FIG. 54, hatched
portions 95 represent portions or shifters at which a phase of light shifts by 180°. A phase shift of light is 0° atportions 96 between adjacent hatchedportions 95. A width W3 of the shifter and a width W4 between the shifters each are double the minimum line width. FIG. 54 shows intensity of light, which is irradiated to the above photomask, on a wafer surface. When the processing is performed with the above photoresist and a negative resist, portions exposed to the light beams will be left after development. Therefore, an exposure time can be appropriately adjusted to form a wide bit line (BL) and a narrow space S defined between bit lines BL within a width (W5) of double the minimum line width. - The word lines may be formed in a similar manner, whereby contact holes of VΦTs of the minimum line width (minimum size) can be formed at the crossings of word lines and bit lines, and thus VΦT-DRAM of the cell size of 4r2 can be formed.
- In this specification, “4F2” contains “4r2” unless otherwise noted.
- Embodiment 18B
- FIG. 56 is a plan showing a photomask used in this embodiment. The photomask consists of 0°-phase shifters, 90°-phase shifters, 180°-phase shifters and 270°-phase shifters. 0°, 90°, 180° and 270° represent phases of light shifted by the phase shifters. Since the intensity of light is 0 at a position where the light beams applied from the four kinds of shifters overlap each other. Therefore, small openings are formed only at vicinities of the crossings of boundaries between the shifters.
- If the contact holes of VΦTs are formed with the photomask shown in FIG. 56 and the negative, contact holes10 can have a size smaller than the minimum size as shown in FIG. 57. In FIG. 57, m2 represents a process margin.
- A method of manufacturing the photoresist shown in FIG. 50 will be described below. Referring to FIG. 57,
first SiN film 90 a, first SiO2 film 90 b,second SiN film 90 c, second SiO2 film 90 d,third SiN film 90 e, third SiO2 film 90 f andfourth SiN film 90 g are deposited on acrystal substrate 90 in this order. A sum of film thicknesses of the SiN films and SiO2 films are determined to correspond to the phase of light of 90°. - Then, a resist90 h is formed on
fourth SiN film 90 g. Resist 90 h is patterned to formopenings 90 i only at portions at which phase shifts of 0°, 90° and 180° are to be set. In FIG. 121, the shifters of 0°, 90°, 180° and 270° are shown as if they are aligned laterally for sake of illustration, the shifters are actually disposed in a matrix form as shown in FIG. 56. - Referring to FIG. 122,
fourth SiN film 90 g and third SiO2 film 90 f are etched using resist 90 h as a mask. In this step,third SiN film 90 e serves as an etching stopper. Therefore, the etching is effected through a constant thickness. After the etching, resist 90 h is removed. - Referring to FIG. 123, a resist90 j is formed on
crystal substrate 90.Openings 90 k are formed only at portions in resist 90 j where phase shifts of 0° and 90° are to be set. Referring to FIG. 124,third SiN film 90 e and second SiO2 film 90 d are etched with a mask formed of resist 90 j. In this step,second SiN film 90 c serves as an etching stopper. After the etching, resist 90 j is removed. - Referring to FIG. 125, a resist901 is formed on
crystal substrate 90. Resist pattern 901 is patterned so thatopenings 90 m may be formed only at portions in resist 901 where phase shift of 0° is to be set. Referring to FIG. 126,second SiN film 90 c and first SiO2 film 90 b are etched with a mask formed of resist 901. In this step,first SiN film 90 c serves as an etching stopper. After the etching, resist 90 is removed, whereby the photomask is completed. - Except for
first SiN film 90 a, nothing exists at the portion of the phase shift of 0° oncrystal substrate 90.First SiN film 90 a, first SiO2 film 90 b andsecond SiN film 90 c exist on the portions of the phase shift of 90°, and the sum of thicknesses of these films corresponds to the phase shift of light equal to 90°. - Therefore, the light beams passed through the portions of phase of 90° have the phase difference of 90° with respect to the portion of the phase of 0°.
- Likewise, the light beams passed through the portions of phases of 180° and 270° have the phase differences of 180° and 270° with respect to the portion of the phase of 0°, respectively.
- Referring to FIG. 127, the photomask shown in FIG. 56 may be obtained also by a method in which the surface of
crystal substrate 90 is shaved by amounts corresponding to respective phase differences by FIB. -
Embodiments 19 to 21 which will be described below are aimed at improvement of the voltage resistance of gate of VΦT. -
Embodiment 19 -
Embodiment 19 is aimed at improvement of the voltage resistance of gate of VΦT. - FIG. 58 is a cross section of the device at a stage after formation of
contact hole 10 which penetrates second interlayer insulating film (SiO2) 9, word line (WL) 3 and first interlayer insulating film (SiO2)film 8 and is provided for exposing the surface of bit line (BL). On the surface of bit line (BL), there is formed a silicon nitride film (SiN) for preventing oxidation of the surface of bit line. - Referring to FIGS. 58 and 59,
gate insulating film 4 is formed by a dry O2 oxidation method at 1100° C., whereby word line (WL) can have around edge 45. The round shape ofedge 45 of word line (WL) can suppress concentration of electric field atedge 45, and thus can improve the voltage resistance of the gate. -
Embodiment 20 - This embodiment is likewise aimed at improvement of the voltage resistance of the gate of VΦT.
- FIG. 60 shows this embodiment. Bit line (BL) is formed on buried SiO2 layer 20. The silicon nitride film (SiN) is formed on bit line (BL). First interlayer insulating film (SiO2) 8 is formed on buried SiO2 layer 20 to cover bit line (BL). Word line (WL) made of doped polysilicon is disposed on first
interlayer insulating film 8. Secondinterlayer insulating film 9 is formed on firstinterlayer insulating film 8 to cover word line (WL).Contact hole 10 penetrates secondinterlayer insulating film 9, word line (WL) and firstinterlayer insulating film 8. Side surfaces of word line (WL) made of doped polysilicon are oxidized to formgate insulating film 4. Referring to FIG. 60, if the doped polysilicon is made of fine or small grains, irregularities are formed on the surface ofgate insulating film 4 in accordance with the face orientation of grains of doped polysilicon, resulting in reduction of the voltage resistance of gate. Accordingly, as shown in FIG. 61, doped amorphous silicon is deposited for depositing the film of word line (WL). Then, anneal is effected at about 600° to grow this doped amorphous polysilicon by solid phase growth into polysilicon formed of grains of a large diameter. Thereby, as shown in FIG. 61,gate insulating film 4 having a high voltage resistance can be formed without irregularities. -
Embodiment 21 - Similarly to
embodiment 20, a film for the word line is deposited in the form of doped amorphous silicon. Then, the contact hole of VΦT is formed while maintaining the form of amorphous silicon. Thereafter, solid phase growth of the amorphous silicon is performed simultaneously with oxidation of gate insulating film. The device including the gate insulating film which is formed in this manner can achieve an effect similarly toembodiment 20, and has the same structure as that shown in FIG. 61. -
Embodiments 22 to 25 are aimed at further improvement of the voltage resistance against punch-through of VΦT for achieving a VΦT-DRAM which is further resistive to the disturb refresh. -
Embodiment 22 - FIG. 62 is a cross section of a VΦT-DRAM of
embodiment 22. If a voltage has been applied tobit line 24 orstorage node 26 has stored electric charges, a depletion layer extends from the source or drain of VΦT. The state where the depletion layer connects the source and drain together is the punch-through state. Assuming that a voltage VR is applied to the drain and the impurity concentration of channel is NA the extension Xdmax of the depletion layer can be expressed by the following formula. - X dmax=(2·K S·∈0(V R÷2φFP)/q·N A)½
- where KS represents a relative dielectric constant of silicon, ∈0 represents a dielectric constant of vacuum, and q represents an elementary quantity of charges. φFP represents quasi Fermi level which is represented by the following formula.
- φFP=(kT/q)·ln·(N A /n i)
- where k represents a Boltzmann's constant, T represents an absolute temperature, and ni represents a true carrier concentration.
- In order to improve the voltage resistance against punch-through, thicknesses (t1 and t2) of the interlayer insulating films located above and below the gate of VΦT are changed in accordance with extension Xdmax of the depletion layer. More specifically, the film thicknesses of first and second interlayer insulating films can be determined to satisfy the following formula.
- Thicknesses (t1 and t2) of interlayer insulating films=Xdmax+impurity diffusion lengths (l1 and l2).
- For example, if the power supply voltage is 1.5V (VR=1.5V) and NA is 1×1018/cm3, Xdmax goes to 700 Å.
- If NA is 1×1017/cm3, Xdmax goes to 2200 Å.
- Assuming that each of the diffusion lengths (l1 and l2) of impurity is 300 Å, the interlayer insulating films in the above case have the film thicknesses of 1000 Å and 2500 Å, respectively.
- By determining the film thicknesses of interlayer insulating film as described above, it is possible to weaken the electric field at the regions (i.e., offset regions) surrounded by the first and second interlayer insulating films in the channel of VΦT, so that punch-through is suppressed and thus the structure becomes resistive to the disturb refresh.
- Interlayer insulating films (8 and 9) may be deposited by an appropriate method such as CVD, in which case the offset region can be formed with significantly good controllability.
- Embodiment 23
- FIG. 63 is a cross section of a VΦT-DRAM of embodiment 23. The DRAM shown in FIG. 63 is the same as the DRAM shown in FIG. 2 except for the following point. Therefore, the same or corresponding portions bear the same reference numbers and will not be described below.
- The device shown in FIG. 63 is provided with
LDD portions 46 a and 46 b instead of offsets in FIG. 62. The LDDs can improve the voltage resistance against punch-through similarly to the offsets. The LDDs are formed as disclosed in the Japanese Patent Application No. 5-345126 (1993), and more specifically, by implanting impurity ions intobit line 24, LDD portion 46 a,channel region 7,LDD portion 46 b andstorage node 26 with various implantation voltages and implantation doses. - They may be formed also by implanting impurity into the LDD portions during the epitaxial growth.
-
Embodiment 24 - This embodiment relates to a method of forming the LDDs utilizing abnormal diffusion of phosphorus.
- FIG. 64 is an impurity profile in the VΦT channel plug taken along line C-C′ in FIG. 62.
- In the case of N-channel, arsenic (As) or phosphorus (P) is generally used as impurity in source and drain, and its distribution forms Gaussian distribution. In contrast to arsenic, phosphorus forms the distribution curve having an extended tail at a low concentration region as shown in the figure. By applying this phenomenon to VΦT, the LDD structure is automatically completed. Thereby, the voltage resistance against punch-through is improved.
- The offsets and LDDs in embodiments 22-24 already described weaken the electric field between the channel and drain, so that they can prevent the parasitic bipolar effect.
-
Embodiment 25 -
Embodiment 25 relates to a structure in which impurity profile of the channel is changed to improve the voltage resistance against punch-through. - FIG. 65 shows an impurity profile of the channel taken along line C-C′ in FIG. 62. As shown in FIG. 65, the channel profile having peaks at opposite ends of the channel is formed by two channel implanting operations (1) and (2) with different implanting depths.
- Extension of the depletion layers from the source and drain can be suppressed at the peaks formed at opposite ends. Since the entire channel of VΦT is depleted or inverted at a region of a low concentration between the peaks, an ideal S-factor is obtained and also a high current drive power is obtained.
- Thereby, the voltage resistance against punch-through can be improved without impairing the advantage of VΦT. In the figure, dotted line (3) shows the curve for comparison which is obtained by only one channel implanting operation.
-
Embodiment 25 -
Embodiment 26 is aimed at suppression of the parasitic bipolar effect. In contrast to an ordinary MOS transistor of which channel potential is fixed at a well potential, the channel potential of VΦT is electrically floated. Therefore, a large number of carriers are accelerated at a high electric field portion between the channel and drain, and impinge against the lattice of silicon. A small number of carriers generated by this impingement are confined in the channel. This is referred to as an impact ionization phenomenon. For example, in the case of VΦT of N-channel, impact ionization caused by acceleration of electrons generates holes, and they are confined in the channel, so that the potential of channel lowers. This induces implantation of new electrons from the source, resulting in increase of the drain current. The drain current thus increased causes further impact ionization and thus positive feedback takes place, so that the electric field between the channel and drain increases. This results in a phenomenon that the drain current increases discontinuously. This is similar to the operation of bipolar transistor, and thus is referred to as a parasitic bipolar effect. The phenomenon that the drain current increases discontinuously makes the operation of VΦT-DRAM unstable. This can be avoided or suppressed, e.g., by weakening the electric field between the channel and drain, or by forming the offsets or LDDs as described in connection with embodiments 22-24. - As shown in FIG. 66, VΦT of P-channel may be used in the memory cell of VΦT-DRAM. In this structure, since the impact ionization efficiency of holes is smaller than that of electrons, the parasitic bipolar effect can be suppressed.
- Embodiment 27
- Embodiments 27 and 28 are aimed at increase of the capacitor capacitance of VΦT-DRAM.
- FIG. 67 shows an upper portion of the contact hole of VΦT filled with amorphous silicon. FIG. 67 does not show components of the VΦT-DRAM other than the capacitor.
Contact hole 10 of VΦT is formed in secondinterlayer insulating film 9.Contact hole 10 is filled withamorphous silicon 15.Amorphous silicon 15 is monocrystallized by epitaxial growth. - Referring to FIGS. 67 and 68, after monocrystallization of the channel portion of VΦT, the monocrystal is etched back to expose the surface of second
interlayer insulating film 9. - Referring to FIGS. 68 and 69,
polysilicon 47 made of grains of a minute diameter is deposited on secondinterlayer insulating film 9. - As a method for increasing a capacitor capacitance, there has been such a method that polysilicon having a significantly irregular surface is used at a storage node for increasing a surface area thereof so as to increase the capacitor capacitance. For example, instead of the polysilicon made of grains of a minute diameter shown in FIG. 69, polysilicon having a significantly irregular surface may be deposited as shown in FIG. 70 and may be processed into a storage node form as shown in FIG. 71.
Storage node 26 thus formed has an irregular upper surface, so that the capacitance of capacitor increases. This method, however, cannot increase the surface area of aside surface 26 a because theside surface 26 a exposed by the etching is flat. - In this embodiment, therefore,
storage node 26 is formed by patterningpolysilicon 47 as shown in FIGS. 69 and 72. Referring to FIGS. 72 and 73, the surface ofstorage node 26 is oxidized. Grain boundaries of polysilicon is oxidized at a higher speed than the gains, so that the gain boundaries of polysilicon are oxidized more rapidly than the others. As a result, irregularities corresponding to the sizes of grains are formed at the upper and side surfaces ofstorage node 26. - An SiO2 film 99 formed at the surface of
storage node 26 can be used as the capacitor insulating film as it is. Alternatively, as shown in FIG. 74, the SiO2 film may be removed, and then film 49 having a high dielectric constant such as double layer of SiN and SiO2 may be formed. - Since the above method can provide the irregularities also at the side surfaces of
storage node 26, the capacitance of capacitor can be sufficiently increased. The storage node described above may be applied to DRAMs other than the VΦT-DRAM. - Embodiment 28
- This embodiment relates to a structure in which highly dielectric material is used for increasing the capacitor capacitance. Referring to FIGS. 68 and 75, a
titanium nitride film 50 is deposited after the etch-back of amorphous silicon, and afirst platinum film 51 is deposited thereon. Then, these films are processed into a form ofstorage node 26. Then, a highly dielectric film (Ba, Sr) TiO3 film 52 is deposited on secondinterlayer insulating film 9. Asecond platinum film 53 is deposited on (Ba, Sr) TiO3 film 52.Cell plate 22 of polysilicon is formed onsecond platinum film 53. - In the DRAM cell of 4F2, since the capacitor requires only a very small area, it is effective to use the highly dielectric film such as (Ba, Sr) TiO3 film for increasing the capacitor capacitance. This embodiment has been described in connection with an example using (Ba, Sr) TiO3 film as the highly dielectric film, the invention is not restricted to this, and other highly dielectric films may be used.
- Embodiment 29
- This embodiment relates to increase of the degree of integration above 4F2 or 4r2.
- Referring to FIG. 76, contact holes10 of VΦTs are disposed at apexes of triangles with sides, each of which has a length equal to twice the minimum line width. This disposition attains the highest disposition density of contact holes 10 of VΦTs. An
area 100 of one cell in this structure is equal to 2(3)½r2, i.e., nearly 3.5r2, so that the degree of integration of cells are much higher than 4r2 inembodiments - In the DRAM cell array formed of the above cells, adjacent cells must be connected by word lines (WL) and bit lines (BL). A width W4 of (3)½r, i.e., nearly 1.73r can be used for forming word line (WL) and bit line (BL).
- For forming bit line (BL), a minimum required width is generally 2r which is a sum of the width (r) of bit line and a width (r) between the bit lines, and thus 1.73r is insufficient. Likewise, for forming word line (WL), a minimum required width is generally 2r which is a sum of the width (r) of word line and a width (r) between the word lines, and thus 1.73r is insufficient.
- Therefore, the cell of 3.5r2 cannot be obtained. However, if the word lines and bit lines are pattered with a mask which is provided with phase shifters enabling shift of the phase by 180° with a space of 1.73r, the bit lines and word lines can be formed as shown in FIG. 77, and thus the cell of 3.5r2can be obtained.
-
Embodiment 30 - Embodiments 30 and 31 relate to a layout of a peripheral circuitry.
- The cell array of 4F can generally provide only a small space for a peripheral circuitry. As shown in FIG. 78, sense amplifiers may be disposed at vertically opposite sides of the memory cells such that the sense amplifiers disposed at the same side (i.e., upper or lower side) are connected to alternate bit lines BL. Also, decoders may be disposed at laterally opposite sides of the memory cells such that the decoders disposed at the same side (i.e., right or left side) are connected to alternate word lines WL. This disposition increases the space for the peripheral circuitry. The above manner of disposition may be applied only to the sense amplifiers or the decoders.
-
Embodiment 31 - This embodiment relates to a manner of connection in the case where contact must be made at a very deep position between adjacent VΦTs in the DRAM cell array or peripheral circuitry.
- Referring to FIG. 79, in the case where contact is to be made at a very deep position between the adjacent VΦTs, it is very difficult to make direct contact with an
aluminum interconnection 54, and also aluminum interconnection may break. - Accordingly, as shown in FIG. 80, a
dummy VΦT 57 is disposed between afirst VΦT 55 and asecond VΦT 56, so that the contact ofaluminum interconnection 54 can be made easily. - However,
channel portion 7 of the dummy VΦT must contain impurity of the same conductivity type as the source and drain at a high concentration as shown in FIG. 80. -
Embodiment 32 -
Embodiment 32 relates to a process of producing the peripheral circuitry of VΦT-DRAM formed of SOI transistors. - Referring to FIG. 81, one prepares a substrate including buried SiO2 layer 20 and SOI layers 30 formed on
silicon substrate 1.SOI layer 30 is patterned to form simultaneously anactive region 58 of SOI transistor and bit line BL of the cell array of VΦT-DRAM. In this embodiment, dry etching is effected topattern SOI layer 30 for isolatingactive region 58 and bit line BL from each other. However, they may be isolated by an LOCOS oxide film as is done inembodiment 16. - Simultaneous patterning of
active region 58 of SOI transistor and the bit line of VΦT-DRAM simplifies the steps. - Referring to FIG. 82, a
gate insulating film 59 and agate electrode 60 of SOI transistor are formed. Referring to FIG. 83,side wall spacers 101 are formed at respective side walls ofactive region 58,gate electrode 60 and bit line BL. Ions are implanted into source/drain regions - Referring to FIG. 84, silicidation is simultaneously effected on the surfaces of
source 102 a,gate electrode 60 and drain 102 b of SOI transistor as well as the surface of bit line BL to formsilicide films 62 on the respective surfaces. Simultaneous silicidation of the respective surfaces simplifies the steps. Thereafter, the VΦT-DRAM is formed on bit line BL. - Then, another process of producing the peripheral circuitry of VΦT-DRAM formed of SOI transistors will be described below.
- Referring to FIG. 128, a buried SiO2 film 80 a is disposed on a
substrate 80. Asource 80 b, achannel 80 c and adrain 80 d of an SOI transistor as well as asource 80 e of VΦT are disposed on buried SiO2 film 80 a. Agate 80 f of VΦT is disposed onsource 80 e of VΦT. There is also provided achannel 80 g ofVΦT penetrating gate 80 f of VΦT. -
Channel 80 g of VΦT is formed by crystallization of filled amorphous silicon. Then,channel implantation 80 h for VΦT is performed. Ifchannel implantation 80 h for VΦT were performed on the whole surface, impurity used in channel implantation for VΦT would be introduced even intochannel 80 c of SOI transistor, resulting erroneous change of the threshold of SOI transistor. This may be avoided by performing the channel implantation for VΦT with a photoresist covering the SOI transistor portion. However, this requires an additional mask, resulting in increase of the manufacturing cost. - In order to avoid the above problem, a
dummy pattern 80 i of the gate of VΦT is disposed abovechannel 80 c of SOI transistor as shown in FIG. 129. Owing todummy pattern 80 i of the gate of VΦT, the impurity is not introduced intochannel 80 c of SOI transistor even if channel implantation for VΦT is effected on the whole surface. Since this method does not use a mask, the manufacturing cost does not increase. -
Embodiment 33 - This embodiment relates to a layer structure in which upper and lower VΦT-DRAMs commonly use the bit lines. FIG. 85 is a cross section of the V<T-DRAMs of
embodiment 33. Afirst VΦT 63 is formed abovebit line 24, and acapacitor 64 of a trench type is connected to the upper side of the first VΦT. Asecond VΦT 65 is connected to the lower side ofbit line 24. Asecond capacitor 65 of the trench type is connected to the second VΦT. This layer structure is formed by laminatingmemory cells - In this embodiment, only one step is required for forming the bit line. Therefore, the number of steps is reduced, and thus the cost is reduced. Since the thickness is reduced by a size corresponding to one layer of bit line, the height of memory cell portion can be small, and thus a difference in height between the memory cell portion and the peripheral circuitry can be small. This facilitates manufacturing of the semiconductor device. Further, the capacitance coupling between interconnections can be reduced, and thus high-speed operation and high performance can be achieved. In the case where the laminating manner is employed, the channel can be monocrystallized.
-
Embodiment 34 - In a transistor of the conventional SCI structure, it is difficult to fix an electrode of a body. This results in the following problem, which is referred to as “latch”. In FIG. 86, a curve (a) represents electrical characteristics of an ordinary bulk Si transistor. A curve (b) represents electrical characteristics of a transistor of the SOI structure. In the transistor of SOI transistor, a drain current rapidly increases after a gate voltage increases to and above a certain value, which is different from the characteristics (a) of the ordinary bulk Si transistor. This phenomenon is probably caused by the following reason.
- Referring to FIG. 87, when a positive voltage is applied to a
gate electrode 305,electrons 307 flow along the surface of abody 301 from asource 302 to adrain 303. At the vicinity ofdrain 303, where the electric field is strong, accelerated electrons impinge against the crystal lattice of silicon, so that electron/hole pairs generate, and in other words, a phenomenon referred to as “impact ionization” occurs. Although electrons thus generated are absorbed bydrain 303,holes 306 are stored inbody 301 to raise the potential ofbody 301. As the potential ofbody 301 rises, further electrons are implanted fromsource 302, so that the above phenomenon acts in the manner of positive feedback, and the drain current excessively flows. This problem is caused by the fact thatbody 301 is floating. -
Embodiment 34 has been developed to overcome the above problem. - FIG. 88 is a cross section of VΦT of
embodiment 34.Substrate 1 is provided at its main surface with firstimpurity diffusion layer 6 a forming one of source/drain regions. First interlayer insulatingfilm 2 a is disposed onsubstrate 1.Gate electrode 3 is disposed on firstinterlayer insulating film 2 a. Secondinterlayer insulating film 2 b coveringgate electrode 3 is disposed on firstinterlayer insulating film 2 a. There is providedcontact hole 19, which penetrates firstinterlayer insulating film 2 a,gate electrode 3 and secondinterlayer insulating film 2 b, and exposes a portion of the surface of firstimpurity diffusion layer 6 a.Gate insulating film 4 covers the side wall ofcontact hole 19. The device is provided with a siliconthin film 39 which is contact with firstimpurity diffusion layer 6 a. Siliconthin film 39 continuously covers the side wall ofcontact hole 19 with the gate insulating film therebetween and has a concave portion atcontact hole portion 19. Siliconthin film 39 is divided into three regions, i.e.,cylindrical channel region 7 surrounded bygate electrode 3 as well assource region 6 aa and drainregion 6 b, which are located above and belowchannel region 7, respectively. Asilicon oxide film 32 fills a portion of the concavity of siliconthin film 39 lower than the upper end ofchannel region 7.Body polysilicon 66 fills a portion of the concavity of siliconthin film 39 located abovesilicon oxide film 32.Body polysilicon 66 is in contact withchannel region 7. By usingbody silicon 66 as a lead electrode, the potential ofchannel region 7 is fixed.Body polysilicon 66 is in contact with analuminum electrode 68 via abody contact 67 disposed in asilicon oxide film 103. A P+-layer 69 is formed at the surface ofbody polysilicon 66. Ohmic connection is made betweenaluminum electrode 68 andbody polysilicon 66 via P+-layer 69. - The device shown in FIG. 88 is manufactured as follows.
- Referring to FIG. 89, the interior of
contact portion 19 is filled withsilicon oxide film 32, and the surface ofsilicon oxide film 32 is shaved off by etching to expose the top end ofchannel region 7. Referring to FIGS. 89 and 90,body polysilicon 66 to which P-type impurity is added is deposited on the entire surface by the LPCVD method.Body polysilicon 66 has at least such a film thickness that it completely fillscontact hole 19.Body polysilicon 66 is etched to an extent that exposesdrain region 6 b. Thereby,body polysilicon 66 is correctly located incontact hole 19. Referring to FIG. 88 again,silicon oxide film 103 is deposited, andbody contact 67 is opened. Arsenic is implanted into the opening to form P+-layer 69 on the surface of body contact in a self-alignment manner.Aluminum electrode 68 is connected to P+-layer 69. - The above embodiment has been described in connection with the structure in which
aluminum electrode 68 is in contact withbody polysilicon 66. However, the present invention is not restricted to this structure. Polysilicon may be used instead of aluminum. - From only FIG. 90, it seems difficult to detect an end point when etching
body polysilicon 66. In practice, however, drainregion 6 b is patterned, and secondinterlayer insulating film 2 b is exposed at almost entire region. Therefore, the end point can be determined when secondinterlayer insulating film 2 b is exposed, and thus any practical problem does not arise. -
Embodiment 35 - FIG. 91 is a cross section of VΦT of
embodiment 35. This embodiment differs fromembodiment 34 in thatpolysilicon 66 does not completely fillcontact hole 19. Even this structure can fix the potential ofchannel region 7. In this embodiment, however, connection between the aluminum electrode andbody polysilicon 66 cannot be made above the transistor, and thus connection of aluminum must be made at a position other than the transistor. Inembodiment 34, deposited body polysilicon must be thick. Meanwhile,embodiment 35 has an advantage that it can be thin. - In
embodiments - According to the
embodiments -
Embodiment 36 - In VΦT disclosed in Japanese Patent Application No. 5-345126, the diameter of cylindrical or columnar body of VΦT directly depends on the inner diameter of contact hole. Therefore, VΦT cannot have the body of a diameter smaller than the minimum hole diameter attainable by the lithography technique. If the diameter of body is large, the drain end has a large junction area, so that a large leak current flows in proportion to the junction area. If the body is thick, it is difficult to achieve complete depletion of the same, so that the drain current cannot be increased sufficiently.
- This embodiment has been developed to overcome the above problem.
- Referring to FIG. 92,
silicon nitride film 12 of 500 Å. in thickness is deposited on n−-type substrate 1.Silicon nitride film 12 is patterned into a predetermined configuration. Portions not covered withsilicon nitride film 12 are oxidized to form isolatingoxide film 13 at the main surface ofsubstrate 1. Impurity is implanted into the main surface ofsubstrate 1 throughsilicon nitride film 12 to form source/drain region 6. First interlayer insulatingfilm 2 a of 200 Å in thickness is formed onsubstrate 1 to coversilicon nitride film 12 and isolatingoxide film 13. Polysilicon of 500 Å in thickness is deposited on firstinterlayer insulating film 2 a and is patterned to formgate electrode 3. Secondinterlayer insulating film 2 b of 2000 Å in thickness is deposited onsubstrate 1 to covergate electrode 3.Contact hole 8, which penetrates firstinterlayer insulating film 2 a,gate electrode 3 and secondinterlayer insulating film 2 b, is formed for exposingsurface 9 a ofsilicon nitride film 12.Polysilicon 70 containing n-type impurity added thereto and having a thickness of 200 nm is deposited by the LP-CVD method. - Referring to FIGS. 92 and 93, the entire surface of
polysilicon 70 is etched by the anisotropic dry etching method, so that aside wall 71 of polysilicon having a thickness of 200 nm is formed on the inner wall ofcontact hole 8. Assuming that the inner diameter ofcontact hole 8 is 600 nm, a space remaining in the contact hole has the inner diameter of 200 nm. - Referring to FIG. 94, the surface of
side wall spacer 71 is oxidized by the thermal oxidation method at 800° C. to 1000° C., so thatgate insulating film 4 made of a silicon oxide film is formed. At this step, the surface ofsilicon substrate 1 at the bottom ofcontact hole 8 is not covered withsilicon nitride film 12, and thus is not oxidized. Referring to FIGS. 94 and 95,silicon nitride film 12 exposed at the bottom of contact hole is removed with phosphoric acid solution. - At this step, etching progresses also in the lateral direction. Therefore, excessive etching may remove
silicon nitride film 12 located underside wall spacer 71, so that theside wall spacer 71 will be in contact with channel polysilicon which will be deposited in a later step. Therefore, it is important not to perform the excessive etching with phosphoric acid. If any problem may arise, it is preferable to employ the anisotropic dry etching. In this case, however,gate insulating film 4 is also etched, so that this etching must be performed under the conditions that the etching select ratio of silicon oxide film and silicon nitride film is large and damage is suppressed. - Referring to FIG. 95,
silicon 103 which will form the body of transistor is deposited by the LP-CVD method to fillcontact hole 8. Thereafter,silicon 103 is crystallized by solid-phase growth method (anneal at 600° C.). Thereafter, impurity is introduced into the surface of silicon to formdrain region 6 b. In the case of P-channel, P-type impurity such as boron is implanted with the implantation energy of 8 keV and concentration of 5×1015/cm3. The heat treatment is effected at 850° C. for 30 seconds, so that impurity diffuses fromsource region 6 intosilicon 103, and also diffuses fromdrain region 6 b intosilicon 103. In this manner, VΦT is completed. In this embodiment, sinceside wall spacer 71 of polysilicon is formed at the inner wall ofcontact hole 8, the diameter of cylindrical orcolumnar channel 7 is smaller than the inner diameter ofcontact hole 8 by twice the sum of the thickness ofside wall spacer 71 and the thickness ofgate insulating film 4. Sinceside wall spacer 71 of polysilicon is in contact withgate electrode 3, it isside wall spacer 71 that functions as the gate of transistor, and no problem arises in connection with the operation. -
Embodiment 37 - FIG. 96 is a cross section of VΦT of
embodiment 37. - In VΦT shown in FIG. 95,
side wall spacer 71 has an upper end at the same level as the upper surface of secondinterlayer insulating film 2 b. In this structure,drain portion 6 b and the gate (side wall spacer 71) overlap each other through a large area, so that capacitance increases and thus such problems may arise that the operation speed of circuit decreases and that the leak current induced by the drain voltage increases. This embodiment has been developed to over come these problems. - Referring to FIG. 96, the upper end of
side wall spacer 71, i.e., second gate is positioned at the level lower than the upper surface of secondinterlayer insulating film 2 b. This structure eliminates the overlapping ofdrain portion 6 b and gate (side wall spacer 71), so that the above problems are overcome. However, the junction area ofdrain 6 b andchannel 7 directly depends on the inner diameter ofcontact hole 8 and thus increases as described previously. - Embodiments 36 and 37 have been described in connection with the examples in which the upper portion forms the drain and the lower portion forms the source. However, the opposite relationship may be employed. Particularly,
embodiment 37 may employ the drain located at the lower position, in which case the junction area of the drain end can be small and thus the leak current can be reduced. If this structure employs thicksilicon nitride film 12, an electrostatic capacitance ofdrain 6 b and gate (71) can be small. Since the thickness ofsilicon nitride film 12 must be at least twice the thickness of the silicon oxide film which isgate insulating film 4, because the dielectric constant of silicon nitride film is twice as large as that of silicon oxide film (capacitance=dielectric constant/film thickness). - In this embodiment, since the side wall spacer of silicon is formed at the inner wall of contact hole and is used as the gate electrode, the diameter of the channel portion of body can be small. As a result, the leak current can be reduced, and the drain current in the on-state can be large.
-
Embodiment 38 - This embodiment relates to a 2-input OR circuit using VΦT.
- Referring to FIG. 97, if a contact hole of VΦT is formed over two gates, i.e., first and
second gates contact hole 97 of VΦT shifts upward in FIG. 97, afirst channel 104 becomes wide, and asecond channel 105 becomes narrow. If it shifts oppositely,first channel 104 becomes narrow, andsecond channel 105 becomes wide. - In FIG. 98, an amount of shift or displacement of the mask can be electrically determined by comparison between values of current which flow between VCC and GND when only
first gate 72 is turned on and when onlysecond gate 73 is turned on. If the circuit is used for detecting the shift of mask, the load is not required in FIG. 98. If the contact hole of VΦT has another shape, the channel width changes in a different manner in accordance with the change of shift, so that the sensitivity can be changed. - Similarly to the above embodiment, the contact hole of VΦT is disposed at the crossing of gates which are patterned into a cross shape as shown in FIG. 99. Thereby, a 4-input OR circuit is completed as shown in FIG. 100. The contact hole of VΦT may have another shape to form an OR circuit having more inputs.
-
Embodiment 39 - This embodiment relates to formation of a 2-input AND circuit using VΦT.
- FIG. 101 is a cross section of an AND circuit using VΦT of
embodiment 39. There is provided a first SiO2 film 75 covering GND. Afirst gate 76 is disposed on first SiO2 film 75. A second SiO2 film 77 coveringfirst gate 76 is disposed on first SiO2 film 75. Asecond gate electrode 78 is disposed on second SiO2 film 77. A third SiO2 film 79 coveringsecond gate electrode 78 is disposed on second SiO2 film 77.Contact hole 10, which penetrates third SiO2 film 79,second gate electrode 78, second SiO2 film 77,first gate electrode 76 and first SiO2 film 75, is provided for exposing the surface of GND. An N+-semiconductor layer 106, an N−-semiconductor layer 107 and an N+-semiconductor layer 108 are formed successively incontact hole 10. A p31-semiconductor layer surrounded byfirst gate electrode 76 is a first channel, and a p−-semiconductor layer surrounded bysecond gate electrode 78 is a second channel. - By providing the contact hole of VΦT penetrating two
gates - If the interlayer film (second SiO2 film 77) between two gates is thin as shown in FIG. 101, it is not necessary to introduce impurity of the same conductivity type as the source/drain into a portion between channels of VΦTs with a high concentration. If second SiO2 film 77 is thick as shown in FIG. 102, it is necessary to introduce impurity of the same conductivity type as the source/drain into the portion between two channels. The impurity may be introduced by ion implantation or epitaxial growth.
- As shown in FIG. 104, a
second VΦT 81 may be formed on afirst VΦT 80. - In the circuits in
embodiments -
Embodiment 40 - FIG. 105 is a cross section of a semiconductor device of
embodiment 40, in which a VΦT of P-channel and a VΦT of N-channel are vertically aligned to form an inverter circuit. In order to eliminate P-N junction formed between these VΦT,silicide 82 is interposed between them. - In order to monocrystallize the channel of P-channel VΦT, an opening82 a is formed at a portion of
silicide 82. However, if it is not necessary to monocrystallize the channel of P-channel VΦT, it is not necessary to provideopening 82 a atsilicide 82. - Embodiment 41
- FIG. 106 is a cross section of a semiconductor device of embodiment 41. Referring to FIG. 106, two VΦT has such a structure that a gate of a first VΦT is commonly used as a source of a second VΦT, and that a drain of the first VΦT is commonly used as a gate of the second VΦT. Thereby, a circuit shown in FIG. 107 is completed. A flip-flop can be formed, if the above structure is formed of a P-channel VΦTs and an N-channel VΦTs in this manner and is connected as shown in FIG. 108.
- In FIG. 106, the gate of first VΦT must be made of monocrystal in order to provide the channel of second VΦT made of monocrystal. The gate of first VΦT made of monocrystal is laminated to the SiO2 film from the layer on the source of first VΦT, so that the gate of first VΦT made of monocrystal is obtained.
-
Embodiment 42 - This embodiment relates to a gain cell using VΦT.
- Referring to FIG. 109, a VΦT is formed on a gate electrode of an MOS transistor of bulk, so that a circuit shown in FIG. 110 is formed to complete a gain cell, in which electric charges stored in the storage node can be amplified for reading out. The write operation is performed with the word line and the write bit line similarly to a DRAM.
- When electric charges stored in the storage node are to be read out, a word line voltage and a write bit line voltage are changed as shown in FIG. 111. If the storage node has been charged, the MOS transistor is immediately turned on, and a current immediately flows to the read bit line. However, if the storage node has not stored electric charges, it is necessary to supply electric charges enough for turning on the MOS transistor from the write bit line, so that the current does not immediately flow through the read bit line. The threshold voltage Vth of MOS transistor is set at a high value in order to prevent flow of leak current through the MOS transistor when the cell is not accessed. In the MOS transistor, the current is significantly amplified and changed even if the quantity of electric charges in gate changes slightly, so that the detection sensitivity to the quantity of gate electric charges is very high.
- When the electric charges in gate are detected, the write bit line voltage is changed for performing the rewrite operation.
- Similarly to the DRAM, the gain cell must periodically repeat the read operation for refreshing data because the leak current of VΦT causes leak of charges from the storage node. This circuit operation may be performed by a circuit shown in FIG. 101 or other structures equivalent to the same.
- The MOS transistor may use an SOI transistor.
- As shown in FIG. 112, a structure, which is upside-down with respect to that in FIG. 109, may be employed.
- In the device shown in FIG. 109, since the contact of VΦT is located above the doped polysilicon of MOS transistor, the channel of VΦT cannot be monocrystallized by epitaxial growth. In the device shown in FIG. 112, however, the channel of VΦT can be monocrystallized by epitaxial growth. In this case, the MOS transistor at the upper position may be a polysilicon TFT.
-
Embodiment 43 - FIG. 113 conceptively shows a device of
embodiment 43. As shown in FIG. 113, VΦTs may be applied to matrix of a liquid crystal display. - More specifically, the storage node portions in the DRAM cell array shown in FIG. 3 are replaced with pixel electrodes, whereby the structure shown in FIG. 113 is obtained.
- According to the semiconductor device of the first aspect of the invention, since the semiconductor layer formed on the dielectric layer is used as the bit line, the dynamic random access memory can have the bit lines of a small capacitance and can operate at a high speed.
- According to the semiconductor device of the second aspect of the invention, since the dummy VΦT is used, the contact of the aluminum interconnection can be made easily.
- According to the semiconductor device of the third aspect of the invention, since the bit line is commonly used by the upper and lower VΦTs, the bit lines can be formed only by one step. This reduces the number of steps and thus can reduce the cost.
- According to the semiconductor device of the fourth aspect of the invention, there is provided the polysilicon which fills the concave portion of the silicon thin film and is in contact with the channel portion, and this polysilicon is used as the lead electrode. Therefore, the potential of channel portion can be fixed.
- According to the semiconductor device of the fifth aspect of the invention, since there is provide the conductive member covering the side wall of contact hole, it is possible to manufacture the VΦT having the body of which diameter is smaller than the minimum hole diameter attainable by the lithography technique. Consequently, the body can be depleted completely.
- According to the semiconductor device including the OR circuit of the sixth aspect of the invention, since the contact hole of VΦT is formed over two gates, the circuit can be formed in a very small area.
- According to the semiconductor device including the AND circuit of the seventh aspect of the invention, since the AND circuit is formed of the VΦT, the occupied area can be small.
- According to the semiconductor device including the inverter of the eighth aspect of the invention, since the VΦT is used, the occupied area can be small.
- According to the semiconductor device including the flip-flop circuit of the ninth aspect of the invention, since the VΦT is used, the occupied area can be small.
- According to the semiconductor device including the gain cell of the tenth aspect of the invention, since the VΦT is used, the occupied area can be small.
- According to the semiconductor device including the matrix of the liquid crystal display of the eleventh aspect of the invention, since the VΦT is used, the occupied area can be small.
- According to the method of manufacturing the semiconductor device of the twelfth aspect of the, invention since the semiconductor layer formed on the dielectric member is used as the bit line, the capacitance of the bit line can be small.
- Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
Claims (44)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/908,607 US6383860B2 (en) | 1994-05-26 | 2001-07-20 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6-112997 | 1994-05-26 | ||
JP11299794A JP3745392B2 (en) | 1994-05-26 | 1994-05-26 | Semiconductor device |
US31347294A | 1994-09-27 | 1994-09-27 | |
US08/648,828 US5627390A (en) | 1994-05-26 | 1996-05-16 | Semiconductor device with columns |
US08/758,841 US5780888A (en) | 1994-05-26 | 1996-12-02 | Semiconductor device with storage node |
US09/038,981 US6150688A (en) | 1994-05-26 | 1998-03-12 | Semiconductor device and method of manufacturing the same |
US09/660,448 US6303425B1 (en) | 1994-05-26 | 2000-09-12 | Semiconductor device and method of manufacturing the same |
US09/908,607 US6383860B2 (en) | 1994-05-26 | 2001-07-20 | Semiconductor device and method of manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/660,448 Continuation US6303425B1 (en) | 1994-05-26 | 2000-09-12 | Semiconductor device and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010041438A1 true US20010041438A1 (en) | 2001-11-15 |
US6383860B2 US6383860B2 (en) | 2002-05-07 |
Family
ID=14600849
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/648,828 Expired - Lifetime US5627390A (en) | 1994-05-26 | 1996-05-16 | Semiconductor device with columns |
US08/758,841 Expired - Lifetime US5780888A (en) | 1994-05-26 | 1996-12-02 | Semiconductor device with storage node |
US09/038,981 Expired - Lifetime US6150688A (en) | 1994-05-26 | 1998-03-12 | Semiconductor device and method of manufacturing the same |
US09/660,448 Expired - Lifetime US6303425B1 (en) | 1994-05-26 | 2000-09-12 | Semiconductor device and method of manufacturing the same |
US09/908,607 Expired - Fee Related US6383860B2 (en) | 1994-05-26 | 2001-07-20 | Semiconductor device and method of manufacturing the same |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/648,828 Expired - Lifetime US5627390A (en) | 1994-05-26 | 1996-05-16 | Semiconductor device with columns |
US08/758,841 Expired - Lifetime US5780888A (en) | 1994-05-26 | 1996-12-02 | Semiconductor device with storage node |
US09/038,981 Expired - Lifetime US6150688A (en) | 1994-05-26 | 1998-03-12 | Semiconductor device and method of manufacturing the same |
US09/660,448 Expired - Lifetime US6303425B1 (en) | 1994-05-26 | 2000-09-12 | Semiconductor device and method of manufacturing the same |
Country Status (4)
Country | Link |
---|---|
US (5) | US5627390A (en) |
JP (1) | JP3745392B2 (en) |
KR (1) | KR100200222B1 (en) |
DE (1) | DE4443968B4 (en) |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060046440A1 (en) * | 2004-09-01 | 2006-03-02 | Nirmal Ramaswamy | Methods of forming layers comprising epitaxial silicon |
US20060046394A1 (en) * | 2004-09-01 | 2006-03-02 | Nirmal Ramaswamy | Forming a vertical transistor |
US20060051941A1 (en) * | 2004-09-01 | 2006-03-09 | Micron Technology, Inc. | Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors |
US20060278910A1 (en) * | 2005-06-13 | 2006-12-14 | Leonard Forbes | Vertical transistor, memory cell, device, system and method of forming same |
US7528424B2 (en) | 2004-09-01 | 2009-05-05 | Micron Technology, Inc. | Integrated circuitry |
CN101933135A (en) * | 2008-01-29 | 2010-12-29 | 日本优尼山帝斯电子株式会社 | Semiconductor storage device and memory embedded semiconductor device, and manufacturing method thereof |
US20120175625A1 (en) * | 2011-01-12 | 2012-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
KR20120135412A (en) * | 2010-02-19 | 2012-12-13 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor memory device, driving method thereof, and method for manufacturing semiconductor device |
US9685526B2 (en) | 2014-02-12 | 2017-06-20 | International Business Machines Corporation | Side gate assist in metal gate first process |
CN110828497A (en) * | 2019-11-19 | 2020-02-21 | 上海华力微电子有限公司 | Vertical gate CMOS image sensor and manufacturing method |
KR20210030997A (en) * | 2016-08-31 | 2021-03-18 | 마이크론 테크놀로지, 인크. | Ferroelectric memory cells |
US11205468B2 (en) | 2016-08-31 | 2021-12-21 | Micron Technology, Inc. | Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory |
WO2023284123A1 (en) * | 2021-07-16 | 2023-01-19 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing same |
US11901005B2 (en) | 2017-07-13 | 2024-02-13 | Micron Technology, Inc. | Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells |
Families Citing this family (172)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3745392B2 (en) | 1994-05-26 | 2006-02-15 | 株式会社ルネサステクノロジ | Semiconductor device |
US5700727A (en) * | 1995-07-24 | 1997-12-23 | Micron Technology, Inc. | Method of forming a thin film transistor |
US5668391A (en) * | 1995-08-02 | 1997-09-16 | Lg Semicon Co., Ltd. | Vertical thin film transistor |
JP3759648B2 (en) * | 1996-03-04 | 2006-03-29 | 株式会社ルネサステクノロジ | Semiconductor memory device |
US5929476A (en) | 1996-06-21 | 1999-07-27 | Prall; Kirk | Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors |
US6674470B1 (en) * | 1996-09-19 | 2004-01-06 | Kabushiki Kaisha Toshiba | MOS-type solid state imaging device with high sensitivity |
US6540466B2 (en) * | 1996-12-11 | 2003-04-01 | Applied Materials, Inc. | Compact apparatus and method for storing and loading semiconductor wafer carriers |
US5792690A (en) * | 1997-05-15 | 1998-08-11 | Vanguard International Semiconductor Corporation | Method of fabricating a DRAM cell with an area equal to four times the used minimum feature |
US6072209A (en) | 1997-07-08 | 2000-06-06 | Micro Technology, Inc. | Four F2 folded bit line DRAM cell structure having buried bit and word lines |
US6191470B1 (en) | 1997-07-08 | 2001-02-20 | Micron Technology, Inc. | Semiconductor-on-insulator memory cell with buried word and body lines |
US6150687A (en) | 1997-07-08 | 2000-11-21 | Micron Technology, Inc. | Memory cell having a vertical transistor with buried source/drain and dual gates |
TW331032B (en) * | 1997-07-24 | 1998-05-01 | Vanguard Int Semiconduct Corp | The DRAM structure and its producing method |
US6528837B2 (en) * | 1997-10-06 | 2003-03-04 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
US6066869A (en) | 1997-10-06 | 2000-05-23 | Micron Technology, Inc. | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor |
US6137129A (en) | 1998-01-05 | 2000-10-24 | International Business Machines Corporation | High performance direct coupled FET memory cell |
KR100331845B1 (en) * | 1998-01-10 | 2002-05-10 | 박종섭 | Method for fabricating of thin film transistor |
US6025225A (en) * | 1998-01-22 | 2000-02-15 | Micron Technology, Inc. | Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same |
US6020239A (en) | 1998-01-28 | 2000-02-01 | International Business Machines Corporation | Pillar transistor incorporating a body contact |
US5943574A (en) * | 1998-02-23 | 1999-08-24 | Motorola, Inc. | Method of fabricating 3D multilayer semiconductor circuits |
US5963469A (en) | 1998-02-24 | 1999-10-05 | Micron Technology, Inc. | Vertical bipolar read access for low voltage memory cell |
US6246083B1 (en) * | 1998-02-24 | 2001-06-12 | Micron Technology, Inc. | Vertical gain cell and array for a dynamic random access memory |
US6304483B1 (en) * | 1998-02-24 | 2001-10-16 | Micron Technology, Inc. | Circuits and methods for a static random access memory using vertical transistors |
US6242775B1 (en) | 1998-02-24 | 2001-06-05 | Micron Technology, Inc. | Circuits and methods using vertical complementary transistors |
US6097242A (en) | 1998-02-26 | 2000-08-01 | Micron Technology, Inc. | Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits |
US6124729A (en) | 1998-02-27 | 2000-09-26 | Micron Technology, Inc. | Field programmable logic arrays with vertical transistors |
JP3788022B2 (en) * | 1998-03-30 | 2006-06-21 | セイコーエプソン株式会社 | Thin film transistor and manufacturing method thereof |
US6174767B1 (en) * | 1998-05-11 | 2001-01-16 | Vanguard International Semiconductor Corporation | Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise |
US6208164B1 (en) | 1998-08-04 | 2001-03-27 | Micron Technology, Inc. | Programmable logic array with vertical transistors |
US6563155B2 (en) * | 1998-09-08 | 2003-05-13 | Texas Instruments Incorporated | Cross point type DRAM cell composed of a pillar having an active region |
WO2000019529A1 (en) * | 1998-09-25 | 2000-04-06 | Infineon Technologies Ag | Integrated circuit comprising vertical transistors, and a method for the production thereof |
JP3955409B2 (en) * | 1999-03-17 | 2007-08-08 | 株式会社ルネサステクノロジ | Semiconductor memory device |
TW461096B (en) * | 1999-05-13 | 2001-10-21 | Hitachi Ltd | Semiconductor memory |
US6107660A (en) * | 1999-05-19 | 2000-08-22 | Worldwide Semiconductor Manufacturing Corp. | Vertical thin film transistor |
DE60041863D1 (en) * | 1999-07-02 | 2009-05-07 | Mitsubishi Material Silicon | MANUFACTURING PROCESS OF A SOI SUBSTRATE |
JP2001044279A (en) * | 1999-07-12 | 2001-02-16 | Motorola Inc | Three-dimensional multilayer semiconductor circuit |
US6500744B2 (en) | 1999-09-02 | 2002-12-31 | Micron Technology, Inc. | Methods of forming DRAM assemblies, transistor devices, and openings in substrates |
US6603168B1 (en) * | 2000-04-20 | 2003-08-05 | Agere Systems Inc. | Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method |
JP4021602B2 (en) * | 2000-06-16 | 2007-12-12 | 株式会社東芝 | Semiconductor memory device |
FR2810792B1 (en) * | 2000-06-22 | 2003-07-04 | Commissariat Energie Atomique | MIG VERTICAL BURST TRANSISTOR AND METHOD OF MANUFACTURING THE SAME |
US6506638B1 (en) * | 2000-10-12 | 2003-01-14 | Advanced Micro Devices, Inc. | Vertical double gate transistor structure |
JP2002198499A (en) * | 2000-12-26 | 2002-07-12 | Toshiba Corp | Semiconductor memory |
US6531727B2 (en) * | 2001-02-09 | 2003-03-11 | Micron Technology, Inc. | Open bit line DRAM with ultra thin body transistors |
US6559491B2 (en) * | 2001-02-09 | 2003-05-06 | Micron Technology, Inc. | Folded bit line DRAM with ultra thin body transistors |
KR100399436B1 (en) * | 2001-03-28 | 2003-09-29 | 주식회사 하이닉스반도체 | A Magnetic random access memory and a method for manufacturing the same |
JP3566944B2 (en) * | 2001-06-23 | 2004-09-15 | 富士雄 舛岡 | Semiconductor storage device and method of manufacturing the same |
DE10130766B4 (en) * | 2001-06-26 | 2005-08-11 | Infineon Technologies Ag | Vertical transistor, memory arrangement and method for producing a vertical transistor |
US6864529B2 (en) | 2001-08-23 | 2005-03-08 | Hewlett-Packard Development Company, L.P. | Thin film transistor memory device |
JP2003068883A (en) * | 2001-08-24 | 2003-03-07 | Hitachi Ltd | Semiconductor storage device |
JP2003086804A (en) * | 2001-09-07 | 2003-03-20 | Seiko Epson Corp | Organic semiconductor device |
US20030052365A1 (en) * | 2001-09-18 | 2003-03-20 | Samir Chaudhry | Structure and fabrication method for capacitors integratible with vertical replacement gate transistors |
JP2003133437A (en) * | 2001-10-24 | 2003-05-09 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
JP2003258204A (en) * | 2002-03-01 | 2003-09-12 | Seiko Epson Corp | Semiconductor storage device |
JP4290921B2 (en) * | 2002-04-08 | 2009-07-08 | エルピーダメモリ株式会社 | Semiconductor integrated circuit device |
US6894336B2 (en) * | 2002-06-12 | 2005-05-17 | Infineon Technologies Ag | Vertical access transistor with curved channel |
DE10227605A1 (en) * | 2002-06-20 | 2004-01-15 | Infineon Technologies Ag | Layer system and production process especially for drams uses a substrate with two opposite processed surfaces and attaches a second substrate to one of these |
US7163851B2 (en) * | 2002-08-26 | 2007-01-16 | International Business Machines Corporation | Concurrent Fin-FET and thick-body device fabrication |
US6583014B1 (en) * | 2002-09-18 | 2003-06-24 | Taiwan Semiconductor Manufacturing Company | Horizontal surrounding gate MOSFETS |
US6632712B1 (en) * | 2002-10-03 | 2003-10-14 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating variable length vertical transistors |
JP2004152958A (en) * | 2002-10-30 | 2004-05-27 | Pioneer Electronic Corp | Organic semiconductor device |
JP3988189B2 (en) * | 2002-11-20 | 2007-10-10 | ソニー株式会社 | Solid-state imaging device |
JP2004221242A (en) * | 2003-01-14 | 2004-08-05 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
JP2004253730A (en) * | 2003-02-21 | 2004-09-09 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
JP4410499B2 (en) * | 2003-06-26 | 2010-02-03 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
DE10350751B4 (en) * | 2003-10-30 | 2008-04-24 | Infineon Technologies Ag | Method for producing a vertical field effect transistor and field effect memory transistor, in particular FLASH memory transistor |
US7372091B2 (en) * | 2004-01-27 | 2008-05-13 | Micron Technology, Inc. | Selective epitaxy vertical integrated circuit components |
US7829883B2 (en) * | 2004-02-12 | 2010-11-09 | International Business Machines Corporation | Vertical carbon nanotube field effect transistors and arrays |
US7098105B2 (en) * | 2004-05-26 | 2006-08-29 | Micron Technology, Inc. | Methods for forming semiconductor structures |
US7098507B2 (en) * | 2004-06-30 | 2006-08-29 | Intel Corporation | Floating-body dynamic random access memory and method of fabrication in tri-gate technology |
KR100541515B1 (en) * | 2004-07-22 | 2006-01-11 | 삼성전자주식회사 | Semiconductor device having a vertical channel pattern and method of manufacturing the same |
US7598134B2 (en) * | 2004-07-28 | 2009-10-06 | Micron Technology, Inc. | Memory device forming methods |
US7242057B2 (en) * | 2004-08-26 | 2007-07-10 | Micron Technology, Inc. | Vertical transistor structures having vertical-surrounding-gates with self-aligned features |
US7442976B2 (en) * | 2004-09-01 | 2008-10-28 | Micron Technology, Inc. | DRAM cells with vertical transistors |
JP2006261421A (en) * | 2005-03-17 | 2006-09-28 | Toshiba Corp | Semiconductor device |
US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
US7504685B2 (en) * | 2005-06-28 | 2009-03-17 | Micron Technology, Inc. | Oxide epitaxial isolation |
US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
US7768051B2 (en) * | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
TWI293207B (en) * | 2006-01-11 | 2008-02-01 | Promos Technologies Inc | Dynamic random access memory structure and method for preparing the smae |
KR100784930B1 (en) * | 2006-09-25 | 2007-12-11 | 재단법인서울대학교산학협력재단 | Memory cell device having vertical channel and double gate structures |
JP2008172164A (en) * | 2007-01-15 | 2008-07-24 | Toshiba Corp | Semiconductor device |
US8058683B2 (en) * | 2007-01-18 | 2011-11-15 | Samsung Electronics Co., Ltd. | Access device having vertical channel and related semiconductor device and a method of fabricating the access device |
TWI323946B (en) * | 2007-05-10 | 2010-04-21 | Au Optronics Corp | Thin film transistor, pixel structure and fabricating method thereof |
US7842999B2 (en) | 2007-05-17 | 2010-11-30 | Elpida Memory, Inc. | Semiconductor memory device and method of manufacturing the same |
JP2008294310A (en) | 2007-05-25 | 2008-12-04 | Elpida Memory Inc | Semiconductor memory |
US7910986B2 (en) | 2007-05-31 | 2011-03-22 | Elpida Memory, Inc. | Semiconductor memory device and data processing system |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
JP2009016444A (en) * | 2007-07-02 | 2009-01-22 | Toshiba Corp | Semiconductor memory |
US8183628B2 (en) | 2007-10-29 | 2012-05-22 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor structure and method of fabricating the semiconductor structure |
JP5237974B2 (en) * | 2008-01-29 | 2013-07-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor memory device, memory-embedded semiconductor device, and manufacturing method thereof |
US8598650B2 (en) | 2008-01-29 | 2013-12-03 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor device and production method therefor |
WO2009095997A1 (en) * | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | Semiconductor device and its manufacturing method |
US8212298B2 (en) | 2008-01-29 | 2012-07-03 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor storage device and methods of producing it |
JP5317343B2 (en) | 2009-04-28 | 2013-10-16 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
JP5623005B2 (en) * | 2008-02-01 | 2014-11-12 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Semiconductor device and manufacturing method thereof |
JP5356260B2 (en) * | 2008-02-15 | 2013-12-04 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
JP5340180B2 (en) * | 2008-02-15 | 2013-11-13 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
JP5356258B2 (en) * | 2008-02-15 | 2013-12-04 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Manufacturing method of semiconductor device |
WO2009110050A1 (en) * | 2008-02-15 | 2009-09-11 | 日本ユニサンティスエレクトロニクス株式会社 | Method for manufacturing semiconductor device |
JP5779702B2 (en) * | 2008-02-15 | 2015-09-16 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device and manufacturing method thereof |
KR100956601B1 (en) * | 2008-03-25 | 2010-05-11 | 주식회사 하이닉스반도체 | Vertical channel transister in semiconductor device and method for forming the same |
KR100946084B1 (en) * | 2008-03-27 | 2010-03-10 | 주식회사 하이닉스반도체 | Vertical transistor for semiconductor device and manufacturing method of the same |
KR100956602B1 (en) * | 2008-04-01 | 2010-05-11 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
KR100958810B1 (en) * | 2008-04-04 | 2010-05-24 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
KR100971420B1 (en) * | 2008-04-04 | 2010-07-21 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
TW201007930A (en) * | 2008-08-07 | 2010-02-16 | Nanya Technology Corp | Dynamic random access memory structure, array thereof, and method of making the same |
US8101497B2 (en) | 2008-09-11 | 2012-01-24 | Micron Technology, Inc. | Self-aligned trench formation |
KR101033982B1 (en) * | 2008-11-14 | 2011-05-11 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming the same |
JP4757317B2 (en) * | 2009-01-26 | 2011-08-24 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor integrated circuit device |
JP2010219139A (en) * | 2009-03-13 | 2010-09-30 | Elpida Memory Inc | Semiconductor device, and method for manufacturing the same |
JP4487221B1 (en) * | 2009-04-17 | 2010-06-23 | 日本ユニサンティスエレクトロニクス株式会社 | Semiconductor device |
JP2011035228A (en) * | 2009-08-04 | 2011-02-17 | Toshiba Corp | Nonvolatile semiconductor storage device and method for manufacturing the same |
JP5356970B2 (en) | 2009-10-01 | 2013-12-04 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device |
WO2011111662A1 (en) | 2010-03-08 | 2011-09-15 | 日本ユニサンティスエレクトロニクス株式会社 | Solid-state image pickup device |
KR20110101876A (en) * | 2010-03-10 | 2011-09-16 | 삼성전자주식회사 | Semiconductor device with a buried bit line and method of manufacturing the semiconductor device |
US8487357B2 (en) | 2010-03-12 | 2013-07-16 | Unisantis Electronics Singapore Pte Ltd. | Solid state imaging device having high sensitivity and high pixel density |
JP5066590B2 (en) | 2010-06-09 | 2012-11-07 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
JP5087655B2 (en) | 2010-06-15 | 2012-12-05 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device and manufacturing method thereof |
US8361856B2 (en) | 2010-11-01 | 2013-01-29 | Micron Technology, Inc. | Memory cells, arrays of memory cells, and methods of forming memory cells |
US8329567B2 (en) | 2010-11-03 | 2012-12-11 | Micron Technology, Inc. | Methods of forming doped regions in semiconductor substrates |
KR101827549B1 (en) * | 2011-01-03 | 2018-03-23 | 에스케이하이닉스 주식회사 | Semiconductor device and method for forming the same |
US8492769B2 (en) * | 2011-01-07 | 2013-07-23 | Eastman Kodak Company | Transistor including multi-layer reentrant profile |
US8450175B2 (en) | 2011-02-22 | 2013-05-28 | Micron Technology, Inc. | Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith |
WO2012121265A1 (en) | 2011-03-10 | 2012-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and method for manufacturing the same |
US8686486B2 (en) * | 2011-03-31 | 2014-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Memory device |
US8569831B2 (en) | 2011-05-27 | 2013-10-29 | Micron Technology, Inc. | Integrated circuit arrays and semiconductor constructions |
CN102760735B (en) * | 2011-06-21 | 2015-06-17 | 钰创科技股份有限公司 | Dynamic memory structure |
US8564034B2 (en) | 2011-09-08 | 2013-10-22 | Unisantis Electronics Singapore Pte. Ltd. | Solid-state imaging device |
US8669601B2 (en) | 2011-09-15 | 2014-03-11 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing semiconductor device and semiconductor device having pillar-shaped semiconductor |
US8866214B2 (en) * | 2011-10-12 | 2014-10-21 | International Business Machines Corporation | Vertical transistor having an asymmetric gate |
KR20130047409A (en) * | 2011-10-31 | 2013-05-08 | 에스케이하이닉스 주식회사 | Semiconductor device and method for fabricating the same |
US8772175B2 (en) | 2011-12-19 | 2014-07-08 | Unisantis Electronics Singapore Pte. Ltd. | Method for manufacturing semiconductor device and semiconductor device |
US8916478B2 (en) | 2011-12-19 | 2014-12-23 | Unisantis Electronics Singapore Pte. Ltd. | Method for manufacturing semiconductor device and semiconductor device |
US8748938B2 (en) | 2012-02-20 | 2014-06-10 | Unisantis Electronics Singapore Pte. Ltd. | Solid-state imaging device |
US9312257B2 (en) * | 2012-02-29 | 2016-04-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP6100559B2 (en) | 2012-03-05 | 2017-03-22 | 株式会社半導体エネルギー研究所 | Semiconductor memory device |
US9036391B2 (en) | 2012-03-06 | 2015-05-19 | Micron Technology, Inc. | Arrays of vertically-oriented transistors, memory arrays including vertically-oriented transistors, and memory cells |
KR20130103942A (en) * | 2012-03-12 | 2013-09-25 | 에스케이하이닉스 주식회사 | Semiconductor device having junctionless vertical gate transistor and method for manufacturing the same |
JP5905752B2 (en) * | 2012-03-16 | 2016-04-20 | 猛英 白土 | Semiconductor device and manufacturing method thereof |
US8975705B2 (en) * | 2012-05-21 | 2015-03-10 | Unisantis Electronics Singapore Pte. Ltd. | Semiconductor device |
US9129896B2 (en) | 2012-08-21 | 2015-09-08 | Micron Technology, Inc. | Arrays comprising vertically-oriented transistors, integrated circuitry comprising a conductive line buried in silicon-comprising semiconductor material, methods of forming a plurality of conductive lines buried in silicon-comprising semiconductor material, and methods of forming an array comprising vertically-oriented transistors |
US9006060B2 (en) | 2012-08-21 | 2015-04-14 | Micron Technology, Inc. | N-type field effect transistors, arrays comprising N-type vertically-oriented transistors, methods of forming an N-type field effect transistor, and methods of forming an array comprising vertically-oriented N-type transistors |
US9478550B2 (en) | 2012-08-27 | 2016-10-25 | Micron Technology, Inc. | Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors |
KR101986145B1 (en) * | 2012-08-28 | 2019-06-05 | 에스케이하이닉스 주식회사 | Semiconductor device with buried bitline and method for manufacturing the same |
US8759875B1 (en) * | 2012-12-07 | 2014-06-24 | Globalfoundries Singapore Pte. Ltd. | Vertical nanowire based hetero-structure split gate memory |
US9111853B2 (en) | 2013-03-15 | 2015-08-18 | Micron Technology, Inc. | Methods of forming doped elements of semiconductor device structures |
JP5688190B1 (en) * | 2013-09-03 | 2015-03-25 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device |
JP6271982B2 (en) * | 2013-12-09 | 2018-01-31 | 猛英 白土 | Semiconductor device and manufacturing method thereof |
JP5779739B1 (en) * | 2014-02-18 | 2015-09-16 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device manufacturing method and semiconductor device |
WO2015199644A1 (en) | 2014-06-23 | 2015-12-30 | Intel Corporation | Techniques for forming vertical transistor architectures |
US9847233B2 (en) | 2014-07-29 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and formation thereof |
US9705004B2 (en) * | 2014-08-01 | 2017-07-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP6065190B2 (en) * | 2014-09-05 | 2017-01-25 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device |
US10032906B2 (en) * | 2016-04-29 | 2018-07-24 | Samsung Electronics Co., Ltd. | Vertical field effect transistor and method of fabricating the same |
US9935101B2 (en) | 2016-07-27 | 2018-04-03 | International Business Machines Corporation | Vertical field effect transistor with uniform gate length |
JP6737953B2 (en) | 2016-08-31 | 2020-08-12 | マイクロン テクノロジー,インク. | Device including ferroelectric memory and method for accessing ferroelectric memory |
WO2018044510A1 (en) | 2016-08-31 | 2018-03-08 | Micron Technology, Inc. | Apparatuses and methods including two transistor-one capacitor memory and for accessing same |
US11088033B2 (en) * | 2016-09-08 | 2021-08-10 | International Business Machines Corporation | Low resistance source-drain contacts using high temperature silicides |
US9859421B1 (en) * | 2016-09-21 | 2018-01-02 | International Business Machines Corporation | Vertical field effect transistor with subway etch replacement metal gate |
US11843054B2 (en) * | 2018-06-22 | 2023-12-12 | Intel Corporation | Vertical architecture of thin film transistors |
CN109285836B (en) * | 2018-08-28 | 2023-10-10 | 中国科学院微电子研究所 | Semiconductor memory device, method of manufacturing the same, and electronic apparatus including the same |
JP7210344B2 (en) * | 2019-03-18 | 2023-01-23 | キオクシア株式会社 | Semiconductor device and its manufacturing method |
JP6961639B2 (en) * | 2019-03-19 | 2021-11-05 | 株式会社東芝 | Pressure sensor |
US10916548B1 (en) * | 2019-07-25 | 2021-02-09 | Micron Technology, Inc. | Memory arrays with vertical access transistors |
CN111326509B (en) * | 2020-03-03 | 2023-06-30 | 中国科学院微电子研究所 | Semiconductor device including capacitor, method of manufacturing the same, and electronic apparatus |
JP2022143580A (en) * | 2021-03-17 | 2022-10-03 | キオクシア株式会社 | Semiconductor device and semiconductor storage device |
CN115568203A (en) * | 2021-07-01 | 2023-01-03 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
JP7457140B2 (en) * | 2021-07-16 | 2024-03-27 | チャンシン メモリー テクノロジーズ インコーポレイテッド | Semiconductor structure and its manufacturing method |
TWI790008B (en) * | 2021-11-25 | 2023-01-11 | 力晶積成電子製造股份有限公司 | Dynamic random access memory structure |
CN116207131A (en) * | 2021-12-15 | 2023-06-02 | 北京超弦存储器研究院 | Thin film transistor and preparation method thereof |
CN116207133B (en) * | 2022-01-21 | 2024-03-15 | 北京超弦存储器研究院 | Thin film transistor and preparation method thereof |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0793365B2 (en) * | 1984-09-11 | 1995-10-09 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
JPS63211750A (en) * | 1987-02-27 | 1988-09-02 | Mitsubishi Electric Corp | Semiconductor memory device |
JPH01125858A (en) * | 1987-11-10 | 1989-05-18 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JP2655859B2 (en) * | 1988-02-03 | 1997-09-24 | 株式会社日立製作所 | Semiconductor storage device |
JP2629818B2 (en) * | 1988-05-09 | 1997-07-16 | 三菱電機株式会社 | MOS dynamic RAM and method of manufacturing the same |
JPH02159058A (en) * | 1988-12-13 | 1990-06-19 | Fujitsu Ltd | Semiconductor memory cell |
JPH02198170A (en) * | 1989-01-27 | 1990-08-06 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JP2804539B2 (en) * | 1989-09-28 | 1998-09-30 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
JPH03225873A (en) * | 1990-01-30 | 1991-10-04 | Mitsubishi Electric Corp | Semiconductor device |
US5001296A (en) * | 1990-03-07 | 1991-03-19 | Mobil Oil Corp. | Catalytic hydrodealkylation of aromatics |
JPH0775247B2 (en) * | 1990-05-28 | 1995-08-09 | 株式会社東芝 | Semiconductor memory device |
JP2941039B2 (en) * | 1990-11-08 | 1999-08-25 | 沖電気工業株式会社 | Method for manufacturing semiconductor memory device |
JPH04188869A (en) * | 1990-11-22 | 1992-07-07 | Mitsubishi Electric Corp | Semiconductor memory device comprising junction type fet and capacitor and manufacture thereof |
JP3158462B2 (en) * | 1991-03-11 | 2001-04-23 | 松下電器産業株式会社 | Semiconductor memory device and method of manufacturing the same |
JP3114233B2 (en) | 1991-05-23 | 2000-12-04 | 株式会社ニコン | Multi flash control device |
JPH0529573A (en) * | 1991-07-24 | 1993-02-05 | Mitsubishi Electric Corp | Semiconductor storage device and manufacture thereof |
KR970001894B1 (en) * | 1991-09-13 | 1997-02-18 | Nippon Electric Kk | Semiconductor memory device |
JPH05160408A (en) * | 1991-12-04 | 1993-06-25 | Toshiba Corp | Field effect transistor and dynamic semiconductor storage device using same |
JP2905642B2 (en) * | 1992-01-18 | 1999-06-14 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
US5208172A (en) * | 1992-03-02 | 1993-05-04 | Motorola, Inc. | Method for forming a raised vertical transistor |
US5308782A (en) * | 1992-03-02 | 1994-05-03 | Motorola | Semiconductor memory device and method of formation |
JP2681729B2 (en) * | 1992-06-11 | 1997-11-26 | シーケーディ株式会社 | Chemical supply device |
KR960016773B1 (en) * | 1994-03-28 | 1996-12-20 | Samsung Electronics Co Ltd | Buried bit line and cylindrical gate cell and forming method thereof |
JP3745392B2 (en) * | 1994-05-26 | 2006-02-15 | 株式会社ルネサステクノロジ | Semiconductor device |
JP3225873B2 (en) | 1997-01-08 | 2001-11-05 | 三菱マテリアル株式会社 | MgO composite ceramics and method for producing the same |
-
1994
- 1994-05-26 JP JP11299794A patent/JP3745392B2/en not_active Expired - Fee Related
- 1994-12-09 DE DE4443968A patent/DE4443968B4/en not_active Expired - Fee Related
-
1995
- 1995-04-14 KR KR1019950008820A patent/KR100200222B1/en not_active IP Right Cessation
-
1996
- 1996-05-16 US US08/648,828 patent/US5627390A/en not_active Expired - Lifetime
- 1996-12-02 US US08/758,841 patent/US5780888A/en not_active Expired - Lifetime
-
1998
- 1998-03-12 US US09/038,981 patent/US6150688A/en not_active Expired - Lifetime
-
2000
- 2000-09-12 US US09/660,448 patent/US6303425B1/en not_active Expired - Lifetime
-
2001
- 2001-07-20 US US09/908,607 patent/US6383860B2/en not_active Expired - Fee Related
Cited By (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7531395B2 (en) | 2004-09-01 | 2009-05-12 | Micron Technology, Inc. | Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors |
US20060051941A1 (en) * | 2004-09-01 | 2006-03-09 | Micron Technology, Inc. | Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors |
US20090179231A1 (en) * | 2004-09-01 | 2009-07-16 | Nirmal Ramaswamy | Integrated Circuitry |
US20060264010A1 (en) * | 2004-09-01 | 2006-11-23 | Nirmal Ramaswamy | Methods of forming layers comprising epitaxial silicon |
US8035129B2 (en) | 2004-09-01 | 2011-10-11 | Micron Technology, Inc. | Integrated circuitry |
US20070166962A1 (en) * | 2004-09-01 | 2007-07-19 | Nirmal Ramaswamy | Methods of forming layers comprising epitaxial silicon |
US20070178646A1 (en) * | 2004-09-01 | 2007-08-02 | Nirmal Ramaswamy | Method of forming a layer comprising epitaxial silicon |
US7439136B2 (en) * | 2004-09-01 | 2008-10-21 | Micron Technology, Inc. | Method of forming a layer comprising epitaxial silicon |
US20060046440A1 (en) * | 2004-09-01 | 2006-03-02 | Nirmal Ramaswamy | Methods of forming layers comprising epitaxial silicon |
US7528424B2 (en) | 2004-09-01 | 2009-05-05 | Micron Technology, Inc. | Integrated circuitry |
US8673706B2 (en) | 2004-09-01 | 2014-03-18 | Micron Technology, Inc. | Methods of forming layers comprising epitaxial silicon |
US20060046394A1 (en) * | 2004-09-01 | 2006-03-02 | Nirmal Ramaswamy | Forming a vertical transistor |
US7517758B2 (en) | 2004-09-01 | 2009-04-14 | Micron Technology, Inc. | Method of forming a vertical transistor |
US7709326B2 (en) | 2004-09-01 | 2010-05-04 | Micron Technology, Inc. | Methods of forming layers comprising epitaxial silicon |
US20100258857A1 (en) * | 2004-09-01 | 2010-10-14 | Nirmal Ramaswamy | Method of Forming a Layer Comprising Epitaxial Silicon, and a Field Effect Transistor |
US7768036B2 (en) | 2004-09-01 | 2010-08-03 | Micron Technology, Inc. | Integrated circuitry |
US7807535B2 (en) | 2004-09-01 | 2010-10-05 | Micron Technology, Inc. | Methods of forming layers comprising epitaxial silicon |
US20100173460A1 (en) * | 2005-06-13 | 2010-07-08 | Micron Technology, Inc. | Vertical transistor, memory cell, device, system and method of forming same |
US7679118B2 (en) * | 2005-06-13 | 2010-03-16 | Micron Technology, Inc. | Vertical transistor, memory cell, device, system and method of forming same |
US20060278910A1 (en) * | 2005-06-13 | 2006-12-14 | Leonard Forbes | Vertical transistor, memory cell, device, system and method of forming same |
US9048337B2 (en) | 2005-06-13 | 2015-06-02 | Micron Technology, Inc. | Vertical transistor, memory cell, device, system and method of forming same |
US8461002B2 (en) | 2005-06-13 | 2013-06-11 | Micron Technology, Inc. | Vertical transistor, memory cell, device, system and method of forming same |
CN101933135A (en) * | 2008-01-29 | 2010-12-29 | 日本优尼山帝斯电子株式会社 | Semiconductor storage device and memory embedded semiconductor device, and manufacturing method thereof |
TWI423427B (en) * | 2008-01-29 | 2014-01-11 | Unisantis Elect Singapore Pte | Semiconductor storage device and embedded memory semiconductor device, and method of producing the same |
KR101889285B1 (en) | 2010-02-19 | 2018-08-20 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor memory device, driving method thereof, and method for manufacturing semiconductor device |
KR20120135412A (en) * | 2010-02-19 | 2012-12-13 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor memory device, driving method thereof, and method for manufacturing semiconductor device |
US10170633B2 (en) | 2011-01-12 | 2019-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US9673336B2 (en) * | 2011-01-12 | 2017-06-06 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20120175625A1 (en) * | 2011-01-12 | 2012-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US9685526B2 (en) | 2014-02-12 | 2017-06-20 | International Business Machines Corporation | Side gate assist in metal gate first process |
KR20210030997A (en) * | 2016-08-31 | 2021-03-18 | 마이크론 테크놀로지, 인크. | Ferroelectric memory cells |
US11107515B2 (en) | 2016-08-31 | 2021-08-31 | Micron Technology, Inc. | Ferroelectric memory cells |
US11205468B2 (en) | 2016-08-31 | 2021-12-21 | Micron Technology, Inc. | Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory |
KR102369776B1 (en) * | 2016-08-31 | 2022-03-03 | 마이크론 테크놀로지, 인크. | Ferroelectric memory cells |
US11574668B2 (en) | 2016-08-31 | 2023-02-07 | Micron Technology, Inc. | Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory |
US11901005B2 (en) | 2017-07-13 | 2024-02-13 | Micron Technology, Inc. | Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells |
CN110828497A (en) * | 2019-11-19 | 2020-02-21 | 上海华力微电子有限公司 | Vertical gate CMOS image sensor and manufacturing method |
WO2023284123A1 (en) * | 2021-07-16 | 2023-01-19 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing same |
Also Published As
Publication number | Publication date |
---|---|
JP3745392B2 (en) | 2006-02-15 |
DE4443968B4 (en) | 2004-07-15 |
DE4443968A1 (en) | 1995-11-30 |
US6383860B2 (en) | 2002-05-07 |
KR100200222B1 (en) | 1999-06-15 |
JPH07321228A (en) | 1995-12-08 |
US5627390A (en) | 1997-05-06 |
KR950034790A (en) | 1995-12-28 |
US5780888A (en) | 1998-07-14 |
US6303425B1 (en) | 2001-10-16 |
US6150688A (en) | 2000-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6303425B1 (en) | Semiconductor device and method of manufacturing the same | |
US6977404B2 (en) | Trench DRAM with double-gated transistor and method of manufacturing the same | |
US5498564A (en) | Structure and method for reducing parasitic leakage in a memory array with merged isolation and node trench construction | |
US6770535B2 (en) | Semiconductor integrated circuit device and process for manufacturing the same | |
US6420751B1 (en) | Semiconductor device and method of manufacturing the same | |
JP4570811B2 (en) | Semiconductor device | |
KR100306931B1 (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
US6605838B1 (en) | Process flow for thick isolation collar with reduced length | |
US5777920A (en) | Semiconductor memory device and method of manufacturing the same | |
JP2851968B2 (en) | Semiconductor device having improved insulated gate transistor and method of manufacturing the same | |
JP2009246383A (en) | Semiconductor device | |
US6150700A (en) | Advanced nor-type mask ROM | |
JP4084041B2 (en) | Semiconductor memory device and manufacturing method thereof | |
US5917247A (en) | Static type memory cell structure with parasitic capacitor | |
JP4369405B2 (en) | Semiconductor device | |
JP4315943B2 (en) | Manufacturing method of semiconductor device | |
US6798014B2 (en) | Semiconductor memory cell and semiconductor component as well as manufacturing methods therefore | |
US20020109194A1 (en) | Semiconductor device | |
JPH1084047A (en) | Semiconductor device and its manufacturing method | |
JP2877069B2 (en) | Static semiconductor memory device | |
JP2621824B2 (en) | Method for manufacturing semiconductor device | |
JPH0770622B2 (en) | MIST dynamic random access memory cell and manufacturing method thereof | |
JP2655048B2 (en) | DRAM cell transistor and method of manufacturing the same | |
JP2980086B2 (en) | Semiconductor device and manufacturing method thereof | |
JPH04302470A (en) | Dynamic semiconductor memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: RENESAS TECHNOLOGY CORP., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MITSUBISHI DENKI KABUSHIKI KAISHA;REEL/FRAME:023594/0048 Effective date: 20091127 |
|
AS | Assignment |
Owner name: VACHELLIA, LLC,CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RENESAS TECHNOLOGY CORPORATION;REEL/FRAME:023882/0159 Effective date: 20091217 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140507 |