US20010044220A1 - Method Of Forming Silicon Oxynitride Films - Google Patents
Method Of Forming Silicon Oxynitride Films Download PDFInfo
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- US20010044220A1 US20010044220A1 US09/484,603 US48460300A US2001044220A1 US 20010044220 A1 US20010044220 A1 US 20010044220A1 US 48460300 A US48460300 A US 48460300A US 2001044220 A1 US2001044220 A1 US 2001044220A1
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- 238000000034 method Methods 0.000 title claims abstract description 66
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 38
- 239000010703 silicon Substances 0.000 title claims abstract description 38
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000001272 nitrous oxide Substances 0.000 claims abstract description 21
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910000077 silane Inorganic materials 0.000 claims abstract description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 15
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 238000002791 soaking Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000012545 processing Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910020286 SiOxNy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/308—Oxynitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
Definitions
- the present invention is generally directed to the field of semiconductor processing, and, more particularly, to an improved method for making process films comprised of silicon oxynitride.
- silicon oxynitride films comprised of silicon oxynitride (SiO x N y ) are formed at various points during the manufacturing process.
- silicon oxynitride films may be used as an etch stop layer in the formation of conductive interconnections in a semiconductor device.
- Such layers may also be used to form sidewall spacers adjacent a gate electrode of a semiconductor device and as a metal hard mask layer in ultraviolet photoresist patterning.
- Such layers are also used for other purposes not enumerated here.
- FIGS. 1 and 2 of the attached drawings One such illustrative situation in which a layer of silicon oxynitride is used as an etch stop layer is depicted in FIGS. 1 and 2 of the attached drawings.
- a gate stack 12 comprised of a gate conductor 16 and a gate dielectric 14 are formed above a surface 11 of a semiconducting substrate 10 .
- the gate dielectric 14 and the gate conductor 16 are typically made by forming process layers comprised of the appropriate materials above the surface 11 of the substrate 10 , and patterning those layers by performing one or more etching processes to define the gate stack 12 . Thereafter, the substrate 10 is subjected to a low energy ion implantation process to form lightly doped source/drain extension regions 19 in the substrate 10 .
- a plurality of side-wall spacers 22 are formed adjacent the gate stack 12 by depositing a layer of spacer material and performing one or more anisotropic etching processes to define the sidewall spacers 22 . Thereafter, an additional ion implantation process is then performed to complete the formation of the source/drain regions 24 having the familiar lightly doped drain (“LDD”) structure.
- LDD lightly doped drain
- the fabrication of the transistor is completed by forming appropriate metal contacts through various openings in the layers of dielectric material positioned above the device.
- a layer of silicon oxynitride 18 may be formed above the structure depicted in FIG. 1, and a dielectric layer 21 may be formed above the layer of silicon oxynitride 18 .
- a plurality of openings 23 are formed in the dielectric layer 21 and the layer of silicon oxynitride 18 , and conductive interconnections 25 , e.g., conductive plugs, are formed therein.
- the layer of silicon oxynitride 18 serves as an etch stop layer during the formation of the openings 23 in the dielectric layer 21 .
- the material used for the dielectric layer 21 is selectively etchable with respect to the layer of silicon oxynitride 18 .
- the underlying source/drain regions 24 may be damaged during the course of forming the openings 23 in the dielectric layer 21 .
- another etching process is performed to remove the layer of silicon oxynitride lying underneath the openings defined in the dielectric layer 21 .
- the etching process used to remove portions of the layer of silicon oxynitride 18 has a high degree of selectivity with respect to the material comprising the dielectric layer 21 and the source/drain regions 24 .
- Such surface non-uniformity may adversely impact the ability to precisely define very small feature sizes in the dielectric layer 21 using photolithographic techniques.
- Another problem associated with the formation of such silicon oxynitride layers is that, in the process of forming such layers, the integrity of the gate dielectric, e.g., gate dielectric 14 in FIG. 1, may be compromised. That is, the breakdown voltage of the gate dielectric, e.g., silicon dioxide, may be reduced below acceptable limits. This in turn may lead to increases in device failure. The damage caused to such gate dielectric may be due, in part, to relatively high power densities used in plasma enhanced chemical vapor deposition processes used to form such layers.
- the present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.
- the present invention is directed to a method of forming process layers comprised of silicon oxynitride.
- the method comprises positioning a wafer in a process chamber, introducing silane and nitrous oxide into the chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, and generating a plasma in the chamber using a high frequency to low frequency power setting ratio ranging from approximately 1.2-1.8.
- FIG. 1 is an illustrative embodiment of a partially formed prior art semiconductor device
- FIG. 2 is the device of FIG. 1 after a layer of silicon oxynitride and a dielectric layer have been formed above the device depicted in FIG. 1;
- FIG. 3 is a flowchart depicting one illustrative embodiment of the present invention.
- the present invention is directed to a method of forming process layers comprised of silicon oxynitride.
- the present invention should not be considered to be limited to any particular type of semiconductor device.
- the various regions and structures are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, those regions and structures are not as precise as indicated in the drawings.
- the relative sizes of the various features depicted in the drawings may be exaggerated or reduced as compared to the size of those feature sizes on fabricated devices. Nevertheless, the attached drawings are included to aid in obtaining an understanding of the present invention.
- the present invention is not limited to any particular production tool used in the course of manufacturing such oxynitride layers, and the present process may be used with either single chamber tools or multiple chamber tools.
- the present invention has been employed with a Novellus Sequel deposition tool.
- the present invention may also be used with other deposition tools, although the precise processing parameters may be varied.
- the present method is applicable to a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, flash memory, EPROMs, etc.
- the present invention is directed to a method of forming a layer of silicon oxynitride (SiO x N y ) using a plasma enhanced chemical vapor deposition (“PECVD”) process that results in improved deposition rates, better layer uniformity, and increased gate dielectric reliability. As indicated in FIG.
- PECVD plasma enhanced chemical vapor deposition
- one illustrative embodiment of the present invention comprises positioning a wafer into a process chamber, as indicated at block 30 , introducing siliane (SiH 4 ) and nitrous oxide (N 2 O) into the process chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, as indicated at block 32 , and generating a plasma in the chamber using a high frequency power setting ratio ranging from approximately 1.2-1.8, as indicated at block 34 .
- This will result in a power density ranging from approximately 0.20-0.37 watts per square centimeter of shower head in the processing chamber.
- the constituent chemicals that are used to form the layer of silicon oxynitride may be varied.
- the constituent chemicals are comprised of silane (SiH 4 ), nitrous oxide (N 2 O), and nitrogen (N 2 ).
- the flow rate of the silane ranges from approximately 435-475 (455 ⁇ 20) standard cubic centimeters per minute (sccm)
- the flow rate of the nitrous oxide (N 2 O) ranges from approximately 125-165 (145 ⁇ 20) sccm
- the flow rate of nitrogen (N 2 ) ranges from approximately 7500-8500 (8000 ⁇ 500) sccm.
- the constituent chemicals are comprised of approximately 455 sccm of silane, approximately 145 sccm of nitrous oxide, and approximately 8000 sccm of nitrogen.
- Other carrier gases such as helium (He) or argon (Ar) may be used in lieu of nitrogen in connection with the present invention.
- flow rates of these alternative gases may vary from that described above with respect to nitrogen.
- the pressure employed during the present process may range from approximately 2.7-3.3 (3 ⁇ 0.3) torr, and in one particular embodiment is approximately 3.0 torr.
- the temperature at which the process disclosed herein may be performed ranges from approximately 380-420° C. (400 ⁇ 20° C.), and in one particular embodiment is approximately 400° C.
- Application of the power used to generate the plasma may also be delayed until a certain time after the silane has been introduced into the process chamber, e.g., a 1-2 second delay.
- the wafer may be subjected to temperature soak for a duration ranging from approximately 15-45 seconds, and in one particular embodiment for a duration of approximately 30 seconds.
- the present invention is comprised of forming a silicon oxynitride layer using the following recipe: silane (SiH 4 ): 435-475-sccm; nitrogen (N 2 ): 7500-8500 sccm; nitrous oxide (N 2 O): 125-165 sccm with a high frequency RF power (HFRF) setting ranging from approximately 510-610 watts, a low frequency RF power (LFRF) setting ranging from approximately 330-430 watts at a pressure ranging from approximately 2.7-3.3 torr, and at a temperature ranging from approximately 380-420° C.
- HFRF high frequency RF power
- LFRF low frequency RF power
- a delay time for introducing the silane prior to the application of the power to form a stable plasma may also be a delay time for introducing the silane prior to the application of the power to form a stable plasma of approximately 1-2 seconds.
- a temperature soaking operation may be performed for a duration ranging from approximately 15-45 seconds to improve the uniformity of the resulting layer.
- the particular order of the introduction of the various process chemicals into the process chamber may be varied.
- the recipe disclosed herein for forming silicon oxynitride layers reduces or eliminates the damage caused to gate dielectrics using some prior art processes. This, in turn, increases the reliability of the resulting devices and increases manufacturing yields.
- the present invention may be used to produce a silicon-rich layer of silicon oxynitride having a refractive index ranging from approximately 2.19-2.49, and in one particular embodiment, a refractive index of approximately 2.34.
Abstract
Description
- 1. Field of the Invention
- The present invention is generally directed to the field of semiconductor processing, and, more particularly, to an improved method for making process films comprised of silicon oxynitride.
- 2. Description of the Related Art
- In the manufacture of semiconductor devices, process films comprised of silicon oxynitride (SiOxNy) are formed at various points during the manufacturing process. By way of example, silicon oxynitride films may be used as an etch stop layer in the formation of conductive interconnections in a semiconductor device. Such layers may also be used to form sidewall spacers adjacent a gate electrode of a semiconductor device and as a metal hard mask layer in ultraviolet photoresist patterning. Such layers are also used for other purposes not enumerated here. One such illustrative situation in which a layer of silicon oxynitride is used as an etch stop layer is depicted in FIGS. 1 and 2 of the attached drawings.
- As shown in FIG. 1, a
gate stack 12 comprised of agate conductor 16 and a gate dielectric 14 are formed above asurface 11 of asemiconducting substrate 10. The gate dielectric 14 and thegate conductor 16 are typically made by forming process layers comprised of the appropriate materials above thesurface 11 of thesubstrate 10, and patterning those layers by performing one or more etching processes to define thegate stack 12. Thereafter, thesubstrate 10 is subjected to a low energy ion implantation process to form lightly doped source/drain extension regions 19 in thesubstrate 10. Next, a plurality of side-wall spacers 22 are formed adjacent thegate stack 12 by depositing a layer of spacer material and performing one or more anisotropic etching processes to define thesidewall spacers 22. Thereafter, an additional ion implantation process is then performed to complete the formation of the source/drain regions 24 having the familiar lightly doped drain (“LDD”) structure. - The fabrication of the transistor is completed by forming appropriate metal contacts through various openings in the layers of dielectric material positioned above the device. In particular, as shown in FIG. 2, a layer of
silicon oxynitride 18 may be formed above the structure depicted in FIG. 1, and adielectric layer 21 may be formed above the layer ofsilicon oxynitride 18. Thereafter, a plurality ofopenings 23 are formed in thedielectric layer 21 and the layer ofsilicon oxynitride 18, andconductive interconnections 25, e.g., conductive plugs, are formed therein. - During this process, the layer of
silicon oxynitride 18 serves as an etch stop layer during the formation of theopenings 23 in thedielectric layer 21. The material used for thedielectric layer 21 is selectively etchable with respect to the layer ofsilicon oxynitride 18. Without the use of thesilicon oxynitride layer 18 as an etch stop, the underlying source/drain regions 24 may be damaged during the course of forming theopenings 23 in thedielectric layer 21. After theopenings 23 are formed in thedielectric layer 21, another etching process is performed to remove the layer of silicon oxynitride lying underneath the openings defined in thedielectric layer 21. The etching process used to remove portions of the layer ofsilicon oxynitride 18 has a high degree of selectivity with respect to the material comprising thedielectric layer 21 and the source/drain regions 24. - Although there are existing techniques for forming the layer of
silicon oxynitride 18, the layers resulting from such known techniques or processes exhibit many problems that are detrimental to device performance and integrity. One problem associated with using known techniques for forming silicon oxynitride layers is that such techniques produce unacceptable variations in the thickness of the deposited layer. Such variations in the thickness of the silicon oxynitride layers formed using known techniques and processes may lead to unacceptable results and may create additional problems in subsequent processing operations. For example, localized variations in the thickness of a layer of silicon oxynitride may result in corresponding unevenness in asurface 29 of thedielectric layer 21, although that situation is not depicted in FIG. 2. Such surface non-uniformity may adversely impact the ability to precisely define very small feature sizes in thedielectric layer 21 using photolithographic techniques. Thus, it is very desirable to be able to produce layers of silicon oxynitride with reduced or smaller variations in thickness across the surface of the layer so that these non-uniformities do not propagate to other process layers as they are formed above the layer of silicon oxynitride. - Additionally, in semiconductor processing operations, it is generally desirable to achieve as much throughput as possible to improve yields and reduce costs. This applies equally to the formation of layers of silicon oxynitride. Thus, it is desirable to develop a method of forming layers comprised of silicon oxynitride with an acceptable range of thickness variations while at the same time insuring that deposition rates are as fast as possible to improve production and lower costs.
- Another problem associated with the formation of such silicon oxynitride layers is that, in the process of forming such layers, the integrity of the gate dielectric, e.g., gate dielectric14 in FIG. 1, may be compromised. That is, the breakdown voltage of the gate dielectric, e.g., silicon dioxide, may be reduced below acceptable limits. This in turn may lead to increases in device failure. The damage caused to such gate dielectric may be due, in part, to relatively high power densities used in plasma enhanced chemical vapor deposition processes used to form such layers.
- The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.
- The present invention is directed to a method of forming process layers comprised of silicon oxynitride. In one embodiment, the method comprises positioning a wafer in a process chamber, introducing silane and nitrous oxide into the chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, and generating a plasma in the chamber using a high frequency to low frequency power setting ratio ranging from approximately 1.2-1.8.
- The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
- FIG. 1 is an illustrative embodiment of a partially formed prior art semiconductor device;
- FIG. 2 is the device of FIG. 1 after a layer of silicon oxynitride and a dielectric layer have been formed above the device depicted in FIG. 1; and
- FIG. 3 is a flowchart depicting one illustrative embodiment of the present invention.
- While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
- The present invention is directed to a method of forming process layers comprised of silicon oxynitride. In disclosing the present invention, reference may be made to the illustrative transistor depicted in FIGS.1-2. However, the present invention should not be considered to be limited to any particular type of semiconductor device. Moreover, although the various regions and structures are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, those regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features depicted in the drawings may be exaggerated or reduced as compared to the size of those feature sizes on fabricated devices. Nevertheless, the attached drawings are included to aid in obtaining an understanding of the present invention.
- As will also be apparent to those skilled in the art upon a complete reading of the present application, the present invention is not limited to any particular production tool used in the course of manufacturing such oxynitride layers, and the present process may be used with either single chamber tools or multiple chamber tools. For example, the present invention has been employed with a Novellus Sequel deposition tool. The present invention may also be used with other deposition tools, although the precise processing parameters may be varied. Moreover, the present method is applicable to a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, flash memory, EPROMs, etc.
- The present invention is directed to a method of forming a layer of silicon oxynitride (SiOxNy) using a plasma enhanced chemical vapor deposition (“PECVD”) process that results in improved deposition rates, better layer uniformity, and increased gate dielectric reliability. As indicated in FIG. 3, one illustrative embodiment of the present invention comprises positioning a wafer into a process chamber, as indicated at
block 30, introducing siliane (SiH4) and nitrous oxide (N2O) into the process chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, as indicated atblock 32, and generating a plasma in the chamber using a high frequency power setting ratio ranging from approximately 1.2-1.8, as indicated atblock 34. This will result in a power density ranging from approximately 0.20-0.37 watts per square centimeter of shower head in the processing chamber. - The constituent chemicals that are used to form the layer of silicon oxynitride may be varied. In one illustrative embodiment, the constituent chemicals are comprised of silane (SiH4), nitrous oxide (N2O), and nitrogen (N2). In one particularly illustrative example, the flow rate of the silane ranges from approximately 435-475 (455±20) standard cubic centimeters per minute (sccm), the flow rate of the nitrous oxide (N2O) ranges from approximately 125-165 (145±20) sccm, and the flow rate of nitrogen (N2) ranges from approximately 7500-8500 (8000±500) sccm. In another particularly illustrative embodiment, the constituent chemicals are comprised of approximately 455 sccm of silane, approximately 145 sccm of nitrous oxide, and approximately 8000 sccm of nitrogen. Other carrier gases, such as helium (He) or argon (Ar) may be used in lieu of nitrogen in connection with the present invention. However, flow rates of these alternative gases may vary from that described above with respect to nitrogen.
- Other process parameters, of course, may be considered in the formation of silicon oxynitride layers in accordance with the present invention. For example, the pressure employed during the present process may range from approximately 2.7-3.3 (3±0.3) torr, and in one particular embodiment is approximately 3.0 torr. Similarly, the temperature at which the process disclosed herein may be performed ranges from approximately 380-420° C. (400±20° C.), and in one particular embodiment is approximately 400° C. Application of the power used to generate the plasma may also be delayed until a certain time after the silane has been introduced into the process chamber, e.g., a 1-2 second delay. Moreover, the wafer may be subjected to temperature soak for a duration ranging from approximately 15-45 seconds, and in one particular embodiment for a duration of approximately 30 seconds.
- In one particular embodiment, the present invention is comprised of forming a silicon oxynitride layer using the following recipe: silane (SiH4): 435-475-sccm; nitrogen (N2): 7500-8500 sccm; nitrous oxide (N2O): 125-165 sccm with a high frequency RF power (HFRF) setting ranging from approximately 510-610 watts, a low frequency RF power (LFRF) setting ranging from approximately 330-430 watts at a pressure ranging from approximately 2.7-3.3 torr, and at a temperature ranging from approximately 380-420° C. There may also be a delay time for introducing the silane prior to the application of the power to form a stable plasma of approximately 1-2 seconds. Additionally, a temperature soaking operation may be performed for a duration ranging from approximately 15-45 seconds to improve the uniformity of the resulting layer. The particular order of the introduction of the various process chemicals into the process chamber may be varied.
- By producing silicon oxynitride layers in accordance with the present invention, better thickness control of the resulting layer may be achieved, e.g., on the order of 1% variation (1 sigma) as compared to the nominal thickness with deposition rates ranging from approximately 2350-2650 (2500±150) Å/minute. In contrast, the process described in U.S. patent application Ser. No. 08/924,130, entitled “In-situ Deposition of Stop Layer and Dielectric Layer During Formation of Local Interconnects,” for forming layers of silicon oxynitride has deposition rates on the order of approximately 1000-1200 Å/minute and a thickness control on the order of 2% variation (1 sigma). Moreover, the recipe disclosed herein for forming silicon oxynitride layers reduces or eliminates the damage caused to gate dielectrics using some prior art processes. This, in turn, increases the reliability of the resulting devices and increases manufacturing yields. The present invention may be used to produce a silicon-rich layer of silicon oxynitride having a refractive index ranging from approximately 2.19-2.49, and in one particular embodiment, a refractive index of approximately 2.34.
- The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
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