US20010051413A1 - Process for fabricating a self-aligned double-polysilicon bipolar transistor - Google Patents
Process for fabricating a self-aligned double-polysilicon bipolar transistor Download PDFInfo
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- US20010051413A1 US20010051413A1 US09/796,116 US79611601A US2001051413A1 US 20010051413 A1 US20010051413 A1 US 20010051413A1 US 79611601 A US79611601 A US 79611601A US 2001051413 A1 US2001051413 A1 US 2001051413A1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 title claims description 20
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000003989 dielectric material Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 74
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 229910045601 alloy Inorganic materials 0.000 claims description 15
- 239000000956 alloy Substances 0.000 claims description 15
- 229910052681 coesite Inorganic materials 0.000 claims description 14
- 229910052906 cristobalite Inorganic materials 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 229910052682 stishovite Inorganic materials 0.000 claims description 14
- 229910052905 tridymite Inorganic materials 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000002019 doping agent Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910006990 Si1-xGex Inorganic materials 0.000 description 1
- 229910007020 Si1−xGex Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
Definitions
- FIGS. 2 a to 2 e are schematic cross-sectional views of the main steps of a first embodiment of the process according to the invention.
Abstract
Description
- The present invention relates in general to the fabrication of double-polysilicon bipolar transistors (i.e. extrinsic base and emitter made of polycrystalline silicon (poly-Si), in contrast to the single-polysilicon bipolar transistors with only the emitter made of poly-Si). More particularly, the present invention relates to a process for fabricating a self-aligned double-polysilicon bipolar transistor having an epitaxially-grown base.
- The conventional process for fabricating a double-polysilicon bipolar transistor includes, as shown in FIG. 1a, forming, in or on a
semiconductor substrate 1 having a first conductivity type (for example a substrate made of single-crystal silicon having an n-type conductivity), aregion 2 having a second conductivity type the opposite of the first (for example a region made of silicon and/or SiGe alloy of p-type conductivity). Thus, abase region 2 of the second conductivity type (p) and a collector region underlying thebase region 2 and of the first conductivity type (n) are formed in thesubstrate 1. The next step includes forming, on thebase region 2, a firstthick layer 3 made of poly-Si of the second conductivity type (for example, a heavily-doped p+ layer), and, on this thick poly-Si layer 3, a thick layer of adielectric material 4 such as SiO2 or an SiO2/Si3N4 bilayer. - An
emitter window 5 is then formed by conventional photolithographic etching of thedielectric material layer 4 and the thick poly-Si layer 3 down to the base region 2 (FIG. 1b). As shown in FIG. 1c, after depositing apassivation layer 6 on the sidewalls of thewindow 5, thewindow 5 is filled and thedielectric material layer 4 is coated with a second poly-Si layer of the first conductivity type (for example heavily doped with n+) to form, after masking and conventional etching, anemitter region 7 made of poly-Si of desired geometry and size. The rest of the first thick p+-doped poly-Si layer forms the extrinsic base region of the transistor, whereas the remaining part of the thin silicon orSiGe alloy layer 2 located under theemitter region 7, forms the intrinsic base region of the bipolar transistor. - The doping of the various layers can be carried out conventionally, either in situ, i.e. during the formation of the layers, or after formation of the layers by ion implantation. Also in a conventional manner, it is possible for the various doped layers to undergo activation annealing of the dopants. Furthermore, the
base region 2 may be conventionally formed from a single-crystal SiGe/Si bilayer. - The etching of the
window 5 usually comprises a first conventional step of etching the layer ofdielectric material 4, for example SiO2, stopping on the first poly-Si layer 3, then a second step which is also conventional etching of the first thick poly-Si layer 3 stopping at the base region 2 (overetching). This overetching may, in practice, result in removing the active base region of the transistor, therefore leading to a defective device. - An object of the invention is to provide a process for fabricating a double-polysilicon bipolar transistor, while avoiding any risk of overetching the active base region of the transistor.
- It has been found, according to the invention, that it is possible to avoid any risk of overetching the active base region of a double-polysilicon bipolar transistor during its fabrication using a process comprising: (a) the production of a substrate comprising a collector region of a first conductivity type and a base region of a second conductivity type the opposite of the first; (b) the formation on the base region of an interlayer made of germanium and/or SiGe alloy (preferably polycrystalline) of the second conductivity type; (c) the formation over a predetermined zone of the Ge and/or SiGe alloy interlayer of an etch-stop film; (d) the formation on the interlayer and the etch-stop film of a first thick layer made of polycrystalline silicone (poly-Si) of the second conductivity type; (e) the formation on the first poly-Si layer of an outer layer of a dielectric material; (f) the etching, through an appropriate mask, of a window preform in the layer of dielectric material and the first thick polysilicon layer, stopping on the etch-stop film, then removal in the window preform of the etch-stop film; (g) the selective removal in the window preform of the Ge and/or SiGe alloy layer in order to form an emitter window having a bottom formed by an exposed zone of the base region and of the sidewalls; (h) the formation of a passivation layer on the sidewalls of the emitter window; (i) the formation of a second polysilicon layer of the first conductivity type, so as to fill the emitter window and cover the outer dielectric material layer; and (j) the etching of the second polysilicon layer of the first conductivity type in order to form an emitter region of the desired geometry and size.
- The processes of forming Ge and/or SiGe alloy layers are well known and it is possible to use, for example, conventional chemical vapor deposition (CVD) processes. Similarly, polysilicon layers may be formed by any conventional process such as CVD and plasma-enhanced chemical vapor deposition (PECVD). The formation of layers made of dielectric material, for example SiO2 or Si3N4, such as the layer of step (c) and the passivation layer of the sidewalls of the emitter window, is also conventional in bipolar transistor technology.
- The Ge and/or SiGe interlayer of step (d) has a thickness which usually varies from 2 to 125 nm and is preferably about 2 to 40 nm. The first polysilicon layer usually has a thickness of 50 to 250 nm, and preferably of 125 nm to 250 nm. The doping of these layers is carried out conventionally, either by in situ doping with a dopant of appropriate conductivity, or, after deposition of the layers, by conventional ion implantation of a dopant of appropriate conductivity. Conventionally, annealing steps may be carried out in order to activate the dopants.
- SiGe alloys are well known. Among these alloys, mention may be made of Si1-xGex where alloys 0<x<1 and Si1-x-yGexCy where alloys 0<x≦0.95 and 0<y≦0.05. Preferably, SiGe alloys with a relatively high germanium content, usually 10 to 50% at germanium, will be used, since the SiGe alloy etching selectivity with respect to silicon and to SiO2 increases with the germanium content of the alloy.
- The masking and the etching of the various layers to form the emitter window preform may be done by any process, such as a isotropic etching by dry means, for example by plasma. The selective removal of the Ge or the SiGe film may be carried out conventionally via a chemical oxidant, for example with a 40 ml 70% HNO3+20 ml H2O2+5 ml 0.5% HF solution or by isotropic plasma etching. This removal is controlled so as to take off that part of the poly-Ge or poly-SiGe layer which is located at the bottom of the emitter window preform and possibly so as to etch a small fraction of this layer under the first polysilicon layer.
- The presence of the etch-stop film, for example made of SiO2, means that the etching of the first polysilicon layer, which is usually by plasma etching, will definitely stop at the stop film. This is because the plasma etching of polysilicon is selective with respect to SiO2 and an end-of-etching detection signal can be used conventionally. So, while the first polysilicon layer is being etched, the interlayer definitely cannot be etched to such an extent that this layer is pierced, with consequent etching of or damage to the base region. The etching of the stop film and consequently of a fraction of the interlayer may then be carried out without risk of damaging the surface of the base region, by using known etching techniques which are gentler and more selective.
- The rest of the description refers to the appended figures:
- FIGS. 1a to 1 c are schematic cross-sectional views of the main steps of a process for fabricating a double-polysilicon bipolar transistor, according to the prior art; and
- FIGS. 2a to 2 e are schematic cross-sectional views of the main steps of a first embodiment of the process according to the invention.
- One embodiment of a double-polysilicon bipolar transistor with an npn structure, in accordance with the process of the invention, will now be described with reference to FIGS. 2a to 2 e. Of course, the process may also apply to a bipolar transistor with a pnp structure.
- As in the process of the prior art, the process starts by producing an n-doped
silicon substrate 1 comprising a p-dopedbase region 2. This base region may be formed by appropriate doping of the substrate region, immediately subjacent to a main surface of thesubstrate 1, that part of thesubstrate 1 which remains n-doped then forming a collector region. This base region may also be produced by forming an appropriately doped SiGe/Si bilayer or SiGe layer on a main surface of the substrate. - A
layer 3 made of Ge or p+-doped SiGe alloy is then formed over thebase region 2. Astop film 10, for example made of SiO2 or Si3N4, is formed in a manner known per se over a predetermined zone of the Ge orSiGe layer 3, followed by a thick p+-doped polycrystalline silicon layer, and finally an SiO2 layer 5. Usually, thestop film 10 has a thickness of 10 to 50 nm. After masking (not shown), the SiO2 layer 5 and the poly-Si layer 4 are etched, for example by anisotropic dry plasma etching, down to thestop film 10 in order to form an emitter window preform 6 (FIG. 2b). - During this etching of the poly-
Si layer 4, as shown in FIG. 2b, it is certain that the entire poly-Si layer 4 has been etched without any risk of the interlayer, and subsequently thebase region 2, being etched. The etching of thestop film 10 and the selective etching of the Ge orSiGe layer 3 are then carried out to expose the surface of thebase region 2 and thus complete the opening of theemitter window 6, as shown in FIG. 2c. This selective removal of the Ge orSiGe layer 3 usually leads to slight etching of thelayer 3 under theremaining parts Si layer 4 on each side on the sidewalls of theemitter window 6. - Next, the process continues conventionally with the formation on the sidewalls of the
emitter window 6 of apassivation layer 7 made of dielectric material, for example SiO2 or Si3N4, as shown in FIG. 2d. Then a second layer of n+-doped poly-Si is formed by filling in theemitter window 6 and by covering theouter layer 5 of dielectric material which, after masking, is then conventionally etched to form theemitter region 8. The bipolar transistor may then be conventionally finished by forming contacts and depositing an encapsulation layer. - Thus, by the process of the invention, a self-aligned double-polysilicon bipolar transistor is formed without any risk of overetching the
base region 2.
Claims (9)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0002855A FR2805923B1 (en) | 2000-03-06 | 2000-03-06 | PROCESS FOR MANUFACTURING A SELF-ALIGNED DOUBLE-POLYSILICON BIPOLAR TRANSISTOR |
FR0002855 | 2000-03-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010051413A1 true US20010051413A1 (en) | 2001-12-13 |
US6436782B2 US6436782B2 (en) | 2002-08-20 |
Family
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/796,116 Expired - Lifetime US6436782B2 (en) | 2000-03-06 | 2001-02-28 | Process for fabricating a self-aligned double-polysilicon bipolar transistor |
Country Status (3)
Country | Link |
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US (1) | US6436782B2 (en) |
EP (1) | EP1132955A1 (en) |
FR (1) | FR2805923B1 (en) |
Cited By (9)
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US6472287B2 (en) * | 2001-03-08 | 2002-10-29 | Nec Corporation | Manufacturing method of semiconductor with a cleansing agent |
WO2003069663A1 (en) * | 2002-02-12 | 2003-08-21 | Infineon Technologies Ag | Polysilicon bipolar transistor and method for producing the same |
US20030221703A1 (en) * | 2002-06-03 | 2003-12-04 | Nec Electronics Corporation | Method of removing germanium contamination on semiconductor substrate |
US20050205862A1 (en) * | 2004-03-17 | 2005-09-22 | Lam Research Corporation | Dual doped polysilicon and silicon germanium etch |
JP2007504647A (en) * | 2003-08-29 | 2007-03-01 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Bipolar transistor having raised extrinsic base with selectable self-alignment and method of forming the same |
JP2007535799A (en) * | 2003-06-24 | 2007-12-06 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Bipolar transistor having high fT and fmax and method of manufacturing the same |
JP2007536724A (en) * | 2004-04-14 | 2007-12-13 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Bipolar device, transistor device, and method of fabricating transistor and bipolar complementary metal oxide semiconductor (BiCMOS) device |
US20100289022A1 (en) * | 2005-11-21 | 2010-11-18 | Nxp B.V. | Method of manufacturing a semiconductor device and semiconductor device obtained with such a method |
US8992043B2 (en) | 2010-02-15 | 2015-03-31 | Abl Ip Holding Llc | Constructive occlusion lighting system and applications thereof |
Families Citing this family (4)
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US7064416B2 (en) * | 2001-11-16 | 2006-06-20 | International Business Machines Corporation | Semiconductor device and method having multiple subcollectors formed on a common wafer |
JP2005109501A (en) * | 2003-09-30 | 2005-04-21 | Agere Systems Inc | Bipolar transistor with selectively deposited emitter |
DE102004053393B4 (en) * | 2004-11-05 | 2007-01-11 | Atmel Germany Gmbh | Method for producing a vertically integrated cascode structure and vertically integrated cascode structure |
US8482101B2 (en) * | 2009-06-22 | 2013-07-09 | International Business Machines Corporation | Bipolar transistor structure and method including emitter-base interface impurity |
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US4855015A (en) * | 1988-04-29 | 1989-08-08 | Texas Instruments Incorporated | Dry etch process for selectively etching non-homogeneous material bilayers |
US5037768A (en) * | 1990-02-12 | 1991-08-06 | Motorola, Inc. | Method of fabricating a double polysilicon bipolar transistor which is compatible with a method of fabricating CMOS transistors |
DE69107779T2 (en) * | 1990-10-31 | 1995-09-21 | Ibm | Transistor with self-adjusting epitaxial base and its manufacturing process. |
JPH07187892A (en) * | 1991-06-28 | 1995-07-25 | Internatl Business Mach Corp <Ibm> | Silicon and its formation |
US5227333A (en) * | 1992-02-27 | 1993-07-13 | International Business Machines Corporation | Local interconnection having a germanium layer |
JP3022689B2 (en) * | 1992-08-31 | 2000-03-21 | 日本電気株式会社 | Manufacturing method of bipolar transistor |
US5616508A (en) * | 1995-01-09 | 1997-04-01 | Texas Instruments Incorporated | High speed bipolar transistor using a patterned etch stop and diffusion source |
US5593905A (en) * | 1995-02-23 | 1997-01-14 | Texas Instruments Incorporated | Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link |
US5592017A (en) * | 1995-03-23 | 1997-01-07 | Texas Instruments Incorporated | Self-aligned double poly BJT using sige spacers as extrinsic base contacts |
JP2914213B2 (en) * | 1995-03-28 | 1999-06-28 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US5866462A (en) * | 1995-09-29 | 1999-02-02 | Analog Devices, Incorporated | Double-spacer technique for forming a bipolar transistor with a very narrow emitter |
FR2764733B1 (en) * | 1997-06-11 | 2003-11-14 | Commissariat Energie Atomique | HYPERFREQUENCY TRANSISTOR WITH A QUASI-AUTOALIGNIZED STRUCTURE AND METHOD OF MANUFACTURING THE SAME |
JP2000068281A (en) * | 1998-08-19 | 2000-03-03 | Sony Corp | Bipolar transistor semiconductor device and manufacture thereof |
JP2000068282A (en) * | 1998-08-24 | 2000-03-03 | Sony Corp | Semiconductor device and manufacture thereof |
FR2805924A1 (en) * | 2000-03-06 | 2001-09-07 | France Telecom | Polycrystalline silicon layer etching process used in production of emitter self-aligned with extrinsic base of bipolar transistor involves stopping plasma-etching on or in germanium or silicon-germanium intermediate layer, to form grooves |
-
2000
- 2000-03-06 FR FR0002855A patent/FR2805923B1/en not_active Expired - Fee Related
-
2001
- 2001-02-28 EP EP01400507A patent/EP1132955A1/en not_active Withdrawn
- 2001-02-28 US US09/796,116 patent/US6436782B2/en not_active Expired - Lifetime
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US6472287B2 (en) * | 2001-03-08 | 2002-10-29 | Nec Corporation | Manufacturing method of semiconductor with a cleansing agent |
WO2003069663A1 (en) * | 2002-02-12 | 2003-08-21 | Infineon Technologies Ag | Polysilicon bipolar transistor and method for producing the same |
US20050106829A1 (en) * | 2002-02-12 | 2005-05-19 | Infineon Technologies Ag | Polysilicon bipolar transistor and method of manufacturing it |
US7091100B2 (en) | 2002-02-12 | 2006-08-15 | Infineon Technologies Ag | Polysilicon bipolar transistor and method of manufacturing it |
US20030221703A1 (en) * | 2002-06-03 | 2003-12-04 | Nec Electronics Corporation | Method of removing germanium contamination on semiconductor substrate |
JP2007535799A (en) * | 2003-06-24 | 2007-12-06 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Bipolar transistor having high fT and fmax and method of manufacturing the same |
JP2007504647A (en) * | 2003-08-29 | 2007-03-01 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Bipolar transistor having raised extrinsic base with selectable self-alignment and method of forming the same |
US20050205862A1 (en) * | 2004-03-17 | 2005-09-22 | Lam Research Corporation | Dual doped polysilicon and silicon germanium etch |
US7682985B2 (en) * | 2004-03-17 | 2010-03-23 | Lam Research Corporation | Dual doped polysilicon and silicon germanium etch |
TWI456650B (en) * | 2004-03-17 | 2014-10-11 | Lam Res Corp | Methods and apparatus for etching a stack with at least one silicon germanium layer over a substrate and for etching a polysilicon layer over a substrate |
JP2007536724A (en) * | 2004-04-14 | 2007-12-13 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Bipolar device, transistor device, and method of fabricating transistor and bipolar complementary metal oxide semiconductor (BiCMOS) device |
US20100289022A1 (en) * | 2005-11-21 | 2010-11-18 | Nxp B.V. | Method of manufacturing a semiconductor device and semiconductor device obtained with such a method |
US8173511B2 (en) * | 2005-11-21 | 2012-05-08 | Nxp B.V. | Method of manufacturing a semiconductor device and semiconductor device obtained with such a method |
US8992043B2 (en) | 2010-02-15 | 2015-03-31 | Abl Ip Holding Llc | Constructive occlusion lighting system and applications thereof |
Also Published As
Publication number | Publication date |
---|---|
FR2805923A1 (en) | 2001-09-07 |
US6436782B2 (en) | 2002-08-20 |
FR2805923B1 (en) | 2002-05-24 |
EP1132955A1 (en) | 2001-09-12 |
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