US20010052616A1 - Nonvolatile semiconductor storage apparatus and production method of the same - Google Patents

Nonvolatile semiconductor storage apparatus and production method of the same Download PDF

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US20010052616A1
US20010052616A1 US09/154,982 US15498298A US2001052616A1 US 20010052616 A1 US20010052616 A1 US 20010052616A1 US 15498298 A US15498298 A US 15498298A US 2001052616 A1 US2001052616 A1 US 2001052616A1
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conductive type
well
storage apparatus
control gate
nonvolatile semiconductor
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US6392268B2 (en
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Kiyokazu Ishige
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NEC Electronics Corp
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NEC Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a nonvolatile semiconductor storage apparatus such as a flash memory having a floating gate and a control gate to which a positive and negative voltages are applied during a memory cell operation.
  • FIG. 15 to FIG. 17 schematically show a conventional nonvolatile semiconductor storage apparatus of this type.
  • FIG. 17 is a plan view showing the conventional nonvolatile semiconductor storage apparatus.
  • FIG. 15 is a cross sectional view along the line A-A′ in FIG. 17, and
  • FIG. 16 is a cross sectional view along the line B-B′ in FIG. 17. Explanation will be given on this conventional nonvolatile semiconductor storage apparatus with reference to these drawings.
  • a P-type semiconductor substrate 1 there is formed an N-type well 2 to oppose to the P-type semiconductor substrate 1 .
  • a P-type well 3 to oppose to the N-type well 2 .
  • the P-type well 3 has a main surface on which a composite gate 8 is formed.
  • the composite gate 8 consists of a first gate insulation film 4 , a floating gate 5 , a second gate insulation film 6 , and a control gate 7 which are successively layered.
  • a source 10 and a drain 11 are formed by an N + -diffused layer.
  • first inter-layer insulation film 12 and a contact 13 over which a first metal wiring 14 , a second inter-layer insulation film 15 , a second metal wiring 16 , and a cover film 17 are formed.
  • the conventional technology has a problem that a charge-up during wiring layer etching causes a memory cell floating gate to trap an electron or hole, causing characteristic fluctuation and an insulation film reliability lowering or insulation destruction. This is because both of positive and negative voltages are applied to the control gate during a memory cell operation and the control gate cannot be connected to a charge-up preventing diode. That is, if a charge-up preventing diode is connected to the control gate, the charge-up preventing diode is biased in a forward direction by either positive or negative voltage applied and accordingly, it becomes impossible to apply a desired voltage to the control gate.
  • the nonvolatile semiconductor storage apparatus is an improved nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate.
  • the nonvolatile semiconductor storage apparatus is characterized in that a first well of a second conductive type opposite to the first conductive type of the semiconductor substrate is formed on the semiconductor substrate, and in the first well is formed a semiconductor layer of the first conductive type, which semiconductor layer is electrically connected to the control gate.
  • the nonvolatile semiconductor storage apparatus is characterized in that on the semiconductor substrate of a first conductive type is formed a first well of a second conductive type opposite to the first conductive type of the semiconductor substrate, and in the first well is formed a second well of the first conductive type, in which is formed a semiconductor layer of the second conductive type, which semiconductor layer is electrically connected to the control gate. That is , a first well of an opposite conductive type to the semiconductor substrate is formed on the semiconductor substrate. A second well of an opposite conductive type to the first well is formed in the first well, and a semiconductor layer of an opposite conductive type to the second well is formed in the second well. This semiconductor layer is connected to the memory cell control gate so as to realize a charge-up preventing element.
  • the nonvolatile semiconductor storage apparatus production method is an improved production method for producing a nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate.
  • the production method according to a first embodiment is characterized by steps of: forming on the semiconductor substrate of a first conductive type, a semiconductor layer of a second conductive type opposite to the first conductive type; electrically connecting the semiconductor layer to the control gate, and electrically insulating the semiconductor layer from the control gate during or after a wiring layer etching.
  • the nonvolatile semiconductor storage apparatus production method is characterized by steps of: forming on the semiconductor substrate of a first conductive type, a semiconductor layer of a second conductive type opposite to the first conductive type; electrically connecting the semiconductor layer to the control gate using a wiring, and cutting off the wiring connecting the semiconductor layer to the control gate during or after a wiring layer etching.
  • the memory cell control gate is connected to the charge-up preventing diode and during a final wiring layer etching, the control gate is cut off from the charge-up preventing diode.
  • the charge-up preventing element for preventing charge-up during a wiring layer etching assures an electric flow path, enabling to prevent a charge-up which may cause a memory cell characteristic fluctuation and an insulation film reliability lowering or insulation destruction as well as to enable to apply both of positive and negative voltages during a cell operation.
  • an N-type well is formed on a P-type substrate.
  • a P-type well In the N-type well is formed a P-type well.
  • a N + diffusion layer is formed in the P-type well. This N + diffusion layer is connected to the control gate, whereas the P-type substrate and the N-type well are grounded.
  • the direction from the P-type well to the N-type well is a forward direction, and because the N-type well is grounded, it is possible to realize a diode having the N + diffusion layer in the P-type well, assuring a current flow path.
  • a direction from the N+ diffusion layer to the P-type well is a forward bias, thus enabling to realize a diode having the P-type well in the N-type well, assuring a current flow path.
  • FIG. 1 is a cross sectional view along a line A-A′ in FIG. 3 showing a nonvolatile semiconductor storage apparatus according to a first embodiment of the present invention.
  • FIG. 2 is a cross sectional view along a line B-B′ in FIG. 3 showing the nonvolatile semiconductor storage apparatus according to the first embodiment of the present invention.
  • FIG. 3 is a plan view showing the nonvolatile semiconductor storage apparatus according to the first embodiment of the present invention.
  • FIG. 4 is a cross sectional view along a line A-A′ in FIG. 6 showing a wiring layer etching in the first embodiment.
  • FIG. 5 is a cross sectional view along a line B-B′ in FIG. 6 showing the wiring layer etching in the first embodiment.
  • FIG. 6 is a plan view showing wiring layer etching in the first embodiment.
  • FIG. 7 is a cross sectional view along a line A-A′ in FIG. 9 showing a specific example of the first embodiment.
  • FIG. 8 is a cross sectional view along a line B-B′ in FIG. 9 showing the specific example of the first embodiment.
  • FIG. 9 is a plan view showing the specific example of the first embodiment.
  • FIG. 10 is a cross sectional view along a line A-A′ in FIG. 12 showing a wiring layer etching in a specific example
  • FIG. 11 is a cross sectional view along a line B-B′ in FIG. 12 showing the wiring layer etching in the specific example.
  • FIG. 12 is a plan view showing the wiring layer etching in the specific example.
  • FIG. 13 is a cross sectional view along a line B-B′ in FIG. 14 showing a nonvolatile semiconductor storage apparatus according to a second embodiment of the present invention.
  • FIG. 14 is a plan view showing the nonvolatile semiconductor storage apparatus according to the second embodiment of the present invention.
  • FIG. 15 is a cross sectional view along a line A-A′ in FIG. 17 showing a conventional nonvolatile semiconductor storage apparatus.
  • FIG. 16 is a cross sectional view along a line B-B′ in FIG. 17 showing the conventional nonvolatile semiconductor storage apparatus.
  • FIG. 17 is a plan view showing the conventional nonvolatile semiconductor storage apparatus.
  • FIG. 1 to FIG. 3 schematically show a nonvolatile semiconductor storage apparatus according to a first embodiment of the present invention.
  • FIG. 1 is a cross sectional view along a line A-A′ in FIG. 3
  • FIG. 2 is a cross sectional view along a line B-B 2 in FIG. 3.
  • FIG. 3 is a plan view showing the nonvolatile semiconductor storage apparatus according to the first embodiment.
  • a first well 52 of second conductive type which is opposite to the first conductive type is formed.
  • a second well 53 of the first conductive type is formed.
  • a composite gate 8 is formed by a first gate insulation film 4 , a floating gate 5 , a second gate insulation film 6 , and a control gate 7 which are successively layered.
  • a source 10 , a drain 11 , and a charge-up preventing element diffusion layer 18 of the second conductive type are formed by ion implantation.
  • first inter-layer insulation film 12 and a contact 13 are partially covered by a fist metal wiring 14 , a second inter-layer insulation film 15 , a second metal wiring 16 , and a cover film 17 , thus constituting a nonvolatile semiconductor storage apparatus.
  • control gate 7 is connected to the charge-up preventing element diffusion layer 18 by the first metal wiring 14 .
  • the first metal wiring 14 is connected to the second metal wiring 16 .
  • the semiconductor substrate 51 and the first well 52 are grounded.
  • FIG. 4 to FIG. 6 schematically shows a wiring layer etching process according to this embodiment.
  • FIG. 4 is a cross sectional view along a line A-A′ in FIG. 6, and
  • FIG. 5 is a cross sectional view along a line B-B′ in FIG. 6.
  • FIG. 6 is a plan view.
  • the semiconductor substrate 51 and the second well. 53 are of the first conductive type, whereas the first well 52 and the charge-up preventing element diffusion layer 18 are of the second conductive type.
  • the semiconductor substrate 51 and the fist well 52 are grounded. Accordingly, when a forward direction voltage is applied from the diffusion layer 18 to the second well 53 at a charge-up during the wiring layer etching, the second well 53 and the first well 52 function as a charge-up preventing diode (FIG. 4).
  • FIG. 7 to FIG. 9 schematically show a specific example of the present embodiment.
  • FIG. 7 is a cross sectional view along a line A-A′ in FIG. 9, and
  • FIG. 8 is a cross sectional view along a line B-B′ in FIG. 9.
  • FIG. 9 is a plan view.
  • a P-type semiconductor substrate 1 In a P-type semiconductor substrate 1 , an N-type well 2 of the opposite conductive type to the P-type semiconductor substrate 1 is formed. In the N-type well, a P-type well 3 is formed to oppose to the N-type conductivity. On a main surface of the P-type well 3 is formed a composite gate 8 consisting of: a first gate insulation film 4 having a thickness in the order of 100 Angstrom, a floating gate 5 having a thickness in the order of 1000 Angstrom, a second gate insulation film 6 having a thickness of 150 Angstrom, and a control gate 7 having a thickness in the order of 2000 Angstrom which are successively layered.
  • a source 10 , a drain 11 , and a charge-up preventing element diffusion layer 18 are formed by way of ion implantation.
  • first inter-layer insulation film 12 having a thickness in the order of 7000 Angstrom and a contact 13 , on which are further formed successively a first metal wiring 14 having a thickness in the order of 5000 angstrom, a second inter-layer insulation film 15 having a thickness in the order of 6000 Angstrom, a second metal wiring 16 having a thickness in the order of 7000 Angstrom, and a cover film 17 having a thickness in the order of 9000 Angstrom, thus forming a flash memory.
  • control gate 7 is connected to the charge-up preventing element diffusion layer 18 by the first metal wiring 14 .
  • the first metal wiring 14 is connected to the second metal wiring 16 .
  • the P-type semiconductor substrate 1 and the N-type well 2 are grounded.
  • FIG. 10 to FIG. 12 schematically show a wiring layer etching process in the present embodiment.
  • FIG. 10 is a cross sectional view along a line A-A′ in FIG. 12, and
  • FIG. 11 is a cross sectional view along a line B-B 7 in FIG. 12.
  • FIG. 12 is a plan view.
  • the P-type semiconductor substrate 1 and the P-type well 3 are of an identical conductive type, whereas the N-type well 2 and the charge-up preventing element diffusion layer 18 are of another identical conductive type.
  • the semiconductor substrate 1 and the N-type well 2 are grounded. Accordingly, when a forward direction voltage is applied from the diffusion layer 18 to the P-type well 3 at a charge-up during the wiring layer etching, the P-type well 3 and the N-type well 2 function as a charge-up preventing diode (FIG. 10).
  • FIG. 13 and FIG. 14 schematically show a nonvolatile semiconductor storage apparatus according to a second embodiment of the present invention.
  • FIG. 13 is a cross sectional view along a line B-B′ in FIG. 14.
  • FIG. 14 is a plan view.
  • Like components as in the first embodiment are denoted by like symbols and their explanations will be omitted.
  • a charge-up preventing diode used when only positive or negative voltage is applied to the control gate 7 during a memory cell operation, and a current path is assured to prevent a charge-up.
  • the control gate 7 is cut off from the charge-up preventing diode in a memory cell. This enables to apply both of positive and negative voltages during a memory cell operation as well as to prevent charge-up during a wiring layer etching.
  • control gate 7 from the charge-up preventing diode in a memory cell may be carried out other than in the final wiring layer etching step such as in a cut-off dedicated etching process.
  • the present invention enables to prevent trap of electron or hole in a memory cell floating gate due to charge-up during a wiring layer etching. This enables to prevent memory cell characteristic fluctuation and insulation film reliability lowering or insulation destruction.
  • a charge-up preventing element is provided so that no operation trouble is caused even if both positive and negative voltages are applied to the memory cell control gate.
  • This charge-up preventing element is connected to the control gate or a charge-up preventing diode is connected to the control gate through a wiring layer, which are later cut-off from each other during an etching such as in the final wiring layer etching.
  • etching such as in the final wiring layer etching.

Abstract

The present invention prevents a charge-up during a wiring layer etching in a nonvolatile semiconductor storage apparatus having a floating gate and a control gate to which both of positive and negative voltages are applied during a memory cell operation.
On a semiconductor substrate 51 of a first conductive type, a first well 52 of a second conductive type is formed to oppose to the first conductive type. In the first well 52, a second well 53 of the first conductive type is formed. On a main surface of the second well 53 is formed a composite gate 8 consisting of a first gate insulation film 4, a floating gate 5, a second gate insulation film 6, and a control gate 7 which are successively layered. On a surface of the second well 53 are formed by way of ion implantation, a source, a drain, and a charge-up preventing element diffusion layer 18 of the second conductive type.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a nonvolatile semiconductor storage apparatus such as a flash memory having a floating gate and a control gate to which a positive and negative voltages are applied during a memory cell operation. [0002]
  • 2. Description of the Related Art [0003]
  • FIG. 15 to FIG. 17 schematically show a conventional nonvolatile semiconductor storage apparatus of this type. FIG. 17 is a plan view showing the conventional nonvolatile semiconductor storage apparatus. FIG. 15 is a cross sectional view along the line A-A′ in FIG. 17, and FIG. 16 is a cross sectional view along the line B-B′ in FIG. 17. Explanation will be given on this conventional nonvolatile semiconductor storage apparatus with reference to these drawings. [0004]
  • In a P-[0005] type semiconductor substrate 1, there is formed an N-type well 2 to oppose to the P-type semiconductor substrate 1. In the N-type well 2, there is formed a P-type well 3 to oppose to the N-type well 2. The P-type well 3 has a main surface on which a composite gate 8 is formed. The composite gate 8 consists of a first gate insulation film 4, a floating gate 5, a second gate insulation film 6, and a control gate 7 which are successively layered. On a surface of the P-type well 3 adjacent to the composite gate 6, a source 10 and a drain 11 are formed by an N+-diffused layer. Moreover, over a part of the P-type well 3, there are formed a first inter-layer insulation film 12 and a contact 13, over which a first metal wiring 14, a second inter-layer insulation film 15, a second metal wiring 16, and a cover film 17 are formed.
  • Moreover, it is known that by connecting the [0006] control gate 7 to a diode through a wiring layer, it is possible to prevent a charge-up during an etching. However, in this type of nonvolatile semiconductor storage apparatus, both positive and negative voltages are applied to the control gate 7 during a memory cell operation. Accordingly, it is impossible to connect the control gate 7 to a charge-up preventing diode. Consequently, a charge-up is inevitable for a memory cell having the floating gate 5.
  • The conventional technology has a problem that a charge-up during wiring layer etching causes a memory cell floating gate to trap an electron or hole, causing characteristic fluctuation and an insulation film reliability lowering or insulation destruction. This is because both of positive and negative voltages are applied to the control gate during a memory cell operation and the control gate cannot be connected to a charge-up preventing diode. That is, if a charge-up preventing diode is connected to the control gate, the charge-up preventing diode is biased in a forward direction by either positive or negative voltage applied and accordingly, it becomes impossible to apply a desired voltage to the control gate. [0007]
    • SUMMARY OF THE INVENTION
  • It is therefore an object of the present invention to provide a nonvolatile semiconductor storage apparatus having a floating gate and a control gate to which both of positive and negative voltages are applied during a memory cell operation, which apparatus enables to prevent characteristic fluctuation and insulation film reliability lowering or insulation destruction due to charge-up during a wiring layer etching. The nonvolatile semiconductor storage apparatus according to the invention is an improved nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate. The nonvolatile semiconductor storage apparatus according to a first embodiment of the present invention is characterized in that a first well of a second conductive type opposite to the first conductive type of the semiconductor substrate is formed on the semiconductor substrate, and in the first well is formed a semiconductor layer of the first conductive type, which semiconductor layer is electrically connected to the control gate. [0008]
  • The nonvolatile semiconductor storage apparatus according to a second embodiment of the present invention is characterized in that on the semiconductor substrate of a first conductive type is formed a first well of a second conductive type opposite to the first conductive type of the semiconductor substrate, and in the first well is formed a second well of the first conductive type, in which is formed a semiconductor layer of the second conductive type, which semiconductor layer is electrically connected to the control gate. That is , a first well of an opposite conductive type to the semiconductor substrate is formed on the semiconductor substrate. A second well of an opposite conductive type to the first well is formed in the first well, and a semiconductor layer of an opposite conductive type to the second well is formed in the second well. This semiconductor layer is connected to the memory cell control gate so as to realize a charge-up preventing element. [0009]
  • The nonvolatile semiconductor storage apparatus production method according to the present invention is an improved production method for producing a nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate. The production method according to a first embodiment is characterized by steps of: forming on the semiconductor substrate of a first conductive type, a semiconductor layer of a second conductive type opposite to the first conductive type; electrically connecting the semiconductor layer to the control gate, and electrically insulating the semiconductor layer from the control gate during or after a wiring layer etching. [0010]
  • The nonvolatile semiconductor storage apparatus production method according to a second embodiment is characterized by steps of: forming on the semiconductor substrate of a first conductive type, a semiconductor layer of a second conductive type opposite to the first conductive type; electrically connecting the semiconductor layer to the control gate using a wiring, and cutting off the wiring connecting the semiconductor layer to the control gate during or after a wiring layer etching. In other words, the memory cell control gate is connected to the charge-up preventing diode and during a final wiring layer etching, the control gate is cut off from the charge-up preventing diode. [0011]
  • According to the present invention, the charge-up preventing element for preventing charge-up during a wiring layer etching assures an electric flow path, enabling to prevent a charge-up which may cause a memory cell characteristic fluctuation and an insulation film reliability lowering or insulation destruction as well as to enable to apply both of positive and negative voltages during a cell operation. [0012]
  • More specifically, an N-type well is formed on a P-type substrate. In the N-type well is formed a P-type well. In the P-type well, a N[0013] + diffusion layer is formed. This N+ diffusion layer is connected to the control gate, whereas the P-type substrate and the N-type well are grounded. When a charge-up during a wiring layer etching has caused a positive voltage applied to the aforementioned N+ diffusion layer, the direction from the P-type well to the N-type well is a forward direction, and because the N-type well is grounded, it is possible to realize a diode having the N+ diffusion layer in the P-type well, assuring a current flow path. Moreover, when a charge-up during a wiring layer etching has caused a negative voltage applied to the aforementioned N+ diffusion layer, a direction from the N+ diffusion layer to the P-type well is a forward bias, thus enabling to realize a diode having the P-type well in the N-type well, assuring a current flow path.
  • Moreover, in a case when the charge-up preventing diode is connected to the control gate and during etching of a final wiring layer or the like, the control gate is cut off from the charge-up preventing diode, it is possible to assure a current flow path with the charge-up preventing diode and disconnection of the charge-up preventing diode by etching such as a final wiring layer etching enables to apply both of positive and negative voltages during a memory cell operation.[0014]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross sectional view along a line A-A′ in FIG. 3 showing a nonvolatile semiconductor storage apparatus according to a first embodiment of the present invention. [0015]
  • FIG. 2 is a cross sectional view along a line B-B′ in FIG. 3 showing the nonvolatile semiconductor storage apparatus according to the first embodiment of the present invention. [0016]
  • FIG. 3 is a plan view showing the nonvolatile semiconductor storage apparatus according to the first embodiment of the present invention. [0017]
  • FIG. 4 is a cross sectional view along a line A-A′ in FIG. 6 showing a wiring layer etching in the first embodiment. [0018]
  • FIG. 5 is a cross sectional view along a line B-B′ in FIG. 6 showing the wiring layer etching in the first embodiment. [0019]
  • FIG. 6 is a plan view showing wiring layer etching in the first embodiment. [0020]
  • FIG. 7 is a cross sectional view along a line A-A′ in FIG. 9 showing a specific example of the first embodiment. [0021]
  • FIG. 8 is a cross sectional view along a line B-B′ in FIG. 9 showing the specific example of the first embodiment. [0022]
  • FIG. 9 is a plan view showing the specific example of the first embodiment. [0023]
  • FIG. 10 is a cross sectional view along a line A-A′ in FIG. 12 showing a wiring layer etching in a specific example [0024]
  • FIG. 11 is a cross sectional view along a line B-B′ in FIG. 12 showing the wiring layer etching in the specific example. [0025]
  • FIG. 12 is a plan view showing the wiring layer etching in the specific example. [0026]
  • FIG. 13 is a cross sectional view along a line B-B′ in FIG. 14 showing a nonvolatile semiconductor storage apparatus according to a second embodiment of the present invention. [0027]
  • FIG. 14 is a plan view showing the nonvolatile semiconductor storage apparatus according to the second embodiment of the present invention. [0028]
  • FIG. 15 is a cross sectional view along a line A-A′ in FIG. 17 showing a conventional nonvolatile semiconductor storage apparatus. [0029]
  • FIG. 16 is a cross sectional view along a line B-B′ in FIG. 17 showing the conventional nonvolatile semiconductor storage apparatus. [0030]
  • FIG. 17 is a plan view showing the conventional nonvolatile semiconductor storage apparatus.[0031]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Description will now be directed to embodiments of the present invention with reference to the attached drawings. [0032]
  • FIG. 1 to FIG. 3 schematically show a nonvolatile semiconductor storage apparatus according to a first embodiment of the present invention. FIG. 1 is a cross sectional view along a line A-A′ in FIG. 3, and FIG. 2 is a cross sectional view along a [0033] line B-B 2 in FIG. 3. FIG. 3 is a plan view showing the nonvolatile semiconductor storage apparatus according to the first embodiment. Hereinafter, an explanation will be given with reference to these drawings.
  • On a [0034] semiconductor substrate 51 of a first conductive type, a first well 52 of second conductive type which is opposite to the first conductive type is formed. In the first well 52, a second well 53 of the first conductive type is formed. On a main surface of the second well 53, a composite gate 8 is formed by a first gate insulation film 4, a floating gate 5, a second gate insulation film 6, and a control gate 7 which are successively layered. On the surface of the second well 53 adjacent to the composite gate 8 and in a portion to become a charge-up preventing element diffusion layer, a source 10, a drain 11, and a charge-up preventing element diffusion layer 18 of the second conductive type are formed by ion implantation. These are partially covered by a first inter-layer insulation film 12 and a contact 13, on which are further formed successively a fist metal wiring 14, a second inter-layer insulation film 15, a second metal wiring 16, and a cover film 17, thus constituting a nonvolatile semiconductor storage apparatus.
  • Moreover, the [0035] control gate 7 is connected to the charge-up preventing element diffusion layer 18 by the first metal wiring 14. The first metal wiring 14 is connected to the second metal wiring 16. The semiconductor substrate 51 and the first well 52 are grounded.
  • It should be noted that in this embodiment, two metal wiring layers are provided, but it is also possible to provide a single or three or more metal wiring layers. [0036]
  • FIG. 4 to FIG. 6 schematically shows a wiring layer etching process according to this embodiment. FIG. 4 is a cross sectional view along a line A-A′ in FIG. 6, and FIG. 5 is a cross sectional view along a line B-B′ in FIG. 6. FIG. 6 is a plan view. Hereinafter, explanation will be given on the function of the present embodiment with reference to these embodiments. [0037]
  • The [0038] semiconductor substrate 51 and the second well. 53 are of the first conductive type, whereas the first well 52 and the charge-up preventing element diffusion layer 18 are of the second conductive type. The semiconductor substrate 51 and the fist well 52 are grounded. Accordingly, when a forward direction voltage is applied from the diffusion layer 18 to the second well 53 at a charge-up during the wiring layer etching, the second well 53 and the first well 52 function as a charge-up preventing diode (FIG. 4). Moreover, when a reverse direction voltage is caused by charge-up from the diffusion layer 18 to the second well 53, a forward direction current flows from the second well 53 to the first well 52 and accordingly, the diffusion layer 18 and the second well 53 function as a charge-up preventing diode (FIG. 5.).
  • FIG. 7 to FIG. 9 schematically show a specific example of the present embodiment. FIG. 7 is a cross sectional view along a line A-A′ in FIG. 9, and FIG. 8 is a cross sectional view along a line B-B′ in FIG. 9. FIG. 9 is a plan view. Hereinafter, explanation will be given with reference to these drawings. [0039]
  • In a P-[0040] type semiconductor substrate 1, an N-type well 2 of the opposite conductive type to the P-type semiconductor substrate 1 is formed. In the N-type well, a P-type well 3 is formed to oppose to the N-type conductivity. On a main surface of the P-type well 3 is formed a composite gate 8 consisting of: a first gate insulation film 4 having a thickness in the order of 100 Angstrom, a floating gate 5 having a thickness in the order of 1000 Angstrom, a second gate insulation film 6 having a thickness of 150 Angstrom, and a control gate 7 having a thickness in the order of 2000 Angstrom which are successively layered. On the surface of the P-type well 3 adjacent to the composite gate 8 and in a portion to become a charge-up preventing element diffusion layer, a source 10, a drain 11, and a charge-up preventing element diffusion layer 18 are formed by way of ion implantation. These are partially covered by a first inter-layer insulation film 12 having a thickness in the order of 7000 Angstrom and a contact 13, on which are further formed successively a first metal wiring 14 having a thickness in the order of 5000 angstrom, a second inter-layer insulation film 15 having a thickness in the order of 6000 Angstrom, a second metal wiring 16 having a thickness in the order of 7000 Angstrom, and a cover film 17 having a thickness in the order of 9000 Angstrom, thus forming a flash memory.
  • Moreover, the [0041] control gate 7 is connected to the charge-up preventing element diffusion layer 18 by the first metal wiring 14. The first metal wiring 14 is connected to the second metal wiring 16. Moreover, the P-type semiconductor substrate 1 and the N-type well 2 are grounded.
  • FIG. 10 to FIG. 12 schematically show a wiring layer etching process in the present embodiment. FIG. 10 is a cross sectional view along a line A-A′ in FIG. 12, and FIG. 11 is a cross sectional view along a line B-B[0042] 7 in FIG. 12. FIG. 12 is a plan view. Hereinafter, explanation will be given on the function of the present embodiment with reference to these drawings.
  • The P-[0043] type semiconductor substrate 1 and the P-type well 3 are of an identical conductive type, whereas the N-type well 2 and the charge-up preventing element diffusion layer 18 are of another identical conductive type. The semiconductor substrate 1 and the N-type well 2 are grounded. Accordingly, when a forward direction voltage is applied from the diffusion layer 18 to the P-type well 3 at a charge-up during the wiring layer etching, the P-type well 3 and the N-type well 2 function as a charge-up preventing diode (FIG. 10). Moreover, when a reverse direction voltage is caused by the charge-up from the diffusion layer 18 to the P-type well 53, a forward direction current flows from the P-type well 3 to the N-type well 2 and accordingly, the diffusion layer 18 and the P-type well 3 function as a charge-up preventing diode (FIG. 11.).
  • FIG. 13 and FIG. 14 schematically show a nonvolatile semiconductor storage apparatus according to a second embodiment of the present invention. FIG. 13 is a cross sectional view along a line B-B′ in FIG. 14. FIG. 14 is a plan view. Hereinafter, an explanation will be given with reference to these drawings. Like components as in the first embodiment (FIG. 1 to FIG. 3) are denoted by like symbols and their explanations will be omitted. [0044]
  • In the second embodiment, in order to prevent the charge-up during a wiring layer etching, there is provided a charge-up preventing diode used when only positive or negative voltage is applied to the [0045] control gate 7 during a memory cell operation, and a current path is assured to prevent a charge-up. In the etching of the final wiring layer, the control gate 7 is cut off from the charge-up preventing diode in a memory cell. This enables to apply both of positive and negative voltages during a memory cell operation as well as to prevent charge-up during a wiring layer etching.
  • It should be noted that the aforementioned cut-off of the [0046] control gate 7 from the charge-up preventing diode in a memory cell may be carried out other than in the final wiring layer etching step such as in a cut-off dedicated etching process.
  • In a nonvolatile semiconductor storage apparatus such as a flash memory having a control gate to which both of positive and negative voltages are applied, the present invention enables to prevent trap of electron or hole in a memory cell floating gate due to charge-up during a wiring layer etching. This enables to prevent memory cell characteristic fluctuation and insulation film reliability lowering or insulation destruction. [0047]
  • This merit of the present invention is realized as follows. A charge-up preventing element is provided so that no operation trouble is caused even if both positive and negative voltages are applied to the memory cell control gate. This charge-up preventing element is connected to the control gate or a charge-up preventing diode is connected to the control gate through a wiring layer, which are later cut-off from each other during an etching such as in the final wiring layer etching. Thus, it is possible to prevent a charge-up to the memory cell during a wiring layer etching, and to apply both of positive and negative voltages during a memory cell operation. [0048]
  • The invention may be embodied in other specific forms without departing from the spirit or essential characteristic thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. [0049]
  • The entire disclosure of Japanese Patent Application No. 9-255697 (Filed on Sep. 19[0050] th, 1997) including specification, claims, drawings and summary are incorporated herein by reference in its entirety.

Claims (14)

What is claimed is:
1. A nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate of a first conductive type,
wherein a first well of a second conductive type opposite to said first conductive type of said semiconductor substrate is formed on said semiconductor substrate, and in said first well is formed a semiconductor layer of said first conductive type, which semiconductor layer is electrically connected to said control gate.
2. A nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate of a first conductive type,
wherein a first well of a second conductive type opposite to said first conductive type of said semiconductor substrate is formed on said semiconductor substrate, and in said first well is formed a second well of said first conductive type, in which second well is formed a semiconductor layer of said second conductive type, said semiconductor layer being electrically connected to said control gate.
3. A nonvolatile semiconductor storage apparatus as claimed in
claim 2
, wherein said semiconductor substrate and said first well are grounded and said second well is floating or grounded.
4. A method for producing a nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate, said method comprising steps of:
forming on said semiconductor substrate of a first conductive type, a semiconductor layer of a second conductive type opposite to the first conductive type electrically connecting said semiconductor layer to said control gate, and
electrically insulating said semiconductor layer from said control gate during a wiring layer etching.
5. A method for producing a nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate of, said method comprising steps of:
forming on said semiconductor substrate of a first conductive type, a semiconductor layer of a second conductive type opposite to the first conductive type
electrically connecting said semiconductor layer to said control gate, and
electrically insulating said semiconductor layer from said control gate after a wiring layer etching.
6. A method for producing a nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate of, said method comprising steps of:
forming on said semiconductor substrate of a first conductive type, a semiconductor layer of a second conductive type opposite to the first conductive type
electrically connecting said semiconductor layer to said control gate using a wiring, and
cutting off said wiring connecting said semiconductor layer to said control gate during a wiring layer etching.
7. A method for producing a nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate of, said method comprising steps of:
forming on said semiconductor substrate of a first conductive type, a semiconductor layer of a second conductive type opposite to the first conductive type
electrically connecting said semiconductor layer to said control gate using a wiring, and
cutting off said wiring connecting said semiconductor layer to said control gate after a wiring layer etching.
8. A nonvolatile semiconductor storage apparatus as claimed in
claim 1
, wherein said nonvolatile semiconductor storage apparatus is a flash memory.
9. A nonvolatile semiconductor storage apparatus as claimed in
claim 2
, wherein said nonvolatile semiconductor storage apparatus is a flash memory.
10. A nonvolatile semiconductor storage apparatus as claimed in
claim 3
, wherein said nonvolatile semiconductor storage apparatus is a flash memory.
11. A method as claimed in
claim 4
, wherein said nonvolatile semiconductor storage apparatus is a flash memory.
12. A method as claimed in
claim 5
, wherein said nonvolatile semiconductor storage apparatus is a flash memory.
13. A method as claimed in
claim 6
, wherein said nonvolatile semiconductor storage apparatus is a flash memory.
14. A method as claimed in
claim 7
, wherein said nonvolatile semiconductor storage apparatus is a flash memory.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060278918A1 (en) * 2005-05-30 2006-12-14 Yoko Inoue Semiconductor device and method for fabricating the same
US8928056B2 (en) 2010-02-25 2015-01-06 Panasonic Intellectual Property Management Co., Ltd. Nonvolatile semiconductor memory device

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100363841B1 (en) * 1999-12-28 2002-12-06 주식회사 하이닉스반도체 Flash memory device
US6620673B1 (en) * 2002-03-08 2003-09-16 Alpine Microsystems, Inc. Thin film capacitor having multi-layer dielectric film including silicon dioxide and tantalum pentoxide
JP2006024598A (en) * 2004-07-06 2006-01-26 Fujitsu Ltd Method for manufacturing semiconductor device
KR100857741B1 (en) 2006-10-02 2008-09-10 삼성전자주식회사 Nonvolitile memory device and method for the same
US20090179247A1 (en) * 2008-01-16 2009-07-16 Renesas Technology Corp. Semiconductor device
JP5259246B2 (en) 2008-05-09 2013-08-07 ルネサスエレクトロニクス株式会社 Semiconductor device
US8816438B2 (en) * 2012-12-14 2014-08-26 Spansion Llc Process charging protection for split gate charge trapping flash

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57100768A (en) * 1980-12-16 1982-06-23 Nec Corp Manufacture of field effect semiconductor device
JPH0724261B2 (en) * 1989-01-20 1995-03-15 株式会社東芝 Method for manufacturing semiconductor device
JPH02297960A (en) * 1989-05-12 1990-12-10 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
US5243559A (en) 1990-12-12 1993-09-07 Nippon Steel Corporation Semiconductor memory device
DE69312676T2 (en) 1993-02-17 1997-12-04 Sgs Thomson Microelectronics Process for the production of integrated components including non-volatile memory and transistors with tunnel oxide protection
JPH07244991A (en) * 1994-03-01 1995-09-19 Sony Corp Floating gate type non-volatile semiconductor storage device
US5457652A (en) * 1994-04-01 1995-10-10 National Semiconductor Corporation Low voltage EEPROM
US5424233A (en) * 1994-05-06 1995-06-13 United Microflectronics Corporation Method of making electrically programmable and erasable memory device with a depression
JPH08181284A (en) * 1994-09-13 1996-07-12 Hewlett Packard Co <Hp> Protective element and manufacture thereof
JP3380836B2 (en) * 1995-07-04 2003-02-24 松下電器産業株式会社 MIS semiconductor device and method of manufacturing the same
KR970008496A (en) * 1995-07-04 1997-02-24 모리시다 요이치 MIS semiconductor device, manufacturing method thereof, and diagnostic method thereof
JP3183326B2 (en) * 1996-07-17 2001-07-09 日本電気株式会社 Read-only semiconductor memory device
US5998826A (en) * 1996-09-05 1999-12-07 Macronix International Co., Ltd. Triple well floating gate memory and operating method with isolated channel program, preprogram and erase processes
JP2924832B2 (en) * 1996-11-28 1999-07-26 日本電気株式会社 Method for manufacturing semiconductor device
JPH10173157A (en) * 1996-12-06 1998-06-26 Toshiba Corp Semiconductor device
JPH10200077A (en) 1997-01-08 1998-07-31 Sony Corp Semiconductor device and its manufacturing method
KR100239424B1 (en) * 1997-09-26 2000-01-15 김영환 Electro-static discharge protection circuit
US6060742A (en) * 1999-06-16 2000-05-09 Worldwide Semiconductor Manufacturing Corporation ETOX cell having bipolar electron injection for substrate-hot-electron program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060278918A1 (en) * 2005-05-30 2006-12-14 Yoko Inoue Semiconductor device and method for fabricating the same
US8928056B2 (en) 2010-02-25 2015-01-06 Panasonic Intellectual Property Management Co., Ltd. Nonvolatile semiconductor memory device

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EP0903789A3 (en) 1999-12-08
CN1212466A (en) 1999-03-31
EP0903789A2 (en) 1999-03-24
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JP3221369B2 (en) 2001-10-22
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KR19990029546A (en) 1999-04-26

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